351B CY7C1351B PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737 • Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for Flow-Through operation • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 7.5 ns (for 117-MHz device) — 8.5 ns (for 100-MHz device) — 11.0 ns (for 66-MHz device) — 12.0 ns (for 50-MHz device) • • • • • The CY7C1351B is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1351B is pin/functionally compatible to ZBT SRAMs IDT71V547, MT55L128L36F, and MCM63Z737. All synchronous inputs pass through input registers controlled by the rising edge of the clock.The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). Write operations are controlled by the four Byte Write Select (BWS[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. — 14.0 ns (for 40-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable Standard 100 TQFP and 119 BGA packages Burst Capability—linear or interleaved burst order Low standby power Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CLK CE ADV/LD A[16:0] 36 D Data-In REG. Q 36 17 CEN CE1 CE2 CE3 WE BWS [3:0] Mode CONTROL and WRITE LOGIC 36 128KX36 MEMORY ARRAY 17 DQ[31:0] DP[3:0] OE . Selection Guide 7C1351B-117 7C1351B-100 Maximum Access Time (ns) 7C1351B-66 7C1351B-50 7C1351B-40 7.5 8.5 11.0 12.0 14.0 Maximum Operating Current (mA) Commercial 375 mA 350 mA 250 mA 200 mA 175 mA Maximum CMOS Standby Current (mA) Commercial 5 mA 5 mA 5 mA 5 mA 5 mA Cypress Semiconductor Corporation Document #: 38-05208 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 19, 2002 PRELIMINARY CY7C1351B Pin Configuration A9 A8 81 NC 83 82 NC 84 OE ADV/LD CEN WE CLK VSS VDD CE3 BWS0 BWS1 BWS2 BWS3 85 86 87 88 89 90 91 92 93 94 95 96 CE1 A7 CE2 97 98 99 100 A6 100-Pin TQFP DP2 1 80 DP1 DQ16 2 79 DQ15 DQ17 3 78 DQ14 VDDQ 4 77 VDDQ VSS 5 76 VSS DQ18 6 75 DQ13 DQ19 7 74 DQ12 DQ20 8 73 DQ11 DQ21 9 72 DQ10 VSS 10 71 VSS VDDQ 11 70 VDDQ CY7C1351B 55 VSS VDDQ 27 54 VDDQ DQ30 28 53 DQ1 DQ31 29 52 DQ0 DP3 30 51 DP0 Document #: 38-05208 Rev. *A DNU 50 26 A16 DQ2 VSS 49 DQ3 56 48 57 25 A15 24 DQ29 A14 DQ4 47 58 A13 23 DQ28 46 DQ5 DQ27 A12 59 45 22 A11 VSS DQ26 44 60 A10 21 43 VDDQ VSS DNU 61 42 20 41 DQ6 VDDQ VDD DQ7 62 40 63 19 VSS 18 DQ25 39 DQ24 DNU VDD VSS 38 64 DNU 17 37 VSS A0 65 36 16 A1 VSS VDD 35 66 A2 15 34 VSS VDD A3 67 33 14 A4 DQ8 VSS 32 DQ9 68 A5 69 13 31 12 DQ23 MODE DQ22 Page 2 of 16 PRELIMINARY CY7C1351B Pin Configuration 119-Ball Bump BGA CY7C1351B (128K x 36) - 7 x 17 BGA A B C D E F G H J K L M N P R T U Document #: 38-05208 Rev. *A 1 2 3 4 5 6 7 VDDQ A A 16M A A VDDQ NC CE2 A ADV/LD A CE3 NC NC A A VDD A A NC DQc DPc VSS NC VSS DPb DQb DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS OE VSS DQb VDDQ DQc DQc VDDQ DQd DQc DQc VDD DQd BWSc VSS VSS(1) VSS 8M WE VDD CLK BWSb VSS VSS(1) VSS DQb DQb VDD DQa DQb DQb VDDQ DQa DQd DQd BWSd NC BWSa DQa DQa VDDQ DQd VSS VSS DQa VDDQ DQd DQd VSS CEN A1 VSS DQa DQa DQd DPd VSS A0 VSS DPa DQa NC A MODE VDD VSS A NC NC 64M A A A 32M NC VDDQ TMS TDI TCK TDO DNU VDDQ Page 3 of 16 PRELIMINARY CY7C1351B Pin Definitions Name I/O Description A[16:0] InputSynchronous Address Inputs used to select one of the 133,072 address locations. Sampled at the rising edge of the CLK. BWS[3:0] InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls DQ[31:24] and DP3. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQ[31:0] I/OSynchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DP[3:0] I/OSynchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3. MODE Input Strap pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. VSS Ground Ground for the device. Should be connected to ground of the system. NC - No Connects. Reserved for address inputs for depth expansion. Pins 83 and 84 will be used for 256K and 512K depths respectively. DNU - Do Not Use pins. These pins should be left floating or tied to VSS. Document #: 38-05208 Rev. *A Page 4 of 16 PRELIMINARY Introduction Functional Overview The CY7C1351B is a Synchronous Flow-Through Burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 7.5 ns (117-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BWS[3:0] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2 and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs (A0–A16) is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 7.5 ns (117-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-stated immediately. Burst Read Accesses The CY7C1351B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE Document #: 38-05208 Rev. *A CY7C1351B input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0–A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ[31:0] and DP[3:0]. On the next clock rise the data presented to DQ[31:0] and DP[3:0] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWS[3:0] signals. The CY7C1351B provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1351B is a common I/O device, Data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] and DP[3:0].are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1351B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWS[3:0] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Page 5 of 16 PRELIMINARY CY7C1351B . Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address Used Operation CE CEN ADV/L D WE BWSx CLK Comments Deselected External 1 0 L X X L-H I/Os three-state following next recognized clock. Suspend - X 1 X X X L-H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L-H Address latched. Begin Write External 0 0 0 0 Valid L-H Address latched, data presented two valid clocks later. Burst Read Operation Internal X 0 1 X X L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write Operation Internal X 0 1 X Valid L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS[3:0]. Notes: 1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN=1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05208 Rev. *A Page 6 of 16 PRELIMINARY Interleaved Burst Sequence First Address Second Address Third Address CY7C1351B Linear Burst Sequence Fourth Address First Address Second Address Third Address Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Write Cycle Description[1, 2] Function WE BWS3 BWS2 BWS1 BWS0 Read 1 X X X X Write − No bytes written 0 1 1 1 1 Write Byte 0 − (DQ[7:0] and DP0) 0 1 1 1 0 Write Byte 1 – (DQ[15:8] and DP1) 0 1 1 0 1 Write Bytes 1, 0 0 1 1 0 0 Write Byte 2 − (DQ[23:16] and DP2) 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Byte 3 − (DQ[31:24] and DP3) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0 Document #: 38-05208 Rev. *A Page 7 of 16 PRELIMINARY Maximum Ratings CY7C1351B Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND......... −0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[7] ...................................... −0.5V to VDDQ + 0.5V Com’l Ambient Temperature[8] VDD/VDDQ 0°C to +70°C 3.3V ± 5% DC Input Voltage[7] .................................. −0.5V to VDDQ + 0.5V Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage[7] IX Input Load Current Test Conditions VDD = Min., IOH = –4.0 VDD = Min., IOL = 8.0 mA[9] Unit V 3.135 3.465 V 2.4 Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled ICC VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC V 0.4 V 2.0 VDD + 0.3V V –0.3 0.8 V –5 5 mA –30 30 mA –5 5 mA 8.5-ns cycle, 117 MHz 375 mA 10-ns cycle, 100 MHz 350 mA 15-ns cycle, 66 MHz 250 mA 20-ns cycle, 50 MHz 200 mA 25-ns cycle, 40 MHz 175 mA 8.5-ns cycle, 117 MHz 90 mA 10-ns cycle, 100 MHz 80 mA 15-ns cycle, 66 MHz 60 mA 20-ns cycle, 50 MHz 40 mA 25-ns cycle, 40 MHz 35 mA GND ≤ VI ≤ VDDQ IOZ Automatic CE Power-Down Current—TTL Inputs Max. 3.465 mA[9] Input Current of MODE ISB1 Min. 3.135 ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f =0 All speed grades 5 mA ISB3 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ –0.3V f = fMAX = 1/tCYC 8.5-ns cycle, 117 MHz 80 mA 10-ns cycle, 100 MHz 70 mA 15-ns cycle, 66 MHz 50 mA 20-ns cycle, 50 MHz 40 mA 25-ns cycle, 40 MHz 35 mA Notes: 7. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 8. TA is the case temperature. 9. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads. Document #: 38-05208 Rev. *A Page 8 of 16 PRELIMINARY CY7C1351B Capacitance[10] Parameter Description Test Conditions CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 3.3V CCLK Clock Input Capacitance CI/O Input/Output Capacitance Max. Unit 4 pF 4 pF 4 pF AC Test Loads and Waveforms R = 317Ω 3.3V OUTPUT OUTPUT Z0 = 50Ω RL = 50Ω ALL INPUT PULSES 3.0V 5 pF R = 351Ω GND VL = 1.5V (a) INCLUDING JIG AND SCOPE (b) Thermal Resistance Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Thermal Resistance (Junction to Case) Symbol TQFP Typ. Units Notes ΘJA 28 °C/W 10 ΘJC 4 °C/W 10 Note: 10. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05208 Rev. *A Page 9 of 16 PRELIMINARY CY7C1351B Switching Characteristics Over the Operating Range[11, 12, 13] -117 Parameter Description Min. Max. -100 Min. Max. -66 Min. -50 Max. Min. -40 Max. Min. Max. Unit Clock tCYC Clock Cycle Time 8.5 10.0 FMAX Maximum Operating Frequency tCH Clock HIGH 1.9 1.9 5.0 6.0 7.0 ns tCL Clock LOW 1.9 1.9 5.0 6.0 7.0 ns 117 15 100 20 66 ns 50 40 MHz Output Times tCDV Data Output Valid After CLK Rise 7.5 8.5 11.0 12.0 14.0 ns tEOV OE LOW to Output Valid[10,11] 4.2 5.0 6.0 7.0 8.0 ns tDOH Data Output Hold After CLK Rise 1.5 tCHZ Clock to High-Z[10,11,12,13] 1.5 tCLZ Clock to Low-Z[10,11,12,13] tEOHZ OE HIGH to Output High-Z[10,11,12,13] tEOLZ OE LOW to Output Low-Z[10,11,12,13] 1.5 4.2 3 1.5 1.5 5.0 3 4.2 1.5 5.0 3.0 5.0 1.5 5.0 3.0 6.0 5.0 3.0 7.0 0 0 0 0 ns ns ns 8.0 ns ns Set-up Times tAS Address Set-up Before CLK Rise 2.0 2.0 2.0 2.0 2.0 ns tDS Data Input Set-up Before CLK Rise 2.0 2.0 2.0 2.0 2.5 ns tCENS CEN Set-up Before CLK Rise 2.0 2.0 2.0 2.0 2.5 ns tWES WE, BWSx Set-up Before CLK Rise 2.0 2.0 2.0 2.0 2.5 ns tALS ADV/LD Set-up Before CLK Rise 2.0 2.0 2.0 2.0 2.5 ns tCES Chip Select Set-up 2.0 2.0 2.0 2.0 2.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns tWEH WE, BWSx Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns tALH ADV/LD Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 1.0 1.0 ns Hold Times Notes: 11. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 12. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 13. This parameter is sampled and not 100% tested. tCHZ, tCLZ, tOEV, tEOLZ and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured +200 mV from steady Document #: 38-05208 Rev. *A Page 10 of 16 PRELIMINARY CY7C1351B Switching Waveforms DESELECT DESELECT SUSPEND Read Read Write Read DESELECT Read Read Write Read/Write/Deselect Sequence CLK tCENH tCENS tCH tCL tCENH tCENS tCYC CEN tAS ADDRESS WA2 RA1 RA3 RA4 WA5 RA6 RA7 D5 In Q6 Out tAH WE tWS tWH tCES tCEH CE tCLZ DataIn/Out Device originally deselected tCHZ tDOH Q1 Out tDOH tCHZ D2 In Q3 Out Q4 Out Q7 Out tCDV WE is the combination of WE & BWSx to define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON’T CARE Document #: 38-05208 Rev. *A = UNDEFINED Page 11 of 16 PRELIMINARY CY7C1351B Switching Waveforms (continued) Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Read Burst Read Begin Read Burst Sequences CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWS tWH tWS tWH BWS[3:0] tCES tCEH CE tCLZ tCHZ tDOH DataIn/Out tCDV Device originally deselected Q11a Out Q1+1 Out Q1+2 Out Q1+3 Out tCDV tCLZ tDH D2 In D2+1 In D2+2 In D2+3 In Q3 Out Q3+1 Out tDS The combination of WE & BWS[3:0] defines a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON’T CARE Document #: 38-05208 Rev. *A = UNDEFINED Page 12 of 16 PRELIMINARY CY7C1351B Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/Os tEOLZ Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range A101 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Commercial 117 CY7C1351B-117AC 100 CY7C1351B-100AC 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 66 CY7C1351B-66AC 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 50 CY7C1351B-50AC 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 40 CY7C1351B-40AC 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 117 CY7C1351B-117BGC 100 CY7C1351B-100BGC 119-Lead PBGA (14 x 22 x 2.4 mm) 66 CY7C1351B-66BGC 119-Lead PBGA (14 x 22 x 2.4 mm) 50 CY7C1351B-50BGC 119-Lead PBGA (14 x 22 x 2.4 mm) 40 CY7C1351B-40BGC 119-Lead PBGA (14 x 22 x 2.4 mm) Document #: 38-05208 Rev. *A BG119 119-Lead PBGA (14 x 22 x 2.4 mm) Commercial Page 13 of 16 PRELIMINARY CY7C1351B Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05208 Rev. *A Page 14 of 16 PRELIMINARY CY7C1351B Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05208 Rev. *A Page 15 of 16 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1351B Document History Page Document Title: CY7C1351B 128K x 36 Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05208 ECN NO. Issue Date Orig. of Change ** 115440 05/06/02 DSG Change from Spec number: 38-00691 to 38-05208 *A 121535 11/21/02 DSG Updated package diagram 51-85115 (BG119) to rev. *B REV. Document #: 38-05208 Rev. *A Description of Change Page 16 of 16