CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY 18-Mb DDR-II SIO SRAM Two-word Burst Architecture Features Functional Description • 18-Mb density (2M x 8, 1M x 18, 512K x 36) — Supports concurrent transactions • 250-MHz clock for high bandwidth • Two-word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatches • Echo clocks (CQ and CQ) simplify data capture in high speed systems • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • 13x15 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15 matrix) • JTAG Interface • On-chip Delay Lock Loop (DLL) Configuration CY7C1392V18–2M x 8 CY7C1393V18–1M x18 The CY7C1392V18/CY7C1393V18/CY7C1394V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate DDR ports, Read and Write port, to access the memory array. The Read port has dedicated outputs and the Write port has dedicated inputs to support read and write operations concurrently. Access to each port is accomplished using a common address bus. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392V18, two 18-bit words in the case of CY7C1393V18, and two 36-bit words in the case of CY7C1394V18, that burst sequentially into or out of the device. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K/K input clocks. All data outputs pass through output registers controlled by the C/C input clocks (or K/K in single clock mode). Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C1394V18–512K x 36 Logic Block Diagram (CY7C1392V18) D[7:0] 8 Write Add. Decode Address Register A(19:0) 20 K K CLK Gen. 1M x 8 Memory Array Write Data Reg 1M x 8 Memory Array Read Add. Decode Write Data Reg Control Logic Read Data Reg. R/W VREF LD BWS0 16 8 Reg. 8 Reg. Control Logic 8 Reg. BWS1 Cypress Semiconductor Corporation Document #: 38-05179 Rev. *A 8 • 3901 North First Street • San Jose • LD R/W C C CQ CQ 8 Q[7:0] CA 95134 • 408-943-2600 Revised July 31, 2002 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Logic Block Diagram (CY7C1393V18) 18 19 K CLK Gen. K Write Data Reg 512K x 18 512K x 18 Memory Memory Array Array Read Add. Decode Address Register A(18:0) Write Data Reg Write Add. Decode D[17:0] Control Logic Read Data Reg. R/W VREF LD BWS0 36 CQ CQ 18 Reg. Control Logic LD R/W C C 18 Reg. 18 18 Reg. BWS1 Q[17:0] 18 Logic Block Diagram (CY7C1394V18) 36 18 K K CLK Gen. Write Data Reg 256K x 36 256K x 36 Memory Memory Array Array Read Add. Decode Address Register A(17:0) Write Data Reg Write Add. Decode D[35:0] Control Logic Read Data Reg. R/W VREF LD BWS[3:0] 72 CQ CQ 36 Reg. Control Logic LD R/W C C 36 Reg. 36 36 Reg. Q[35:0] 36 Selection Guide 300 MHz[1] 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 300 250 200 167 MHz Maximum Operating Current TBD TBD TBD TBD mA Note: 1. Shaded cells indicate advanced information. Document #: 38-05179 Rev. *A Page 2 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Pin Configurations CY7C1392V18 (2M x 8) - 11 x 15 FBGA A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 CQ VSS/72M A R/W BWS1 K NC LD A VDD/36M CQ NC NC NC A NC K BWS0 A NC NC Q3 NC NC NC D4 NC A VSS A VSS A VSS VSS VSS NC NC VSS VSS NC NC NC D3 NC NC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC NC DOFF NC D5 VREF NC Q5 VDDQ NC VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC VDDQ NC NC VREF Q1 NC ZQ D1 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 NC NC NC D7 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D0 NC NC NC Q7 A A C A A NC NC NC TDO TCK A A A C A A A TMS TDI CY7C1393V18 (1M x 18) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R CQ 2 3 VSS/144M NC/36M 4 5 6 7 8 9 10 11 R/W BWS1 K NC LD A GND/72M CQ NC Q9 D9 A NC K BWS0 A NC NC Q8 NC NC NC D11 D10 VSS VSS A VSS A VSS A VSS VSS VSS NC Q10 Q7 NC D8 D7 NC NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 NC DOFF NC D13 VREF NC Q13 VDDQ D14 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC VDDQ NC NC VREF Q4 D5 ZQ D4 NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 NC NC NC D17 D16 Q16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC Q1 NC D2 D1 NC NC Q17 A A C A A NC D0 Q0 TDO TCK A A A C A A A TMS TDI Document #: 38-05179 Rev. *A Page 3 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Pin Configurations (continued) CY7C1394V18 (512K x 36) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R CQ 2 3 VSS/288M NC/72M 4 5 6 7 8 R/W BWS2 K BWS1 LD 9 10 11 NC/36M VSS/144M CQ Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 D27 D28 Q28 D20 D19 A VSS A VSS A VSS VSS VSS D16 Q19 VSS VSS Q16 Q7 D15 D8 D7 Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 Q30 D30 DOFF D31 Q21 VDDQ VDDQ VDDQ VDDQ D14 Q13 VDDQ D12 Q14 VSS VSS VSS VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VSS D22 VREF Q31 D21 Q22 VDDQ D23 D13 VREF Q4 Q5 D5 ZQ D4 Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 D33 D34 Q34 D26 D25 Q25 VSS VSS VSS A VSS A VSS A VSS VSS D10 Q10 Q1 D9 D2 D1 Q35 D35 Q26 A A C A A Q9 D0 Q0 TDO TCK A A A C A A A TMS TDI Pin Definitions Pin Name I/O Pin Description D[x:0] InputSynchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1392V18 − DQ[7:0] CY7C1393V18 − DQ[17:0] CY7C1394V18 − DQ[35:0] LD InputSynchronous Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one period of bus activity). BWS[3:0] InputSynchronous Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1392V18 − BWS0 controls D[3:0] and BWS1 controls D[7:4]. CY7C1393V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1394V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputSynchronous Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1392V18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1393V18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1394V18. All the address inputs are ignored when the appropriate port is deselected. Q[x:0] OutputsSynchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. Document #: 38-05179 Rev. *A Page 4 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Pin Definitions (continued) Pin Name I/O Pin Description InputSynchronous Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and hold times around edge of K. C InputClock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C InputClock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K InputClock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K InputClock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ InputClock Positive Output Echo Clock. The rising edge of CQ is synchronous with respect to C (or K in single clock mode) and is used for data valid indication coming off of C (or K) clock. This is a free-running clock. CQ Input-Clock Negative Output Echo Clock. The rising edge of CQ is synchronous with respect to C (or K in single clock mode) and is used for data valid indication coming off of C (or K) clock. This is a free-running clock. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL Turn Off. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDRTM-II.” R/W TDO Output TCK Input TDO for JTAG. TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC/36M Input Address expansion for 36M. This is a No connect on the 18M and could be tied to any level on the 18M devices GND/36M Input Address expansion for 36M. This should be tied LOW on the 18M devices. NC/72M Input Address expansion for 72M. This is a No connect on the 18M and could be tied to any level on the 18M devices VSS/72M Input Address expansion for 72M. This must be tied LOW on the 18M SRAM. VSS/144M Input Address expansion for 144M. This must be tied LOW on the 18M SRAM. VSS/288M Input Address expansion for 288M. This must be tied LOW on the 18M SRAM. VREF InputReference Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as A/C measurement points. VDD Power Supply Power supply inputs to the core of the device. Should be connected to 1.8V power supply. VSS VDDQ NC Ground Power Supply NC Document #: 38-05179 Rev. *A Ground for the device. Should be connected to ground of the system. Power supply inputs for the outputs of the device. Should be connected to 1.5V power supply. No connect. Page 5 of 24 PRELIMINARY Introduction Functional Overview The CY7C1392V18/CY7C1393V18/CY7C1394V18 are synchronous pipelined Burst SRAMs equipped with a DDR-II SIO interface. Accesses are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks, C/C (or K/K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks, C/C (or K/K when in single clock mode). All synchronous control (R/W, LD, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). The following descriptions use CY7C1393V18 as an example. However, the same is true for the other DDR-II SIO SRAMs, CY7C1392V18 and CY7C1394V18. These chips utilize a DLL that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. Read Operations The CY7C1393V18 is organized internally as a 512K x 36 SRAM. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the Positive Input Clock (K). The address presented to the Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest-order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.35 ns from the rising edge of the output clock (C/C, 250-MHz device). Read accesses can be initiated on every K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks, C/C (or K/K when in single clock mode). When the read port is deselected, the CY7C1393V18 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the Positive Output Clock (C). Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. Write accesses can be initiated on every rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Document #: 38-05179 Rev. *A CY7C1392V18 CY7C1393V18 CY7C1394V18 Byte Write Operations Byte Write operations are supported by the CY7C1393V18. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1393V18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. The echo clocks would be synchronized to the input clocks K/K in this mode. Double DDR Operation The CY7C1393V18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double DDR mode of operation. If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The write information must be stored because the SRAM can not perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±10% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the Separate I/O DDR. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Page 6 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Application Example[2] SRAM #1 D CLK/CLK (input) CLK/CLK (output) 18 18 Q VTERM = VREF C/C K/K R/W Add. Q Din Add. R/W LD SRAM #4 D LD C/C K/K R/W. Add. LD 18 Memory Controller Q R = 50Ω 18 72 17 17 72 2 2 R = 50Ω VT = VREF Truth Table[ 3, 4, 5, 6, 7, 8] Operation K LD R/W Write Cycle: Load address; input write data on consecutive K and K rising edges. L-H L L D(A + 0)at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. L-H L H Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑ NOP: No Operation L-H H X High-Z High-Z Stopped X X Previous State Previous State Standby: Clock Stopped DQ DQ Write Cycle Descriptions[3, 9](CY7C1392V18 and CY7C1393V18) BWS0 BWS1 K K - L L L-H L L - L H L-H Comments During the Data portion of a Write sequence : CY7C1392V18 − both nibbles (D[7:0]) are written into the device, CY7C1393V18 − both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence : CY7C1392V18 − both nibbles (D[7:0]) are written into the device, CY7C1393V18 − both bytes (D[17:0]) are written into the device. - During the Data portion of a Write sequence : CY7C1392V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1393V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. Notes: 2. The above application shows 4 CY7C1393V18 being used. This holds true for CY7C1392V18 and CY7C1394V18 as well. 3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 4. Device will power-up deselected and the outputs in a three-state condition. 5. “A” represents address location latched by the devices when transaction was initiated. A+0 and A+1 represents the addresses sequence in the burst. 6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document #: 38-05179 Rev. *A Page 7 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Write Cycle Descriptions[3, 9](CY7C1392V18 and CY7C1393V18) (continued) BWS0 BWS1 K L H - H L L-H H L – H H L-H H H – K Comments L-H During the Data portion of a Write sequence : CY7C1392V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1393V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence : CY7C1392V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1393V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – L-H During the Data portion of a Write sequence : CY7C1392V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1393V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – No data is written into the devices during this portion of a write operation. L-H No data is written into the devices during this portion of a write operation. Write Cycle Descriptions[3, 9](CY7C1394V18) BWS0 BWS1 BWS2 BWS3 K K L L L L L-H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L H H H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. H L H H L-H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H L H H – L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H H L H L-H – During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H L H – L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H H L L-H H H H L – L-H H H H H L-H – No data is written into the device during this portion of a write operation. H H H H – L-H No data is written into the device during this portion of a write operation. Comments During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. Note: 9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1392V18 and CY7C1393V18 and also BWS2, BWS3 in the case of CY7C1394V18can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05179 Rev. *A Page 8 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY DC Input Voltage[12] .............................–0.5V to VDDQ + 0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V DC Voltage Applied to Outputs in High-Z State[12] ............................... –0.5V to VDDQ + 0.5V Range Com’l Ambient Temperature[10] 0°C to +70°C VDD 1.8 ±100 mV VDDQ 1.4V to VDD Electrical Characteristics Over the Operating Range[1, 11] Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage IOH = −2.0 mA, Nominal Impedance VOL Output LOW Voltage IOL = 2.0 mA, Nominal Impedance VIH Input HIGH Voltage[12] [12] VIL Input LOW Voltage IX Input Load Current IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VREF Input Reference Voltage[13] Typical Value = 0.75V IDD VDD Operating Supply x8,x18 IDD ISB1 ISB1 VDD Operating Supply x36 GND ≤ VI ≤ VDDQ Min. Typ. Max. Unit 1.7 1.8 1.9 V 1.4 1.5 VDD V VDDQ – 0.2 VDDQ – 0.2 VDDQ V VSS VSS 0.2 V VREF + 0.1 VREF + 0.1 VDDQ + 0.3 V –0.3 VREF – 0.1 VREF – 0.1 V –5 –5 5 µA –5 –5 5 µA 0.68 0.75 0.95 V VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz TBD mA TBD mA 250 MHz TBD mA 300 MHz TBD mA VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz TBD mA TBD mA 250 MHz TBD mA 300 MHz TBD mA Automatic Power-down Current,x8,x18 Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH or 200 MHz VIN ≤ VIL f = fMAX = 1/tCYC, 250 MHz Inputs Static 300 MHz TBD mA TBD mA TBD mA TBD mA Automatic Power-down Current, x36 Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH or 200 MHz VIN ≤ VIL f = fMAX = 1/tCYC, 250 MHz Inputs Static 300 MHz TBD mA TBD mA TBD mA TBD mA Notes: 10. Ambient Temperature = TA. This is the case temperature. 11. All voltage referenced to ground. 12. Overshoot: VIH(AC) < VDD + 0.5V for t < tTCYC/2; undershoot VIL(AC) < − 0.5V for t < tTCYC/2; power-up: VIH < 1.8V and VDD < 1.8V and VDDQ < 1.4V for t < 200 ms. 13. VREF Min. = 0.68V or 0.46VDDQ, whichever is larger, VREF Max. = 0.95V or 0.54VDDQ, whichever is smaller. Document #: 38-05179 Rev. *A Page 9 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Switching Characteristics Over the Operating Range[1, 14] 300 MHz Parameter Description Min. 250 MHz 200 MHz 167 MHz Max. Min. Max. Min. Max. Min. Max. Unit tCYC K Clock and C Clock Cycle Time 3.3 4.0 4.0 5.0 5.0 6.0 6.0 7.5 ns tKH Input Clock (K/K and C/C) HIGH 1.32 – 1.6 – 2.0 – 3.0 – ns tKL Input Clock (K/K and C/C) LOW 1.32 – 1.6 – 2.0 – 3.0 – ns tKHKH K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge) 1.49 1.82 1.8 – 2.2 – 2.7 – ns tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 1.45 0.0 1.8 0.0 2.3 0.0 2.8 ns Set-up Times tSA Address Set-up to K Clock Rise 0.4 – 0.5 – 0.6 – 0.7 – ns tSC Control Set-up to Clock (K, K, C, C) Rise (RPS, WPS, BWS0, BWS1) 0.4 – 0.5 – 0.6 – 0.7 – ns tSD D[17:0] Set-up to Clock (K and K) Rise 0.3 – 0.4 – 0.5 – 0.6 – ns tHA Address Hold after Clock (K and K) Rise 0.4 – 0.5 – 0.6 – 0.7 – ns tHC Control Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) 0.4 – 0.5 – 0.6 – 0.7 – ns tHD D[17:0] Hold after Clock (K and K) Rise 0.3 – 0.4 – 0.5 – 0.6 – ns Hold Times Output Times tCO C/C Clock Rise (or K/K in single clock mode) to Data Valid[14] – 0.29 – 0.35 – 0.38 – 0.40 ns tDOH Data Output Hold after Output C/C Clock Rise (Active to Active) −0.29 – −0.35 – −0.38 – −0.40 – ns tCCQO C/C Clock Rise to Echo Clock Valid 0.38 ns tCQOH Echo Clock Hold after C/C Clock Rise −0.27 tCQD Echo Clock High to Data Change −0.27 tCLZ Clock (C and C) Rise to Low-Z[15, 16] −0.29 – −0.35 – −0.38 – −0.40 – ns tCHZ Clock (C and C) Rise to High-Z (Active to High-Z)[15, 16] – 0.29 – 0.35 – 0.38 – 0.40 ns tKC Clock Phase Jitter – 0.08 – 0.10 – 0.13 – 0.15 ns tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – cycl es 0.27 0.33 −0.33 0.36 −0.36 −0.38 0.29 −0.33 0.35 −0.36 0.38 −0.38 0.40 DLL Timing Capacitance[17] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. Unit TBD pF TBD pF TBD pF Notes: 14. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 0.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads. 15. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 16. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. Document #: 38-05179 Rev. *A Page 10 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY AC Test Loads and Waveforms VREF = 0.75V VREF 0.75V VREF OUTPUT Z0 = 50Ω Device Under Test RL = 50Ω VREF = 0.75V ZQ 0.75V R = 50Ω ALL INPUT PULSES [14] 1.25V 0.75V OUTPUT Device Under ZQ Test RQ = 250Ω 5 pF RQ = 250Ω 0.25V Slew Rate = 2V / ns (a) INCLUDING JIG AND SCOPE (b) Note: 17. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05179 Rev. *A Page 11 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Switching Waveforms Read/Deselect Sequence Read Read Deselect Read tKHKH Deselect tKL tKHKH K Deselect tCYC tKH tKL K tKH tSA A[17:0] B A C tHA tSC tHC LD tSC tHC R/W Q(A) Q tKHCH C tCLZ Q(A+1) C Q(C) tCO Q(C+1) tCQD tKL tDOH tKHCH Q(B+1) tCQD tCO tKHKH Q(B) tKH tCHZ tKL tKH tCQOH tCCQO CQ tCCQO tCQOH CQ = DON’T CARE Document #: 38-05179 Rev. *A = UNDEFINED Page 12 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Switching Waveforms Write/Deselect Sequence[18, 19] Write Deselect Write Write Deselect tCYC Deselect tKL K tKHKH tKH tKL K tKH tSA tHA A A tSC B C tHC LD tSC tHC R/W tSC tHC BWSx D D(A) D(A+1) D(B) D(B+1) tSD = DON’T CARE D(C) D(C+1) tHD = UNDEFINED Notes: 18. C and C reference to Data Outputs and do not affect Write operations. 19. BWSx LOW = Valid, Byte writes allowed, see Byte write table for details. Document #: 38-05179 Rev. *A Page 13 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Switching Waveforms Read/Write/Deselect Sequence[20, 21] Write Write Read Deselect Read Deselect K K A A B C D LD R/W D[x:0] Q[x:0] D(B) Q(A) D(B+1) D(C) D(C+1) Q(A+1) Q(D) Q(D+1) C C CQ CQ = DON’T CARE = UNDEFINED Notes: 20. Read Port previously deselected. 21. BWSx assumed active during write cycles. Document #: 38-05179 Rev. *A Page 14 of 24 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) The DDRII SIO incorporates a serial boundary scan test access port (TAP) in the FBGA package. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port–Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin Document #: 38-05179 Rev. *A CY7C1392V18 CY7C1393V18 CY7C1394V18 on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of Page 15 of 24 PRELIMINARY CY7C1392V18 CY7C1393V18 CY7C1394V18 SAMPLE/PRELOAD; rather it performs a capture of the Input and Output ring when these instructions are executed. state, a snapshot of data on the input and output pins is captured in the boundary scan register. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that, during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not fully compliant with the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. To guarantee that the boundary scan register will capture the correct value of a signal, he SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). The SRAM clock inputs might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the K, K, C, and C captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. SAMPLE Z Bypass The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR Document #: 38-05179 Rev. *A Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 16 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY TAP Controller State Diagram[22] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 22. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05179 Rev. *A Page 17 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[11, 12, 23, 24] Parameter Description Test Conditions Min. Max. VOH1 Output HIGH Voltage IOH = −2.0 mA VDD–0.45 VOH2 Output HIGH Voltage IOH = −100 µA VDD–0.2 VOL1 Output LOW Voltage IOL = 2.0 mA VOL2 Output LOW Voltage IOL = 100 µA VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and OutputLoad Current GND ≤ VI ≤ VDD Unit V V 0.45 V 0.2 V 0.65VDD VDD + 0.3 V –0.3 0.35VDD V –5 5 µA TAP AC Switching Characteristics Over the Operating Range[25, 26] Parameter Description Min. Max. 100 Unit tTCYC TCK Clock Cycle Time ns tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns 10 MHz Set-up Times tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns Notes: 23. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 24. VDD means core supply voltage. 25. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 26. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05179 Rev. *A Page 18 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[25, 26] Parameter Description Min. Max. Unit Hold Times tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions[26] 0.9V 50Ω ALL INPUT PULSES TDO 1.8V Z0 = 50Ω 0.9V CL = 20 pF 0V (a) GND tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05179 Rev. *A tTDOX Page 19 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Identification Register Definitions Value Instruction Field CY7C1392V18 CY7C1393V18 CY7C1394V18 000 000 000 Revision Number (31:29) Description Version number. Cypress Device ID (28:12) 11010100100000101 11010100100010101 11010100100100101 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 1 Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. This instruction is not 1149.1 compliant. The EXTEST command implemented by these devices will NOT place the output buffers into a high-Z condition. If the output buffers need to be in high-Z condition, this can be accomplished by deselecting the Read port. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. The SAMPLE Z command implemented by these devices will place the output buffers into a high-Z condition. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order Boundary Scan Order Bit # Bump ID Bit # 0 6R 12 9P 1 6P 13 10M 2 6N 14 11N 3 7P 15 9M 4 7N 16 9N 5 7R 17 11L 6 8R 18 11M 7 8P 19 9L 8 9R 20 10L 9 11P 21 11K 10 10P 22 10K 11 10N 23 9J Document #: 38-05179 Rev. *A Bump ID Page 20 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Boundary Scan Order Boundary Scan Order Bit # Bump ID Bit # Bump ID 24 9K 68 1B 25 10J 69 3D 26 11J 70 3C 27 11H 71 1D 28 10G 72 2C 29 9G 73 3E 30 11F 74 2D 31 11G 75 2E 32 9F 76 1E 33 10F 77 2F 34 11E 78 3F 35 10E 79 1G 36 10D 80 1F 37 9E 81 3G 38 10C 82 2G 39 11D 83 1J 40 9C 84 2J 41 9D 85 3K 42 11B 86 3J 43 11C 87 2K 44 9B 88 1K 45 10B 89 2L 46 11A 90 3L 47 10A 91 1M 48 9A 92 1L 49 8B 93 3N 50 7C 94 3M 51 6C 95 1N 52 8A 96 2M 53 7A 97 3P 54 7B 98 2N 55 6B 99 2P 56 6A 100 1P 57 5B 101 3R 58 5A 102 4R 59 4A 103 4P 60 5C 104 5P 61 4B 105 5N 62 3A 106 5R 63 2A 64 1A 65 2B 66 3B 67 1C Document #: 38-05179 Rev. *A Page 21 of 24 CY7C1392V18 CY7C1393V18 CY7C1394V18 PRELIMINARY Ordering Information[1] Speed (MHz) 300 Ordering Code CY7C1392V18-300BZC Package Name Package Type Operating Range BB165A 13 x 15 mm FBGA Commercial BB165A 13 x 15 mm FBGA Commercial BB165A 13 x 15 mm FBGA Commercial BB165A 13 x 15 mm FBGA Commercial CY7C1393V18-300BZC CY7C1394V18-300BZC 250 CY7C1392V18-250BZC CY7C1393V18-250BZC CY7C1394V18-250BZC 200 CY7C1392V18-200BZC CY7C1393V18-200BZC CY7C1394V18-200BZC 167 CY7C1392V18-167BZC CY7C1393V18-167BZC CY7C1394V18-167BZC Document #: 38-05179 Rev. *A Page 22 of 24 PRELIMINARY CY7C1392V18 CY7C1393V18 CY7C1394V18 Package Diagram 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*B QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05179 Rev. *A Page 23 of 24 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1392V18 CY7C1393V18 CY7C1394V18 Document Title: CY7C1392V18/CY7C1393V18/CY7C1394V18 18 Mb DDR-II SIO SRAM with 2-Word Burst Architecture Document Number: 38-05179 ISSUE DATE ORIG. OF CHANGE REV. ECN NO. ** 110858 11/09/01 SKX New Data Sheet *A 115921 08/01/02 RCS Changed status to Preliminary Shaded 300-MHz bin Updated JTAG scan order Document #: 38-05179 Rev. *A DESCRIPTION OF CHANGE Page 24 of 24