398V25 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION 18-Mb 4-Word Burst SRAM with DDR-I Architecture Features Functional Description • 18-Mb Density (2M x 8, 1M x 18, 512K x 36) — Supports concurrent transactions • 300-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @300 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatches • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 1.8V core power supply with HSTL Inputs and Outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–VDD) • 13x15 mm 1.0 mm pitch fBGA package, 165 ball (11x15 matrix) • JTAG Interface Configurations CY7C1398V25 – 1M x 18 The CY7C1398V25/CY7C1323V25 are 2.5V Synchronous Pipelined SRAMs equipped with DDR-I (Double Data Rate) architecture. The DDR-I consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock.Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Every read or write operation is associated with four words that burst sequentially into or out of the device. The burst counter takes in the least two significant bits of the external address and bursts four 18-bit words in the case of CY7C1398V25 and four 36-bit words in the case of CY7C1323V25. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to separately capture data from each individual DDR SRAM in the system design. Output data clocks (C/C) are also provided for maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C1323V25 – 512K x 36 Logic Block Diagram (CY7C1398V25) A(1:0) 18 Write Write Write Write Reg Reg Reg Reg Address Register Read Add. Decode 256K x 18 Array CLK Gen. 256K x 18 Array K K 256K x 18 Array LD 256K x 18 Array Address A(19:2) Register Write Add. Decode A(19:0) 20 20 LD 18 Output Logic Control C C Read Data Reg. VREF R/W BWS[1:0] 72 CQ CQ 36 Reg. Control Logic A(19:0) 36 Reg. 18 Reg. DQ[17:0] 18 Cypress Semiconductor Corporation Document #: 38-05176 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 22, 2001 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Logic Block Diagram (CY7C1323V25) Burst Logic 17 A(18:0) 128K x 36 Array CLK Gen. 128K x 36 Array K K 128K x 36 Array LD Write Write Write Write Reg Reg Reg Reg 128K x 36 Array Address A(19:2) Register Write Add. Decode 19 Read Add. Decode A(1:0) 36 Output Logic Control C C Read Data Reg. VREF R/W BWS[3:0] 144 CQ 72 Reg. Control Logic 72 CQ Reg. 36 Reg. DQ[35:0] 36 Selection Guide 300 MHz 250 MHz 200 MHz 167 MHz Maximum Operating Frequency (MHz) 300 250 200 167 Maximum Operating Current (mA) TBD TBD TBD TBD Document #: 38-05176 Rev. ** Page 2 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Pin Configurations CY7C1398V25 (1M x 18) - 11 x 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P CQ GND/72M A WE BWS1 K NC LD A GND/36M CQ NC DQ9 NC A NC K BWS0 A NC NC DQ8 NC NC NC NC NC VSS A0 VSS A1 VSS VSS VSS NC DQ10 VSS VSS A NC DQ7 NC NC NC NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 NC NC NC NC DQ12 VDDQ VDDQ VDDQ VDDQ NC NC VDDQ NC NC VSS VSS VSS VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VSS NC VREF NC NC DQ13 VDDQ NC NC VREF DQ4 DQ5 NC ZQ NC NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 R NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 NC NC NC NC NC DQ16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC DQ1 NC NC NC NC NC DQ17 A A C A A NC NC DQ0 TDO TCK A A A C A A A TMS TDI CY7C1323V25 (512K x 36) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P CQ R 2 3 GND/144M NC/36M 4 5 6 7 8 9 10 WE BWS2 K A GND/72M 11 CQ BWS1 LD NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8 NC NC NC DQ29 DQ28 DQ19 VSS VSS A VSS A0 VSS A1 VSS VSS VSS NC NC DQ17 NC DQ7 DQ16 NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 NC NC NC DQ31 VREF NC DQ22 VDDQ DQ32 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC VDDQ NC NC VREF DQ13 DQ14 ZQ DQ4 NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 NC NC NC DQ35 DQ34 DQ25 VSS VSS VSS A VSS A VSS A VSS VSS NC NC DQ11 NC DQ1 DQ10 NC NC DQ26 A A C A A NC DQ9 DQ0 TDO TCK A A A C A A A TMS TDI Document #: 38-05176 Rev. ** Page 3 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Pin Definitions Name I/O Description DQ[x:0] Input/OutputSynchronous Data Input/Output signals: Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. CY7C1398V25—DQ[17:0] CY7C1323V25—DQ[35:0] LD InputSynchronous Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods of bus activity). BWS0, BWS1, BWS2, BWS3 InputSynchronous Byte Write Select 0, 1, 2, and 3—active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1398V25—BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1323V25—BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A, A0, A1 InputSynchronous Address inputs. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 1M x 18 4 arrays each of 256K x 18) for CY7C1323V25 and 256K x 36 (4 arrays each of 128K x 36) for CY7C1398V25. CY7C1323V25—A0 and A1 are the inputs to the burst counter. These are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. CY7C1398V25—A0 and A1 are the inputs to the burst counter. These are incremented in a linear fashion internally. 19 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected. R/W InputSynchronous Synchronous Read/Write Input: When LD is LOW, this input designates the access type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the setup and hold times around edge of K. C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. Output-Clock Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals are free running and do not stop when the output data bus (which is shared with the inputs) is three-stated. Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. CQ, CQ ZQ TDO Output TCK Input Document #: 38-05176 Rev. ** TDO for JTAG. TCK pin for JTAG. Page 4 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Pin Definitions (continued) Name I/O Description TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC Input No connects. Can be tied to any voltage level. NC/36M Input Address expansion for 36M. This is not connected to the die. GND/72M Input Address expansion for 72M. This should be tied LOW on the 18M devices. GND/144M Input Address expansion for 144M. This should be tied LOW on the 18M devices. VREF InputReference VDD Power Supply VSS Ground VDDQ Power Supply NC NC Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device. Should be connected to 2.5V power supply. Ground for the device. Should be connected to ground of the system. Power supply inputs for the outputs of the device. Should be connected to 1.5V power supply. No connect Introduction Functional Overview The CY7C1398V25/CY7C1323V25 are synchronous pipelined Burst SRAMs equipped with DDR-I interface. Accesses are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C or K and K when in single clock mode). cess must be allowed to complete. Each Read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, Read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). When the read port is deselected, the CY7C1398V25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. All synchronous control (R/W, LD, BWS0, BWS1) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). Write Operations The following descriptions take CY7C1398V25 as an example. However, the same is true for the other DDR-I SRAM, CY7C1323V25. Read Operations The CY7C1398V25 is organized internally as a 256K x 72 SRAM. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the Positive Input Clock (K). The address presented to the Address inputs is stored in the Read address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 1.8 ns from the rising edge of the output clock (C or C, 300-MHz device). In order to maintain the internal logic, each read acDocument #: 38-05176 Rev. ** Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the Positive Input Clock (K). The address presented to Address inputs is stored in the Write address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Page 5 of 26 ADVANCE INFORMATION When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1398V25. A write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1398V25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. DDR Operation The CY7C1398V25 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. At slower frequencies, the CY7C1398V25 requires a single No Operation (NOP) cycle when transitioning from a Read to a Write cycle. At higher frequencies, a second NOP cycle may be required to prevent bus contention. Document #: 38-05176 Rev. ** CY7C1398V25 CY7C1323V25 If a Read occurs after a Write cycle, address and data for the Write are stored in registers. The write information must be stored because the SRAM can not perform the last word Write to the array without conflicting with the Read. The data stays in this register until the next Write cycle occurs. On the first Write cycle after the Read(s), the stored data from the earlier Write will be written into the SRAM array. This is called a Posted Write. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±10% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR-I to simplify data capture on high speed systems. Two echo clocks are generated by the DDR-I. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-I. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Page 6 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Application Example[1] SRAM #1 DQ 18 DQ LD Add. RW C/C K/K RW Add. LD C/C K/K RW Add. LD DQ Memory Controller VTERM = VDDQ/2 SRAM #4 18 R = 50Ω 72 20 20 2 CLK/CLK (input) 2 CLK/CLK (output) R = 50Ω VT = VDDQ/2 Truth Table[2, 3, 4, 5, 6, 7] Operation K LD R/W Write Cycle: Load address; input write data on 2 consecutive K and K rising edges. L-H L L D(A1)at K(t + 1) ↑ D(A2) at K(t + 1) ↑ D(A3) at K(t + 2) ↑ D(A4) at K(t + 2) ↑ Read Cycle: Load address; wait one cycle; read data on 2 consecutive C and C rising edges. L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 1) ↑ Q(A3) at C(t + 2)↑ Q(A4) at C(t + 2) ↑ NOP: No Operation L-H H X High-Z High-Z High-Z) High-Z Stopped X X Previous State Previous State Previous State Previous State Standby: Clock Stopped DQ DQ DQ DQ Note: 1. The above application shows 4 of CY7C1398V25 being used. This holds true for CY7C1323V25 as well. 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW ↑represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3, and A4 represents the addresses sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document #: 38-05176 Rev. ** Page 7 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Linear Burst Address Table First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X..X00 X..X01 X..X10 X..X11 X..X01 X..X10 X..X11 X..X00 X..X10 X..X11 X..X00 X..X01 X..X11 X..X00 X..X01 X..X10 Write Cycle Descriptions[2, 8](CY7C1398V25) BWS0 BWS1 K K L L L-H - During the Data portion of a Write sequence : CY7C1398V25 − both bytes (D[17:0]) are written into the device. L L - L-H During the Data portion of a Write sequence : CY7C1398V25 − both bytes (D[17:0]) are written into the device. L H L-H - During the Data portion of a Write sequence : CY7C1398V25 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L H - L-H During the Data portion of a Write sequence : CY7C1398V25 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. H L L-H - During the Data portion of a Write sequence : CY7C1398V25 − only the upper byte (D17:9]) is written into the device. D[8:0] will remain unaltered. H L - L-H During the Data portion of a Write sequence : CY7C1398V25 − only the upper byte (D17:9]) is written into the device. D[8:0] will remain unaltered. H H L-H - No data is written into the devices during this portion of a write operation. H H - L-H No data is written into the devices during this portion of a write operation. Comments Note: 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1398V25 and also BWS2, BWS3 in the case of CY7C1323V25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05176 Rev. ** Page 8 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Write Cycle Descriptions[2, 8](CY7C1323V25) BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L-H - During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L L L L - L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. H L H H L-H - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H L H H - L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H H L H L-H - During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H L H - L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H H L L-H H H H L - L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. H H H H L-H - No data is written into the device during this portion of a write operation. H H H H - L-H No data is written into the device during this portion of a write operation. Document #: 38-05176 Rev. ** During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. Page 9 of 26 ADVANCE INFORMATION IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1398V25 incorporates a serial boundary scan test access port (TAP) in the FBGA package. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAP Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state that will not interfere with the operation of the device. Test Access Port (TAP) - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on Document #: 38-05176 Rev. ** CY7C1398V25 CY7C1323V25 the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; Page 10 of 26 ADVANCE INFORMATION rather it performs a capture of the Input and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction that is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Document #: 38-05176 Rev. ** CY7C1398V25 CY7C1323V25 The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). The SRAM clock inputs might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the K, K, C and C captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 11 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05176 Rev. ** Page 12 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register x . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[9, 10, 11] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.7 V VOH2 Output HIGH Voltage IOH = −100 µA 2.1 V VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage 1.7 VDD + 0.3 V VIL Input LOW Voltage –0.3 0.7 V IX Input and OutputLoad Current −5 5 µA GND ≤ VI ≤ VDDQ Notes: 9. All Voltage referenced to Ground. 10. Overshoot: VIH(AC) < VDD+1.5V for t < tTCYC/2, Undershoot VIL(AC) < 0.5V for t < tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. 11. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. Document #: 38-05176 Rev. ** Page 13 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION TAP AC Switching Characteristics Over the Operating Range[12, 13] Parameter Description Min. Max. 100 Unit tTCYC TCK Clock Cycle Time ns tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns 10 MHz Set-up Times tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns Notes: 12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05176 Rev. ** Page 14 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION TAP Timing and Test Conditions[13] 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z0 = 50Ω 1.25V CL = 20 pF 0V GND (a) tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX Document #: 38-05176 Rev. ** tTDOV Page 15 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Identification Register Definitions (To be Updated) Value Instruction Field CY7CxxxxV25 Revision Number (31:29) 000 Cypress Device ID (28:12) 01011010011010110 Cypress JEDEC ID (11:1) 00000110100 ID Register Presence (0) 1 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Scan Register Sizes (To be Updated) Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan x Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. This instruction is not 1149.1 compliant. The EXTEST command implemented by these devices will NOT place the output buffers into a high-Z condition. If the output buffers need to be in high-Z condition, this can be accomplished by deselecting the Read port. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. The SAMPLE Z command implemented by these devices will place the output buffers into a high-Z condition. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement the 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05176 Rev. ** Page 16 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Boundary Scan Order (To be Updated) Bit # Signal Name Boundary Scan Order (To be Updated) Bump ID Bit # Signal Name Bump ID 1 C 6R 37 K 6B 2 C 6P 38 K 6A 3 A 6N 39 BWS1 5A 4 A 7P 40 WPS 4A 5 A 7N 41 A 5C 6 A 7R 42 A 4B 7 A 8R 43 NC/36M(1) 3A 8 A 8P 44 GND/144M 2A 9 A 9R 45 Reserved 1A (Don’t Care) 10 D0 10P 46 D9 3B 11 Q0 11P 47 Q9 2B 12 D1 11N 48 D10 3C 13 Q1 10M 49 Q10 3D 14 D2 11M 50 D11 2D 15 Q2 11L 51 Q11 3E 16 D3 10K 52 D12 3F 17 Q3 11K 53 Q12 2F 18 D4 11J 54 D13 2G 19 ZQ 11H 55 Q13 3G 20 Q4 10J 56 D14 3J 21 D5 11G 57 Q14 3K 22 Q5 11F 58 D15 3L 23 D6 10E 59 Q15 2L 24 Q6 11E 60 D16 3M 25 D7 11D 61 Q16 3N 26 Q7 10C 62 D17 2N 27 D8 11C 63 Q17 3P 28 Q8 11B 64 A 3R 29 Reserved 12A (Don’t Care) 65 A 4R 30 GND/72M 10A 66 A 4P 31 NC/18M(1) 9A 67 A 5P 32 A 8B 68 A 5N 33 A 7C 69 A 5R 34 NC (0) 6C 35 RPS 8A 36 BWS0 7B Document #: 38-05176 Rev. ** Page 17 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Supply Voltage on VDD Relative to GND ....... –0.5V to +3.6V Range DC Voltage Applied to Outputs in High Z State[14] ............................... –0.5V to VDDQ + 0.5V Com’l Ambient Temperature[15] VDD VDDQ 0°C to +70°C 1.8 ± 100 mV 1.4V to VDD DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 1.7 1.9 V VDDQ I/O Supply Voltage 1.4 VDD V VOH Output HIGH Voltage IOH = −2.0 mA, Nominal Impedance VDDQ – 0.2 VDDQ V VOL Output LOW Voltage IOL = 2.0 mA, Nominal Impedance VSS 0.2 V VIH Input HIGH Voltage VREF + 0.1 VDDQ + 0.3 V –0.3 VREF – 0.1 V [14] VIL Input LOW Voltage IX Input Load Current GND ≤ VI ≤ VDDQ −5 5 µA IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −5 5 µA VREF Input Reference Voltage[16] Typical Value = 0.75V 0.68 0.95 V IDD VDD Operating Supply x8, x18 VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz TBD mA TBD mA 250 MHz TBD mA 300 MHz TBD mA VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz TBD mA TBD mA 250 MHz TBD mA 300 MHz TBD mA Max. VDD, Both Ports De- 167 MHz selected, VIN ≥ VIH or VIN 200 MHz ≤ VIL f = fMAX = 1/tCYC, Inputs Static 250 MHz TBD mA TBD mA TBD mA 300 MHz TBD mA Max. VDD, Both Ports De- 167 MHz selected, VIN ≥ VIH or VIN 200 MHz ≤ VIL f = fMAX = 1/tCYC, Inputs Static 250 MHz TBD mA TBD mA TBD mA 300 MHz TBD mA IDD ISB1 ISB1 VDD Operating Supply x36 Automatic Power-Down Current, x8, x18 Automatic Power-Down Current, x36 Note: 14. Minimum voltage equals –0.9V for pulse duration less than 20 ns. 15. TA is the case temperature. 16. VREF Min. = 0.68V or 0.46VDDQ, whichever is larger, VREF max = 0.95V or 0.54VDDQ, whichever is smaller. Document #: 38-05176 Rev. ** Page 18 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Switching Characteristics Over the Operating Range[18] 300 Parameter Description 250 200 167 Min. Max. Min. Max. Min. Max. Min. Max. Unit tCYC K Clock and C Clock Cycle Time 3.3 4.0 4.0 5.0 5.0 6.0 6.0 7.5 ns tKH Input Clock (K/K and C/C) HIGH 1.3 - 1.6 - 2.0 - 2.4 - ns tKL Input Clock (K/K and C/C) LOW 1.3 - 1.6 - 2.0 - 2.4 - ns tKHKH K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge) 1.55 1.75 1.9 2.1 2.4 2.6 2.8 3.2 ns tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 0.8 0.0 1.0 0.0 1.5 0.0 2.0 ns Set-up Times tSA Address Set-up to K Clock Rise 0.4 - 0.5 - 0.6 - 0.7 - ns tSC Control Set-up to Clock (K, K, C, C) Rise (R/W, LD, BWS0, BWS1, BWS2, BWS3) 0.4 - 0.5 - 0.6 - 0.7 - ns tSD D[17:0] Set-up to Clock (K and K) Rise 0.4 - 0.5 - 0.6 - 0.7 - ns tHA Address Hold after Clock (K and K) Rise 0.4 - 0.5 - 0.6 - 0.7 - ns tHC Control Hold after Clock (K and K) Rise (R/W, LD, BWS0, BWS1, BWS2, BWS3) 0.4 - 0.5 - 0.6 - 0.7 - ns tHD D[17:0] Hold after Clock (K and K) Rise 0.4 - 0.5 - 0.6 - 0.7 - ns Hold Times Output Times tCO C/C Clock Rise (or K/K in single clock mode) to Data Valid[17] - 1.8 - 2.2 - 2.4 - 3.0 ns tDOH Data Output Hold after Output C/C Clock Rise (Active to Active) 0.8 - 0.8 - 0.8 - 0.8 - ns tCCQO C/C Clock Rise to Echo Clock Valid 0.8 2.0 0.8 2.4 0.8 2.6 0.8 3.2 ns tCQD Echo Clock (CQ/CQ) Rise to Data Valid - 0.25 - 0.30 - 0.35 - 0.40 ns tCQOH Echo Clock (CQ/CQ) Rise to Data Hold –0.25 - –0.30 - –0.35 - –0.40 - ns 0.8 - 0.8 - 0.8 - 0.8 0.8 ns C Clock Rise to High-Z (Active to High-Z) - 1.8 - 2.2 - 2.4 - 3.0 ns tKC Clock Phase Jitter - 0.08 - 0.10 - 0.13 0.15 ns tKC lock DLL Lock Time (K, C) 1024 - 1024 - 1024 - - Cls tCLZ tCHZ C Clock Rise to Low-Z [18, 19] [18, 19] DLL Timing 1024 Notes: 17. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads. 18. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 19. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. Document #: 38-05176 Rev. ** Page 19 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Capacitance[20] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance TA = 25°C, f = 1 MHz, VDD = 2.5V VDDQ = 1.5V Max. Unit TBD pF TBD pF TBD pF Note: 20. Tested initially and after any design or process change that may affect these parameters. AC Test Loads and Waveforms VDDQ/2 VREF VDDQ/2 VREF OUTPUT Z0 = 50Ω Device Under Test RL = 50Ω VREF = 0.75V ZQ VDDQ/2 R = 50Ω [17] ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under ZQ Test RQ = 250Ω 5 pF 0.25V RQ = 250Ω (a) INCLUDING JIG AND SCOPE Document #: 38-05176 Rev. ** (b) Page 20 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Switching Waveforms Read/Deselect Sequence Ignored Read Deselect Ignored Read Deselect tCYC tKHKH tKL tKHKH K tKH tKL K tKH LD tSA A(16:0) tHA A B R/W tCLZ DQ Q(A+1) Q(A) Q(A+2) Q(A+3) Q(B) Q(B+1) Q(B+2) tKHCH tCO C Q(B+3) tCHZ tCQOH tDOH tCO tCO C tCCQO tCO CQ tCCQO tCQD CQ Device originally deselected. Activity on the Write Port is unknown. = DON’T CARE Document #: 38-05176 Rev. ** = UNDEFINED Page 21 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Switching Waveforms (continued) Write/Deselect Sequence Ignored Write Write Deselect Deselect tCYC tKL K tKH tKL K tSA tHA A A B tSA tHC LD tSC tHC R/W tHC tSC BWSx Data In D(A) D(A+1) D(A+2) D(A+3) D(B) tSD D(B+1) D(B+2) D(B+3) tHD C and C reference to Data Outputs and do not affect Write operations. Activity on the Read Port is unknown. BWSx LOW=Valid, Byte writes allowed, see Byte write table for details. = DON’T CARE Document #: 38-05176 Rev. ** = UNDEFINED Page 22 of 26 CY7C1398V25 CY7C1323V25 ADVANCE INFORMATION Switching Waveforms (continued) Read/Write/Deselect Sequence Write 1 Ignored 2 Read Ignored 5 4 3 NOP/Deselect Write 6 K K A A B C LD R/W DQ[17:0] D(A) Q(A+1) D(A+1) D(A+2) D(A+3) Q(B) Q(G+1) Q(B+1) Q(B+2) Q(B+3) C C Read Port previously deselected. BWSx assumed active. = DON’T CARE Document #: 38-05176 Rev. ** = UNDEFINED Page 23 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Ordering Information Speed (MHz) Ordering Code 300 CY7C1317V18-300BZC 250 CY7C1317V18-250BZC 200 CY7C1317V18-200BZC 167 CY7C1317V18-167BZC 300 CY7C1319V18-300BZC 250 CY7C1319V18-250BZC 200 CY7C1319V18-200BZC 167 CY7C1319V18-167BZC 300 CY7C1321V18-300BZC 250 CY7C1321V18-250BZC 200 CY7C1321V18-200BZC 167 CY7C1321V18-166BZC Document #: 38-05176 Rev. ** Package Name Package Type Operating Range BB165 13 x 15 mm FBGA Commercial BB165 13 x 15 mm FBGA Commercial BB165 13 x 15 mm FBGA Commercial Page 24 of 26 ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Package Diagram 165-Ball FBGA (13 x 15 x 1.35 mm) BB165 51-85122 Document #: 38-05176 Rev. ** Page 25 of 26 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ADVANCE INFORMATION CY7C1398V25 CY7C1323V25 Revision History Document Title: CY7C1398V25/CY7C1323V25 18-Mb 4-Word Burst SRAM with DDR-I Architecture Document Number: 38-05176 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 110855 11/09/01 SKX Document #: 38-05176 Rev. ** DESCRIPTION OF CHANGE New Data Sheet Page 26 of 26