CY7C1305BV25 CY7C1307BV25 PRELIMINARY 18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and Write data ports • 2.5V core power supply with HSTL Inputs and Outputs The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the device’s Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 18-bit words (CY7C1305BV25) and four 36-bit words (CY7C1307BV25) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. • Variable drive HSTL output buffers All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • Supports concurrent transactions • 167-MHz clock for high bandwidth • 2.5 ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing • SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Expanded HSTL output voltage (1.4V–1.9V) • JTAG interface Configurations • CY7C1305BV25 – 1M x 18 • CY7C1307BV25 – 512K x 36 Cypress Semiconductor Corporation Document #: 38-05630 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 29, 2004 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Logic Block Diagram (CY7C1305BV25) D[17:0] 18 Address Register Read Add. Decode Write Add. Decode 256Kx18 Array CLK Gen. Write Write Reg Reg 256Kx18 Array K K 256Kx18 Array 18 256Kx18 Array Address Register A[17:0] Write Write Reg Reg RPS Control Logic C C Read Data Reg. 72 Vref WPS 36 Reg. Control Logic BWS[0:1] A(17:0) 18 36 Reg. 18 Reg. Q[17:0] 18 Logic Block Diagram (CY7C1307BV25) D[35:0] 36 Address Register Read Add. Decode Write Add. Decode 128K x 36 Array CLK Gen. Write Write Reg Reg 128K x 36 Array K K 128K x 36 Array 17 Write Write Reg Reg 128K x 36 Array A(16:0) Address Register RPS Control Logic C C Read Data Reg. Vref WPS BWS[0:3] 144 72 Reg. Control Logic A(16:0) 17 72 Reg. 36 Reg. 36 Q[35:0] Selection Guide CY7C1305BV25-167 CY7C1307BV25-167 CY7C1305BV25-133 CY7C1307BV25-133 CY7C1305BV25-100 CY7C1307BV25-100 Unit Maximum Operating Frequency 167 133 100 MHz Maximum Operating Current TBD TBD TBD mA Document #: 38-05630 Rev. ** Page 2 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY \ Pin Configuration–CY7C1305BV25 (Top View) 1 2 3 4 5 6 7 8 9 10 11 A NC GND/ 144M NC/ 36M WPS BWS1 K NC RPS A GND/ 72M NC B NC Q9 D9 A NC K BWS0 A NC NC Q8 C NC NC D10 VSS A NC A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI Pin Configuration–CY7C1307BV25 (Top View) 1 2 3 4 5 6 7 8 9 10 11 A NC GND/ 288M NC/ 72M WPS BWS2 K BWS1 RPS NC/ 36M GND/ 144M NC B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C A A A TMS TDI Document #: 38-05630 Rev. ** Page 3 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Pin Definitions Name I/O Description D[x:0] InputSynchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1305BV25 – D[17:0] CY7C1307BV25 – D[35:0] WPS InputSynchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. BWS0, BWS1, BWS2, BWS3 InputSynchronous Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1305BV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1307BV25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputSynchronous Address Inputs. Sampled on the rising edge of the K clock during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25. Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for CY7C1307BV25. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputsSynchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. CY7C1305BV25 - Q[17:0] CY7C1307BV25 - Q[35:0] RPS InputSynchronous Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential 18-bit or 36-bit transfers. C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board cack to the controller. See application example for further details. K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to VSS or left unconnected. ZQ TDO Output TDO pin for JTAG TCK Input TCK pin for JTAG TDI Input TDI pin for JTAG TMS Input TMS pin for JTAG Document #: 38-05630 Rev. ** Page 4 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Pin Definitions (continued) Name I/O Description NC/36M N/A Address expansion for 36M. This is not connected to the die. Can be connected to any voltage level on CY7C1305BV25/CY7C1307BV25. GND/72M Input Address expansion for 72M. This should be tied LOW on the CY7C1305BV25. NC/72M N/A Address expansion for 72M. This can be connected to any voltage level on CY7C1307BV25. GND/144M Input Address expansion for 144M. This should be tied LOW on CY7C1305BV25/CY7C1307BV25. GND/288M Input VREF InputReference VDD Power Supply VSS Ground VDDQ NC Power Supply N/A Address expansion for 144M. This should be tied LOW on CY7C1307BV25. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device Ground for the device Power supply inputs for the outputs of the device Not connected to the die. Can be tied to any voltage level. Introduction Functional Overview The CY7C1305BV25/CY7C1307BV25 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the device completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 18-bit data transfers in the case of CY7C1305BV25 and four 36-bit data transfers in the case of CY7C1307BV25, in two clock cycles. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[0:x]) inputs pass through input registers controlled by the rising edge of input clocks (K and K). CY7C1305BV25 is described in the following sections. The same basic descriptions apply to CY7C1307BV25. Read Operations The CY7C1305BV25 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven Document #: 38-05630 Rev. ** onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 167-MHz device). In order to maintain the internal logic, each Read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode). When the read port is deselected, the CY7C1305BV25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the positive clock (K). Doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Page 5 of 21 PRELIMINARY CY7C1305BV25 CY7C1307BV25 When deselected, the write port will ignore all inputs after the pending Write operations have been completed. includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Byte Write Operations Byte Write operations are supported by the CY7C1305BV25. A write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Read and Write accesses must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Single Clock Mode Depth Expansion The CY7C1305BV25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. The CY7C1305BV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Concurrent Transactions An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. The Read and Write ports on the CY7C1305BV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This Programmable Impedance Application Example[1] Note: 1. The above application shows four QDR-I being used. Document #: 38-05630 Rev. ** Page 6 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Truth Table[2, 3, 4, 5, 6, 7, 8, 9] Operation K RPS Write Cycle: Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges. L-H H[8] Read Cycle: Load address on the rising edge of K; wait one cycle; read data on two consecutive C and C rising edges. L-H NOP: No operation Standby: Clock stopped WPS DQ DQ DQ DQ [9] D(A+00)at K(t+1) ↑ D(A+01) at K(t+1) ↑ D(A+10) at K(t+2) ↑ D(A+11) at K(t+2) ↑ L[9] X Q(A+00) at C(t+1) ↑ Q(A+01) at C(t+1) ↑ Q(A+10) at C(t+2) ↑ Q(A+11) at C(t+2) ↑ L-H H H D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z Stopped X X Previous state Previous state Previous state L Previous state Write Cycle Descriptions (CY7C1305BV25)[2, 10] BWS0 BWS1 K K Comments L L L-H – During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L L – L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. L H L-H – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. H L L-H – During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. H L – L-H During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. H H L-H – No data is written into the device during this portion of a Write operation. H H – L-H No data is written into the device during this portion of a Write operation. Notes: 2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request. Document #: 38-05630 Rev. ** Page 7 of 21 PRELIMINARY CY7C1305BV25 CY7C1307BV25 Write Cycle Descriptions (CY7C1307BV25)[2, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L-H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L H H H L-H – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L H H H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. H L H H L-H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H L H H – L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H H L H L-H – During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H L H – L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H H L L-H H H H L – L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. H H H H L-H – No data is written into the device during this portion of a Write operation. H H H H – L-H No data is written into the device during this portion of a write operation. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. Note: 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 in the case of CY7C1305BV25 and BWS2 and BWS3 in the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05630 Rev. ** Page 8 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current ................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V DC Applied to Outputs in High-Z State –0.5V to VDDQ + 0.5V DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V Range Ambient Temperature (TA) VDD[12] VDDQ[12] 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V Com’l Electrical Characteristics Over the Operating Range[13] DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit 2.4 2.5 2.6 V 1.4 1.5 1.9 V VDDQ/2 + 0.12 V VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage Note 14 VDDQ/2 – 0.12 VOL Output LOW Voltage Note 15 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V VOH(LOW) Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V VOL(LOW) Output LOW Voltage IOH = 0.1 mA, Nominal Impedance VIH Input HIGH Voltage[11] Voltage[11, 16] VIL Input LOW IX Input Load Current GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled V V –0.3 VREF – 0.1 V –5 5 µA 5 µA V 167 MHz TBD mA 133 MHz TBD mA 100 MHz TBD mA Max. VDD, Both Ports 167 MHz Deselected, 133 MHz VIN ≤ VIH or VIN < VIL f = fMAX = 1/tCYC, Inputs Static 100 MHz TBD mA TBD mA TBD mA Output Leakage Current Input Reference Voltage[17] Typical value = 0.75V IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Automatic Power-Down Current 0.2 VDDQ + 0.3 0.95 IOZ VREF ISB1 VSS VREF + 0.1 –5 0.68 0.75 AC Input Requirements Over the Operating Range Min. Typ. Max. Unit VIH Parameter Input High (Logic 1) Voltage Description Test Conditions VREF + 0.2 – – V VIL Input Low (Logic 0) Voltage – – VREF – 0.2 V Thermal Resistance[18] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions 165 FBGA Package Unit 16.7 °C/W 2.5 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. Notes: 11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 12. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 13. All Voltage referenced to Ground. 14. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 15. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. 16. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V. 17. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. Document #: 38-05630 Rev. ** Page 9 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Capacitance[18] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VDD = 2.5V. VDDQ = 1.5V Unit 5 pF 6 pF 7 pF AC Test Loads and Waveforms VDDQ/2 VDDQ/2 VREF VREF OUTPUT Z0 = 50Ω Device Under Test RL = 50Ω VREF = 0.75V ZQ VDDQ/2 R = 50Ω ALL INPUT PULSES 1.25V 0.75V OUTPUT Device Under ZQ Test RQ = 250Ω 5 pF [18] 0.25V RQ= 250 Ω (a) INCLUDING JIG AND SCOPE (b) Switching Characteristics Over the Operating Range[19] Cypress Parameter tPower 167 MHz Consortium Parameter [20] Description VCC (typical) to the First Access Read or Write Min. Max. 133 MHz Min. Max. 100 MHz Min. Max. Unit 10 10 10 µs Cycle Time tCYC tKHKH K Clock and C Clock Cycle Time 6.0 7.5 10.0 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 3.2 3.5 ns tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 tKHKH tKHKH K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge) 2.7 3.3 3.4 4.1 4.4 5.4 ns tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0 2.0 0.0 2.5 0.0 3.0 ns 3.2 3.5 ns Set-up Times tSA tSA Address Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) 0.7 0.8 1.0 ns tSD tSD D[x:0] Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns tHA tHA Address Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns tHC tHC Control Signals Hold after Clock (K and K) Rise (RPS, WPS, BWS0, BWS1) 0.7 0.8 1.0 ns tHD tHD D[x:0] Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns Hold Times Output Times tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid[21] 2.5 3.0 3.0 ns Note: 18. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05630 Rev. ** Page 10 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Switching Characteristics Over the Operating Range[19] (continued) Cypress Parameter 167 MHz Consortium Parameter Description tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to Active) tCHZ tCHZ Clock (C and C) rise to High-Z (Active to High-Z)[21, 22] tCLZ tCLZ Clock (C and C) rise to Low-Z[21, 22] Min. Max. 1.2 133 MHz Min. 1.2 2.5 1.2 Max. 100 MHz Min. 1.2 3.0 1.2 Max. ns 3.0 1.2 Unit ns ns Notes: 19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads. 20. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated. 21. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage. 22. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO. Document #: 38-05630 Rev. ** Page 11 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Switching Waveforms[23, 24, 25] NOP 1 READ 2 WRITE 3 READ 4 WRITE 5 NOP 6 7 K t KL tKH t CYC t KHKH K RPS t SC t HC t HC t SC WPS A A1 A0 t SA A2 A3 t HD t HA t HD t SD D t SD D10 Q Qx3 Q00 t KHCH Q01 D11 Q02 D12 Q03 D13 D30 Q20 D31 Q21 Q22 D32 D33 Q23 t CO t DOH t CLZ tCO tCHZ t DOH C tKHCH tCYC tKHKH tKH tKL C DON’T CARE UNDEFINED Notes: 23. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 24. Outputs are disabled (High-Z) one clock cycle after a NOP. 25. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram. Document #: 38-05630 Rev. ** Page 12 of 21 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. CY7C1305BV25 CY7C1307BV25 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Test Access Port—Test Clock Boundary Scan Register The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 38-05630 Rev. ** The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 13 of 21 PRELIMINARY is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. CY7C1305BV25 CY7C1307BV25 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST Output Bus Three-state IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a three-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus three-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05630 Rev. ** Page 14 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY TAP Controller State Diagram[26] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05630 Rev. ** Page 15 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 1 0 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range[11, 13, 27] Parameter Description Test Conditions Min. IOH = −2.0 mA 1.7 Output HIGH Voltage IOH = −100 µA 2.1 Output LOW Voltage IOL = 2.0 mA VOL2 Output LOW Voltage IOL = 100 µA VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and Output Load Current VOH1 Output HIGH Voltage VOH2 VOL1 GND ≤ VI ≤ VDDQ Max. Unit V V 0.7 V 0.2 V 1.7 VDD + 0.3 V –0.3 0.7 V −5 5 µA TAP AC Switching Characteristics Over the Operating Range [28, 29] Parameter Description Min. Max. Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns 100 ns Set-up Times Hold Times Notes: 27. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 28. Parameters tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 29. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05630 Rev. ** Page 16 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range (continued)[28, 29] Parameter Description Min. Max. Unit Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 ns 0 ns TAP Timing and Test Conditions[29] 1.25V 50Ω ALL INPUT PULSES TDO 2.5V Z0 =50Ω (a) 1.25V CL = 20 pF 0V GND tTL tTH Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Identification Register Definitions Value Instruction Field Revision Number (31:29) Cypress Device ID (28:12) CY7C1305BV25 CY7C1307BV25 000 000 01011010011010101 01011010011100101 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 ID Register Presence (0) 1 1 Document #: 38-05630 Rev. ** Description Version number. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Page 17 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order Boundary Scan Order (continued) Bit # Bump ID Bit # Bump ID 0 6R 24 9K 1 6P 25 10J 2 6N 26 11J 3 7P 27 11H 4 7N 28 10G 5 7R 29 9G 6 8R 30 11F 7 8P 31 11G 8 9R 32 9F 9 11P 33 10F 10 10P 34 11E 11 10N 35 10E 12 9P 36 10D 13 10M 37 9E 14 11N 38 10C 15 9M 39 11D 16 9N 40 9C 17 11L 41 9D 18 11M 42 11B 19 9L 43 11C 20 10L 44 9B 21 11K 45 10B 22 10K 46 11A 23 9J 47 Internal Document #: 38-05630 Rev. ** Page 18 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Boundary Scan Order (continued) Boundary Scan Order (continued) Bit # Bump ID Bit # Bump ID 48 9A 92 1L 49 8B 93 3N 50 7C 94 3M 51 6C 95 1N 52 8A 96 2M 53 7A 97 3P 54 7B 98 2N 55 6B 99 2P 56 6A 100 1P 57 5B 101 3R 58 5A 102 4R 59 4A 103 4P 60 5C 104 5P 61 4B 105 5N 62 3A 106 5R 63 1H 64 1A 65 2B 66 3B 67 1C 68 1B 69 3D 70 3C 71 1D 72 2C 73 3E 74 2D 75 2E 76 1E 77 2F 78 3F 79 1G 80 1F 81 3G 82 2G 83 1J 84 2J 85 3K 86 3J 87 2K 88 1K 89 2L 90 3L 91 1M Document #: 38-05630 Rev. ** Page 19 of 21 CY7C1305BV25 CY7C1307BV25 PRELIMINARY Ordering Information Speed (MHz) 167 Ordering Code CY7C1305BV25-167BZC Package Name Operating Range Package Type BB165D 13 x 15 x 1.4 mm FBGA BB165D 13 x 15 x 1.4 mm FBGA BB165D 13 x 15 x 1.4 mm FBGA Commercial CY7C1307BV25-167BZC 133 CY7C1305BV25-133BZC CY7C1307BV25-133BZC 100 CY7C1305BV25-100BZC CY7C1307BV25-100BZC Package Diagram 165 FBGA 13 x 15 x 1.40 mm BB165D 51-85180-** Quad Data Rate™ SRAM and QDR™ SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05630 Rev. ** Page 20 of 21 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1305BV25 CY7C1307BV25 Document History Page Document Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR™ Architecture Document Number: 38-05630 REV. ECN NO. Issue Date Orig. of Change ** 253049 See ECN SYT Document #: 38-05630 Rev. ** Description of Change New Data Sheet Page 21 of 21