For new designs see CY7C374i CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Features • • • • • • Functional Description 128 macrocells in eight logic blocks 64 I/O pins 6 dedicated inputs including 4 clock pins Bus Hold capabilities on all I/Os and dedicated inputs No hidden delays High speed — fMAX = 100 MHz The CY7C374 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of high-density, high-speed CPLDs. Like all members of the FLASH370 family, the CY7C374 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. The 128 macrocells in the CY7C374 are divided between eight logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. — tPD = 12 ns The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. — tS = 6 ns — tCO = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin CLCC, 100-pin TQFP, and 84-pin PGA packages • Pin compatible with the CY7C373 Logic Block Diagram The CY7C374 is a register intensive 128-Macrocell CPLD. Every two macrocells in the device feature an associated I/O pin, resulting in 64 I/O pins on the CY7C374. In addition, there are two dedicated inputs and four input/clock pins. CLOCK INPUTS INPUTS 2 4 INPUT/CLOCK MACROCELLS INPUT MACROCELLS 4 4 8 I/Os LOGIC BLOCK I/O0−I/O7 A 8 I/Os LOGIC BLOCK I/O8−I/O15 B LOGIC BLOCK 8 I/Os I/O16−I/O23 C LOGIC BLOCK 8 I/Os I/O24−I/O31 D 36 LOGIC BLOCK 16 H 36 36 LOGIC BLOCK 16 16 36 36 16 16 36 36 16 16 36 16 PIM 8 I/Os I/O56−I/O63 8 I/Os I/O48−I/O55 G LOGIC BLOCK 8 I/Os I/O40−I/O47 F LOGIC BLOCK 8 I/Os I/O32−I/O39 E 7C374–1 32 32 Selection Guide 7C374-100 7C374-83 7C374-66 7C374L-66 Maximum Propagation Delay tPD (ns) 12 15 20 20 Minimum Set-Up, tS (ns) 6 8 10 10 Maximum Clock to Output, tCO (ncs) Maximum Supply Current, ICC (mA) Cypress Semiconductor Corporation Document #: 38-03021 Rev. ** Commercial 7 8 10 10 300 300 300 150 370 370 Military/Industrial • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 1998 CY7C374 Pin Configurations PGA Bottom View I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 I/O63 I5 GND VCC I/O2 I/O1 I/O0 VCC GND I/O7 I/O6 I/O5 I/O4 I/O3 PLCC/CLCC Top View L I/O23 I/O25 I/O26 I/O28 I/O31 I/O33 VCC I/O34 I/O36 I/O37 I/O39 K I/O21 GND I/O24 I/O27 I/O30 I2 I/O32 I/O35 I/O38 GND I/O41 J I/O20 I/O22 I/O29 VCC GND I/O40 I/O42 H I/O18 I/O19 I/O43 I/O44 G CLK1 / I1 I/O16 GND CLK2 /I3 I/O46 I/O47 F I/O17 CLK0 /I0 VCC VCC I/O45 GND E I/O15 I/O14 I/O13 I/O49 I/O48 CLK3 /I4 D I/O12 I/O11 I/O51 I/O50 C I/O10 I/O8 I/O54 I/O52 B I/O9 GND I/O6 A I/O7 I/O5 1 2 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCC CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCC GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND 7C374–2 I/O1 VCC I5 I/O3 I/O0 I/O61 I/O62 I/O59 I/O56 GND I/O53 I/O4 I/O2 VCC GND I/O63 I/O60 I/O58 I/O57 I/O55 3 4 5 6 8 9 10 7 11 7C374–3 GND NC VCC GND NC VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 NC VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-03021 Rev. ** NC VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND NC VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND NC 7C374–4 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC NC GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC N/C GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC NC Page 2 of 16 CY7C374 Functional Description (continued) Finally, the CY7C374 features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C374 remain the same. Logic Block The number and configuration of logic blocks distinguishes the members of the FLASH370 family. The CY7C374 includes eight logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is to be used as an input. Buried Macrocell The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for this register has the same options as described for the I/O macrocell. One difference on the buried macrocell is the addition of input register capability. The user can program the buried macrocell to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. The product term array in the FLASH370 logic block receives 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows very complex functions to be implemented in a single pass through the device. Programmable Interconnect Matrix Product Term Allocator A feature called bus-hold has been added to all FLASH370 I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370 CPLDs. Note that product term allocation is handled by software and is invisible to the user. I/O Macrocell Half of the macrocells on the CY7C374 have I/O pins associated with them. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The I/O macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two Document #: 38-03021 Rev. ** The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374 to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Bus Hold Capabilities on all I/Os and Dedicated Inputs Development Tools Development software for the CY7C374 is available from Cypress’s Warp™ software packages. Both of these products are based on IEEE standard 1076/1164 VHDL. Cypress CPLDs are also supports by a number of third-party vendors such as ABEL™ CUPL™, and LOG/iC™. Please refer to third-party tool support data sheets for further information. Page 3 of 16 CY7C374 Maximum Ratings Output Current into Outputs ........................................ 16 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage to Ground Potential .................−0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Commercial DC Input Voltage .................................................−0.5V to +7.0V Industrial DC Program Voltage .....................................................12.5V [1] Military Ambient Temperature VCC 0°C to +70°C 5V ± 5% −40°C to +85°C 5V ± 5% −55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter VOH Description Test Conditions Output HIGH Voltage Min. IOH = −3.2 mA (Com’l/Ind) VCC = Min. Max. Unit 2.4 V IOH = −2.0 mA (Mil) VOL Output LOW Voltage VCC = Min. V IOL = 16 mA (Com’l/Ind) 0.5 V IOL = 12 mA (Mil) V [3] VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for all inputs 2.0 7.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW voltage for all inputs[3] −0.5 0.8 V IIX Input Load Current VI = Internal GND, VI = VCC −10 +10 µA IOZ Output Leakage Current Vo = Internal GND, Vo = VCC −50 +50 µA IOS Output Short Circuit Current[4, 5] VCC = Max., VOUT = 0.5V −30 −160 mA ICC Power Supply Current[6] VCC = Max., IOUT = 0 mA f = 1 MHz, VIN = GND, VCC Com’l 300 mA Com’l “L” −66 150 mA Mil./Ind. 370 mA Shaded area contains preliminary information. Capacitance[5] Parameter CI/O [7, 8] Description Input Capacitance Test Conditions VIN = 5.0V at f=1 MHz Max. Unit 10 pF Endurance Characteristics[5] Parameter N Description Minimum Reprogramming Cycles Test Conditions Min. Normal Programming Conditions 100 Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. Document #: 38-03021 Rev. ** 5. 6. 7. 8. Max. Unit Cycles Tested initially and after any design or process changes that may affect these parameters. Measured with 16-bit counter programmed into each logic block. CI/O for the CLCC and CPGA packages is 15 pF max. CI/O for I5 is 15 pF max Page 4 of 16 CY7C374 AC Test Loads and Waveforms 238Ω (COM'L) 319Ω (MIL) 238Ω (COM’L) 319Ω (MIL) 5V 5V OUTPUT 170Ω (COM’L) 236Ω (MIL) 35 pF INCLUDING JIG AND SCOPE OUTPUT INCLUDING JIG AND SCOPE Equivalent to: OUTPUT 90% 90% 170Ω (COM'L) 10% GND 236Ω (MIL) ≤2 ns 5 pF (a) ALL INPUT PULSES 3.0V (b) 7C374–5 10% ≤ 2n 7C374–6 TH ÉVENIN EQUIVALENT 99Ω (COM’L) 136Ω (MIL) 2.08V (COM'L) 2.13V (MIL) Parameter[9] VX tER(−) 1.5V Output Waveform Measurement Level VOH −0.5V tER(+) VX 2.6V −0.5V VX VOH tEA(+) 1.5V −0.5V VOH VX tEA(−) Vthc VX −0.5V VOH Note: 9. tER is measured with 5-pF AC Test Load and tEA is measured with 35-pF AC Test Load. Document #: 38-03021 Rev. ** Page 5 of 16 CY7C374 Switching Characteristics Over the Operating Range[10] 7C374-100 Parameter Description 7C374-83 7C374-66 7C374L-66 Min. Max. Min. Max. Min. Max. Unit Combinatorial Mode Parameters tPD Input to Combinatorial Output 12 15 20 ns tPDL Input to Output Through Transparent Input or Output Latch 15 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches 16 19 24 ns tEA Input to Output Enable 16 19 24 ns tER Input to Output Disable 16 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time[5] 3 4 5 ns tWH Clock or Latch Enable Input HIGH Time[5] 3 4 5 ns tIS Input Register or Latch Set-Up Time 2 3 4 ns tIH Input Register or Latch Hold Time 2 tICO Input Register Clock or Latch Enable to Combinatorial Output 16 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch 18 21 26 ns 7 8 10 ns 3 4 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output tS Set-Up Time from Input to Clock or Latch Enable 6 tH Register or Latch Data Hold Time 0 tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array) tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) 10 12 15 ns tSL Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 12 15 20 ns tHL Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 0 0 0 ns fMAX1 Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] 100 83 66 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 143 125 100 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) 76.9 67.5 50 MHz tOH-tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[5, 11] 0 0 0 ns 8 10 0 16 ns 0 19 ns 24 ns Pipelined Mode Parameters tICS Input Register Clock to Output Register Clock 10 12 15 ns fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 100 83.3 66.6 MHz Document #: 38-03021 Rev. ** Page 6 of 16 CY7C374 Switching Characteristics Over the Operating Range[10] (continued) 7C374-100 Parameter Description 7C374-83 7C374-66 7C374L-66 Min. Max. Min. Max. Min. Max. Unit Reset/Preset Parameters tRW Asynchronous Reset Width[5] tRR Asynchronous Reset Recovery Time tRO Asynchronous Reset to Output tPW Asynchronous Preset Width 12 [5] 15 14 17 18 [5] 12 [5] tPR Asynchronous Preset Recovery Time tPO Asynchronous Preset to Output 20 22 21 15 14 ns 26 20 17 18 ns ns 22 21 ns ns 26 ns Notes: 10. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 11. This specification is intended to guarantee interface compatibility of the other members of the CY7C370 family with the CY7C374. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. Document #: 38-03021 Rev. ** Page 7 of 16 CY7C374 Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 7C374–7 Registered Input REGISTERED INPUT tIS tIH INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWL tWH CLOCK 7C374–8 Registered Output INPUT tS tH CLOCK tCO REGISTERED OUTPUT tWH tWL CLOCK 7C374–9 Document #: 38-03021 Rev. ** Page 8 of 16 CY7C374 Switching Waveforms (continued) Latched Output INPUT tS tH LATCH ENABLE tCO tPDL LATCHED OUTPUT 7C374–10 Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK tICS tSCS UTPUT REGISTER CLOCK 7C374–12 Document #: 38-03021 Rev. ** Page 9 of 16 CY7C374 Switching Waveforms (continued) Latched Input LATCHED INPUT tIS tIH LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWH tWL LATCH ENABLE 7C374–13 Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 7C374–14 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 7C374–15 Document #: 38-03021 Rev. ** Page 10 of 16 CY7C374 Switching Waveforms (continued) Output Enable/Disable INPUT tER tEA OUTPUTS 7C374–17 Ordering Information Speed (MHz) 100 83 66 Ordering Code Package Name Package Type CY7C374-100AC A100 100-Pin Thin Quad Flat Pack CY7C374-100GC G84 84-Pin Grid Array (Cavity Up) CY7C374-100JC J83 84-Lead Plastic Leaded Chip Carrier CY7C374-83AC A100 100-Pin Thin Quad Flat Pack CY7C374-83GC G84 84-Pin Grid Array (Cavity Up) CY7C374-83JC J83 84-Lead Plastic Leaded Chip Carrier CY7C374-83AI A100 CY7C374-83JI J83 84-Lead Plastic Leaded Chip Carrier CY7C374-83GMB G84 84-Pin Grid Array (Cavity Up) CY7C374-83YMB Y84 84-Pin Ceramic Leaded Chip Carrier CY7C374-66AC A100 100-Pin Thin Quad Flat Pack CY7C374-66GC G84 84-Pin Grid Array (Cavity Up) CY7C374-66JC J83 84-Lead Plastic Leaded Chip Carrier CY7C374-66AI A100 CY7C374-66JI J83 84-Lead Plastic Leaded Chip Carrier CY7C374-66GMB G84 84-Pin Grid Array (Cavity Up) CY7C374-66YMB Y84 84-Pin Ceramic Leaded Chip Carrier CY7C374L-66AC A100 100-Pin Thin Quad Flat Pack CY7C374L-66JC J83 Document #: 38-03021 Rev. ** 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Industrial Military Commercial Industrial Military Commercial 84-Lead Plastic Leaded Chip Carrier Page 11 of 16 CY7C374 MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics DC Characteristics tPD 9, 10, 11 tPDL 9, 10, 11 Parameter Subgroups Parameter Subgroups VOH 1, 2, 3 tPDLL 9, 10, 11 VOL 1, 2, 3 tCO 9, 10, 11 VIH 1, 2, 3 tICO 9, 10, 11 VIL 1, 2, 3 tICOL 9, 10, 11 IIX 1, 2, 3 tS 9, 10, 11 IOZ 1, 2, 3 tSL 9, 10, 11 ICC1 1, 2, 3 tH 9, 10, 11 tHL 9, 10, 11 tIS 9, 10, 11 tIH 9, 10, 11 tICS 9, 10, 11 tEA 9, 10, 11 tER 9, 10, 11 UltraLogic and FLASH370 are trademarks of Cypress Semiconductor Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation. ABEL is a trademark of Data I/O Corporation. CUPL is a trademark of Logical Devices Incorporated. LOG/iC is a trademark of Isdata Corporation. Document #: 38-03021 Rev. ** Page 12 of 16 CY7C374 Package Diagrams 100-Pin Thin Quad Flat Pack A100 Document #: 38-03021 Rev. ** Page 13 of 16 CY7C374 Package Diagrams (continued) 84-Pin Grid Array (Cavity Up) G84 51-80015-A 84-Lead Plastic Leaded Chip Carrier J83 Document #: 38-03021 Rev. ** Page 14 of 16 CY7C374 Package Diagrams (continued) 84-pin Ceramic Leaded Chip Carrier Y84 Document #: 38-03021 Rev. ** Page 15 of 16 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C374 Document Title: CY7C374 UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03021 REV. ECN NO. Issue Date Orig. of Change ** 106324 05/08/01 SZV Document #: 38-03021 Rev. ** Description of Change Transferred from Spec number: 38-00214 to 38-03021. Page 16 of 16