CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins 5 dedicated inputs including 2 clock pins In-System Reprogrammable (ISR™) Flash technology — JTAG interface • Bus Hold capabilities on all I/Os and dedicated inputs • No hidden delays • High speed — fMAX = 143 MHz Like all of the UltraLogic™ FLASH370i devices, the CY7C371i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. — tPD= 8.5 ns The 32 macrocells in the CY7C371i are divided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. — tS = 5 ns • • • • — tCO = 6 ns Fully PCI compliant 3.3V or 5.0V I/O operation Available in 44-pin PLCC, and TQFP packages Pin compatible with the CY7C372i The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Functional Description Like all members of the FLASH370i family, the CY7C371i is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371i. In addition, there are three dedicated inputs and two input/clock pins. The CY7C371i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C371i is de- Logic Block Diagram CLOCK INPUTS INPUTS 3 2 INPUT MACROCELLS INPUT/CLOCK MACROCELLS 2 16 I/Os 2 LOGIC BLOCK A I/O0–I/O15 36 PIM 16 I/Os LOGIC BLOCK B 36 I/O16–I/O31 16 16 7c371i–1 16 16 Selection Guide 7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66 8.5 10 12 12 15 15  Maximum Propagation Delay , tPD (ns) Minimum Set-Up, tS (ns) 5 6 8 8 10 10 Maximum Clock to Output, tCO (ns) 6 6.5 8 8 10 10 Typical Supply Current, ICC (mA) 75 75 75 45 75 45 Comm./Ind. Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 10, 2000 CY7C371i Pin Configurations I/O5 /SCLK I/O6 I/O7 I0 ISREN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O5 /SCLK I/O6 I/O7 I0 ISREN I/O27 /SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 I/O21 GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11 I/O28 I/O29 I/O31 I/O30 I/O2 I/O4 I/O3 I/O28 I/O29 I/O31 I/O30 I/O 1 I/O 0 GND VCCIO I/O 2 I/O 4 I/O 3 6 5 4 3 2 1 44 43 42 41 40 I/O1 I/O0 GND VCCIO TQFP Top View PLCC Top View 44 43 42 41 40 39 38 37 36 35 34 33 32 2 3 31 4 30 5 29 6 28 27 7 1 26 8 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 I/O21 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 I/O19 /SDO I/O20 7c371i–3 I/O19 /SDO I/O20 I/O12 I/O13 /SMODE I/O14 I/O15 V CCINT GND I/O16 I/O17 I/O18 7c371i–2 I/O27 /SDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 I2 I/O23 I/O22 Functional Description (continued) I/O Macrocell Finally, the CY7C371i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C371i remain the same. Each of the macrocells on the CY7C371i has a separate associated I/O pin. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed. It also has polarity control, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Logic Block Programmable Interconnect Matrix The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C371i includes two logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. The Programmable Interconnect Matrix (PIM) connects the two logic blocks on the CY7C371i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in a single pass through the device. For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, “An Introduction to In System Reprogramming with FLASH370i.” Product Term Allocator PCI Compliance The product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i CPLDs. Note that product term allocation is handled by software and is invisible to the user. The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. Programming 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of V CC pins: one 2 CY7C371i Design Tools set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When V CCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Development software for the CY7C371i is available from Cypress’s Warp™, Warp Professional™, and Warp Enterprise™ software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools. Please refer to third-party tool support for further information. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Bus Hold Capabilities on all I/Os and Dedicated Inputs Ambient Temperature with Power Applied.................................................. −55°C to +125°C In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Supply Voltage to Ground Potential ................. −0.5V to +7.0V DC Voltage Applied to Outputs in High Z State..................................................... −0.5V to +7.0V DC Input Voltage ................................................. −0.5V to +7.0V DC Program Voltage..................................................... 12.5V Output Current into Outputs (LOW)............................. 16 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Ambient Temperature VCC VCCINT Commercial 0°C to +70°C 5V ± 0.25V 5V ± 0.25V OR 3.3V ± 0.3V −40°C to +85°C 5V ± 0.5V 5V ± 0.5V OR 3.3V ± 0.3V Industrial VCCIO 3 CY7C371i Electrical Characteristics Over the Operating Range[2,3] Param. Description Test Conditions Min. Typ. Max. Unit VOH Output HIGH Voltage with Output Enabled VCC = Min. IOH = −3.2 mA (Com’l/Ind) VOHZ Output HIGH Voltage with Output Disabled VCC = Max. IOH = 0 µA (Com’l/Ind)[4,5] 4.0 V IOH = −50 µA (Com’l/Ind) 3.6 V Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind) 0.5 V 2.0 7.0 V −0.5 0.8 V VOL VIH Input HIGH Voltage  2.4 V [4,5] Guaranteed Input Logical HIGH Voltage for all inputs   VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all inputs IIX Input Load Current VI = Internal GND, VI = VCC −10 +10 µA IOZ Output Leakage Current VCC = Max., VO = GND or VO =VCC, Output Disabled VCC = Max., VO = 3.3V, Output Disabled  −50 +50 µA –125 µA −30 −160 mA IOS Output Short Circuit Current[7,8] VCC = Max., VOUT = 0.5V ICC Power Supply Current VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, V CC 0 –70 Com’l/Ind. 75 125 mA Com’l “L” −66, −83 45 75 mA IBHL Input Bus Hold LOW Sustaining Current VCC = Min., VIL = 0.8V +75 µA IBHH Input Bus Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V −75 µA IBHLO Input Bus Hold LOW Overdrive Current VCC = Max. +500 µA IBHHO Input Bus Hold HIGH Overdrive Current VCC = Max. −500 µA Capacitance Parameter Description Test Conditions CI/O Input Capacitance VIN = 5.0V at f=1 MHz CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz Min. Max. Unit 8 pF 5 12 pF Inductance Parameter L Description Maximum Pin Inductance Test Conditions 44-Lead TQFP 44-Lead PLCC Unit 2 5 nH VIN = 5.0V at f= 1 MHz Endurance Characteristics Parameter N Description Maximum Reprogramming Cycles Test Conditions Max. Unit Normal Programming Conditions 100 Cycles Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 4. I OH = −2 mA, IOL = 2 mA for SDO. 5. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional information. 6. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. Tested initially and after any design or process changes that may affect these parameters. 9. Measured with 16-bit counter programmed into each logic block. 4 CY7C371i AC Test Loads and Waveforms 238Ω (COM'L) 319Ω (MIL) 238Ω (COM'L) 319Ω (MIL) 5V 5V OUTPUT OUTPUT 35 pF INCLUDING JIG AND SCOPE 170Ω (COM'L) 236Ω (MIL) 7c371i–4 (a) 5 pF INCLUDING JIG AND SCOPE 170Ω (COM'L) 236Ω (MIL) 7c371i–5 (b) ALL INPUT PULSES 3.0V 90% Equivalent to: THÉVENIN EQUIVALENT 99Ω (COM'L) 136Ω (MIL) 2.08V(COM'L) OUTPUT 2.13V(MIL) GND 90% 10% 10% < 2 ns < 2 ns (c) Parameter Vx tER(–) 1.5V Output Waveform Measurement Level VOH 0.5V tER(+) VX 2.6V VX 0.5V VOL tEA(+) 1.5V VOH 0.5V VX tEA(–) 7c371i–6 Vthe VX 0.5V VOL Notes: 10. CI/O for ISREN is 15 pF Max. 11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. 5 CY7C371i Switching Characteristics Over the Operating Range Parameter Description 7C371i−143 7C371i−110 7C371i−83 7C371iL−83 7C371i−66 7C371iL−66 Min. Min. Min. Min. Max. Max. Max. Max. Unit Combinatorial Mode Parameters tPD Input to Combinatorial Output 8.5 10 12 15 ns tPDL Input to Output Through Transparent Input or Output Latch 11.5 13 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches 13.5 15 20 24 ns tEA Input to Output Enable 13 14 19 24 ns tER Input to Output Disable 13 14 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time 2.5 3 4 5 ns tWH Clock or Latch Enable Input HIGH Time  2.5 3 4 5 ns tIS Input Register or Latch Set-Up Time 2 2 3 4 ns tIH Input Register or Latch Hold Time 2 2 3 4 ns tICO Input Register Clock or Latch Enable to Combinatorial Output 12 14 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch 14 16 21 26 ns 6 6.5 8 10 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output tS Set-Up Time from Input to Clock or Latch Enable 5 6 8 10 ns tH Register or Latch Data Hold Time 0 0 0 0 ns tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array) tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) 7 9 12 15 ns tSL Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 9 10 12 15 ns tHL Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 0 0 0 0 ns fMAX1 Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO) 143 111 83.3 66.6 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) 166.7 153.8 100 83.3 MHz fMAX3 Maximum Frequency with external feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) 91 80 50 41.6 MHz tOH-tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[8,13] 0 0 0 0 ns 12 14 19 24 ns Notes: 12. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C371i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. 6 CY7C371i Switching Characteristics Over the Operating Range (continued) Parameter Description 7C371i−143 7C371i−110 7C371i−83 7C371iL−83 7C371i−66 7C371iL−66 Min. Min. Min. Min. Max. Max. Max. Max. Unit Pipelined Mode Parameters tICS Input Register Clock to Output Register Clock fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) 7 9 12 15 ns 125 111 76.9 62.5 MHz 8 10 15 20 ns 10 12 17 22 ns Reset/Preset Parameters tRW tRR Asynchronous Reset Width Asynchronous Reset Recovery Time  tRO Asynchronous Reset to Output tPW Asynchronous Preset Width tPR tPO  Asynchronous Preset Recovery Time Asynchronous Preset to Output 14  16 21 26 ns 8 10 15 20 ns 10 12 17 22 ns  14 16 21 26 ns Tap Controller Parameters fTAP Tap Controller Frequency 500 500 500 500 kHz 3.3V I/O Mode Parameters t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT 7c371i–7 atched Output INPUT tS tH LATCH ENABLE tPDL tCO LATCHED OUTPUT 7c371i–8 7 CY7C371i Switching Waveforms (continued) Registered Input REGISTERED INPUT tIH tIS INPUT REGISTER CLOCK tICO COMBINATORIAL OUTPUT tWL tWH CLOCK 7c371i–9 Clock to Clock REGISTERED INPUT INPUT REGISTER CLOCK tSCS tICS OUTPUT REGISTER CLOCK 7c371i–10 Latched Input LATCHED INPUT tIH tIS LATCH ENABLE tPDL tICO COMBINATORIAL OUTPUT tWL tWH LATCH ENABLE 7c371i–11 8 CY7C371i Switching Waveforms (continued) Latched Input and Output LATCHED INPUT tPDLL LATCHED OUTPUT tICOL tSL tHL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tWL tWH LATCH ENABLE 7c371i–12 Asynchronous Reset tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK 7c371i–13 Asynchronous Preset tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK 7c371i–14 9 CY7C371i Switching Waveforms (continued) Output Enable/Disable INPUT tEA tER OUTPUTS 7c371i–16 Ordering Information Speed (MHz) 143 110 83 66 Package Name Package Type CY7C371i−143AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−143JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371i−110AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−110JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371i–110AI A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i–110JI J67 44-Lead Plastic Leaded Chip Carrier CY7C371i−83AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−83JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371i−83AI A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−83JI J67 44-Lead Plastic Leaded Chip Carrier CY7C371iL−83AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371iL−83JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371iL−83AI A44 44-Lead Thin Plastic Quad Flat Pack CY7C371iL−83JI J67 44-Lead Plastic Leaded Chip Carrier CY7C371i−66AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−66JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371i−66AI A44 44-Lead Thin Plastic Quad Flat Pack CY7C371i−66JI J67 44-Lead Plastic Leaded Chip Carrier CY7C371iL−66AC A44 44-Lead Thin Plastic Quad Flat Pack CY7C371iL−66JC J67 44-Lead Plastic Leaded Chip Carrier CY7C371iL−66AI A44 44-Lead Thin Plastic Quad Flat Pack CY7C371iL−66JI J67 44-Lead Plastic Leaded Chip Carrier Ordering Code Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38−00497−E FLASH370, F LASH370i, ISR, UltraLogic, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation 10 CY7C371i Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 44-Lead Plastic Leaded Chip Carrier J67 51-85003-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.