HD74SSTV16842
11–bit to 22–bit Buffer with SSTL_2 Inputs and Outputs
ADE-205-602A (Z)
Rev.1
May 2001
Description
The HD74SSTV16842 is a 11–bit to 22–bit buffer designed for 2.3 V to 2.7 V Vcc operation and SSTL_2
data (A) inputs.
Features
• Supports SSTL_2 data inputs
• Flow through architecture optimizes PCB layout
Function Table
Input A
Output Y
L
L
H
H
H:
L:
High level
Low level
HD74SSTV16842
Pin Arrangement
Y11A 1
64 VDDQ
Y10A 2
63 GND
GND 3
62 A11
Y9A 4
61 A10
Y8A 5
60 VCC
VDDQ 6
59 VDDQ
GND 7
58 GND
Y7A 8
57 A9
Y6A 9
56 A8
Y5A 10
55 VDDQ
GND 11
54 GND
Y4A 12
53 A7
Y3A 13
Y2A 14
52 A6
51 VDDQ
GND 15
50 GND
Y1A 16
49 NC
Y11B 17
VDDQ 18
48 NC
Y10B 19
46 VCC
47 VDDQ
Y9B 20
45 VREF
Y8B 21
44 A5
GND 22
43 GND
Y7B 23
42 VDDQ
Y6B 24
41 A4
Y5B 25
40 A3
GND 26
39 GND
VDDQ 27
38 VDDQ
Y4B 28
37 VCC
Y3B 29
36 A2
GND 30
35 A1
Y2B 31
34 GND
Y1B 32
33 VDDQ
(Top view)
Rev.1, May 2001, page 2 of 7
HD74SSTV16842
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC or VDDQ
–0.5 to 3.6
V
VI
–0.5 to VDDQ+0.5
V
VO
–0.5 to VDDQ+0.5
V
Input clamp current
IIK
±50
mA
VI < 0 or VI > VCC
Output clamp current
IOK
±50
mA
VO < 0 or VO > VDDQ
Continuous output current
IO
±50
mA
VO = 0 to VDDQ
VCC, VDDQ or GND current / pin
ICC, IDDQ or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air)
PT
1
W
Storage temperature
Tstg
–65 to +150
°C
Supply voltage
Input voltage
*1
Output voltage
Notes:
*1, 2
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This current will flow only when the output is in the high state and VO > VDDQ.
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Unit Conditions
Supply voltage
VCC
VDDQ
2.5
2.7
V
Output supply voltage
VDDQ
2.3
2.5
2.7
V
Reference voltage
VREF
1.15
1.25
1.35
V
Termination voltage
VTT
VREF–40 mV
VREF
VREF+40 mV
V
Input voltage
VI
0
—
VCC
V
AC high level input voltage
VIH
VREF+310 mV —
—
V
A
AC low level input voltage
VIL
—
VREF–310 mV
V
A
DC high level input voltage
VIH
VREF+150 mV —
—
V
A
DC low level input voltage
VIL
—
—
VREF–150 mV
V
A
High level output current
IOH
—
—
–20
mA
Low level output current
IOL
—
—
20
mA
Input transition rise or fall time
∆t / ∆v
—
—
10
ns/V
Operating temperature
Ta
0
—
70
°C
—
VREF = 0.5 × VDDQ
Rev.1, May 2001, page 3 of 7
HD74SSTV16842
Logic Diagram
VREF
45
A1
35
16
32
Y1A
Y1B
To ten other channels
Electrical Characteristics
Item
Symbol VCC (V)
Min
Typ
Max
Unit Test Conditions
Input diode voltage
VIK
2.3
—
—
–1.2
V
IIN = –18 mA
Output voltage
VOH
2.3 to 2.7 VCC–0.2 —
—
V
IOH = –100 µA
2.3
VOL
Input current
(All inputs)
Quiescent supply current
IIN
ICC
*2
Dynamic operating per each ICCD
data input
Output high
Output low
1.95
VDDQ
IOH = –16 mA
—
0.2
IOL = 100 µA
2.3
0
—
0.35
IOL = 16 mA
2.7
—
—
±5
µA
VIN = 2.7 V or 0
2.7
—
—
45
mA
VIN = VIH(AC) or VIL(AC), IO = 0
2.7
—
—
20
µA/ VI = VIH(AC) or VIL(AC),
data One data input switching at
input 50% duty cycle.
rOH
2.3 to 2.7 7
—
20
Ω
IOH = –20 mA
rOL
2.3 to 2.7 7
—
20
Ω
IOL = 20 mA
rO(∆)
2.5
—
—
4
Ω
IO = 20 mA, Ta = 25°C
Data inputs CIN
2.5
2.5
—
3.5
pF
VI = VREF±310 mV
*3
*3
rOH – rOL each
*3
separate bit
Input
capacitance
*2
—
2.3 to 2.7 —
*1
Notes: 1. All typical values are at VCC = 2.5 V, Ta = 25°C.
2. Total ICC (max) = ICC + {ICCD (Data)×11}
3. This is effective in the case that it did terminate by resistance.
Rev.1, May 2001, page 4 of 7
HD74SSTV16842
Switching Characteristics
Item
Symbol
Propagation delay time
Note:
*1
tPLH
tPHL
VCC = 2.5 ± 0.2 V
Unit
Min
Typ
Max
1.6
—
2.8
ns
FROM
TO
(Input)
(Output)
A
Y
1. This timing relationship is specified into test load (see waveforms – 1) with all of the outputs
switching.
Test Circuit
VTT
*2
50 Ω
Test point
*1
C L = 30 pF
Notes:
1.
2.
3.
CL includes probe and jig capacitance.
VTT = VREF = VDDQ × 0.5
Input waveform : PRR • 10 MHz, Zo = 50 Ω,
Input slew rate = 1 V/ns ±20% (unless otherwise noted.)
Waveforms – 1
VIH
Input
VTT
VTT
tPLH
tPHL
VIL
VOH
Output
VTT
VTT
VOL
Rev.1, May 2001, page 5 of 7
HD74SSTV16842
Package Dimensions
Unit: mm
17.0
17.2 Max
33
6.10
64
1
32
0.50
*0.20 ± 0.05
0.08 M
1.0
8.10 ± 0.20
0.90 Max
*Pd plating
Rev.1, May 2001, page 6 of 7
0.05 ± 0.05
0.08
*0.15 ± 0.05
1.20 Max
0˚ – 8˚
0.5 ± 0.1
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-64D
—
Conforms
0.47 g
HD74SSTV16842
Disclaimer
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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products.
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 4.0
Rev.1, May 2001, page 7 of 7