a iCoupler ® Digital Isolator ADuM1100 FEATURES High Data Rate: DC to 100 Mbps (NRZ) Compatible with 3.3 V and 5.0 V Operation/ Level Translation 125ⴗC Max Operating Temperature Low Power Operation 5 V Operation 1.0 mA Max @ 1 Mbps 4.5 mA Max @ 25 Mbps 16.8 mA Max @ 100 Mbps 3.3 V Operation 0.4 mA Max @ 1 Mbps 3.5 mA Max @ 25 Mbps 7.1 mA Max @ 50 Mbps 8-Lead SOIC Package (lead-free version available) High Common-Mode Transient Immunity: >25 kV/s Safety and Regulatory Information UL Recognized 2500 V rms for 1 Minute per UL 1577 CSA Component Acceptance Notice No. 5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–01 DIN EN 60950 (VDE 0805): 2001–12; EN 60950: 2000 VIORM = 560 VPEAK GENERAL DESCRIPTION The ADuM1100 is a digital isolator based on Analog Devices’ iCoupler technology. Combining high speed CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. Configured as a pin compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with either voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125°C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 µA per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105°C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125°C and supports data rates up to 100 Mbps. APPLICATIONS Digital Fieldbus Isolation Opto-Isolator Replacement Computer-Peripheral Interface Microprocessor System Interface General Instrumentation and Data Acquisition Applications FUNCTIONAL BLOCK DIAGRAM VDD1 VI (DATA IN) VDD2 D E C O D E E N C O D E VO (DATA OUT) VDD1 UPDATE GND1 GND2 WATCHDOG ADuM1100 GND2 FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADuM1100–SPECIFICATIONS (4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25ⴗC, VDD1 = VDD2 = 5 V.) ELECTRICAL SPECIFICATIONS, 5 V OPERATION1 Parameter DC SPECIFICATIONS Input Supply Current Output Supply Current Input Supply Current (25 Mbps) (See TPC 1) Output Supply Current2 (25 Mbps) (See TPC 2) Input Supply Current (100 Mbps) (See TPC 1) Output Supply Current2 (100 Mbps) (See TPC 2) Input Current Logic High Output Voltage Logic Low Output Voltage SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width3 Maximum Data Rate4 For ADuM1100BR/ADuM1100UR Minimum Pulse Width3 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low Output5, 6 (See TPC 3) Propagation Delay Time to Logic High Output5, 6 (See TPC 3) Pulse Width Distortion |tPLH – tPHL|6 Change versus Temperature7 Propagation Delay Skew (Equal Temperature)6, 8 Propagation Delay Skew (Equal Temperature, Supplies)6, 8 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output9 Input Dynamic Power Dissipation Capacitance10 Output Dynamic Power Dissipation Capacitance10 Symbol Typ Max Unit Test Conditions IDD1(Q) IDD2(Q) IDD1(25) 0.3 0.01 2.2 0.8 0.06 3.5 mA mA mA VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz Logic Signal Frequency IDD2(25) 0.5 1.0 mA 12.5 MHz Logic Signal Frequency IDD1(100) 9.0 14 mA IDD2(100) 2.0 2.8 mA +10 µA V V V V V 50 MHz Logic Signal Frequency, ADuM1100BR/ADuM1100UR Only 50 MHz Logic Signal Frequency, ADuM1100BR/ADuM1100UR Only 0 ≤ VIN ≤ VDD1 IO = –20 µA, VI = VIH IO = –4 mA, VI = VIH IO = 20 µA, VI = VIL IO = 400 µA, VI = VIL IO = 4 mA, VI = VIL 40 ns Mbps CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels 6.7 150 10 ns Mbps CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels tPHL 10.5 18 ns CL = 15 pF, CMOS Signal Levels tPLH 10.5 18 ns CL = 15 pF, CMOS Signal Levels PWD 0.5 3 2 CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels II VOH VOL Min –10 +0.01 VDD2 – 0.1 5.0 VDD2 – 0.8 4.6 0.0 0.03 0.3 PW 0.1 0.1 0.8 25 PW 100 tPSK1 8 ns ps/°C ns tPSK2 6 ns CL = 15 pF, CMOS Signal Levels 3 35 ns kV/µs CL = 15 pF, CMOS Signal Levels VI = 0 or VDD1, VCM = 1000 V, Transient Magnitude = 800 V 35 pF 8 pF t R , tF |CML|, |CMH| CPD1 CPD2 25 See Notes on page 5. Specifications subject to change without notice. –2– REV. E ADuM1100 (3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All min/max ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION1 specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25ⴗC, VDD1 = VDD2 = 3.3 V.) Parameter DC SPECIFICATIONS Input Supply Current Output Supply Current Input Supply Current (25 Mbps) (See TPC 1) Output Supply Current2 (25 Mbps) (See TPC 2) Input Supply Current (50 Mbps) (See TPC 1) Output Supply Current2 (50 Mbps) (See TPC 2) Input Current Logic High Output Voltage Logic Low Output Voltage SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width3 Maximum Data Rate4 For ADuM1100BR/ADuM1100UR Minimum Pulse Width3 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low Output5, 6 (See TPC 4) Propagation Delay Time to Logic High Output5, 6 (See TPC 4) Pulse Width Distortion |tPLH – tPHL|6 Change versus Temperature7 Propagation Delay Skew (Equal Temperature)6, 8 Propagation Delay Skew (Equal Temperature, Supplies)6, 8 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output9 Input Dynamic Power Dissipation Capacitance10 Output Dynamic Power Dissipation Capacitance10 Symbol Min Typ Unit Test Conditions IDD1(Q) IDD2(Q) IDD1(25) 0.1 0.3 0.005 0.04 2.0 2.8 mA mA mA VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz Logic Signal Frequency IDD2(25) 0.3 0.7 mA 12.5 MHz Logic Signal Frequency IDD1(50) 4.0 6.0 mA IDD2(50) 1.2 1.6 mA +10 µA V V V V V 25 MHz Logic Signal Frequency, ADuM1100BR/ADuM1100UR Only 25 MHz Logic Signal Frequency, ADuM1100BR/ADuM1100UR Only 0 ≤ VIN ≤ VDD1 IO = –20 µA, VI = VIH IO = –2.5 mA, VI = VIH IO = 20 µA, VI = VIL IO = 400 µA, VI = VIL IO = 2.5 mA, VI = VIL 40 ns Mbps CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels 10 100 20 ns Mbps CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels tPHL 14.5 28 ns CL = 15 pF, CMOS Signal Levels tPLH 15.0 28 ns CL = 15 pF, CMOS Signal Levels PWD 0.5 10 3 CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels II VOH VOL –10 +0.01 VDD2 – 0.1 3.3 VDD2 – 0.5 3.0 0.0 0.04 0.3 PW 0.1 0.1 0.4 25 PW 50 tPSK1 15 ns ps/°C ns tPSK2 12 ns CL = 15 pF, CMOS Signal Levels 3 35 ns kV/µs CL = 15 pF, CMOS Signal Levels VI = 0 or VDD1, VCM = 1000 V, Transient Magnitude = 800 V 47 pF 14 pF t R , tF |CML|, |CMH| CPD1 25 CPD2 See Notes on page 5. Specifications subject to change without notice. REV. E Max –3– ADuM1100 (5 V/3 V operation: 4.5 V ≤ V ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V or 3 V/5 V OPERATION1 ≤ 5.5 V, 3.0 V ≤ V ≤ 3.6 V. DD1 DD2 3 V/5 V operation: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25ⴗC, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V.) Parameter DC SPECIFICATIONS Input Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Output Voltage, 5 V/3 V Operation Logic Low Output Voltage, 5 V/3 V Operation Logic High Output Voltage, 3 V/5 V Operation Logic Low Output Voltage, 3 V/5 V Operation SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width3 Maximum Data Rate4 For ADuM1100BR/ADuM1100UR Minimum Pulse Width3 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low/High Output5, 6 5 V/3 V Operation (See TPC 5) 3 V/5 V Operation (See TPC 6) Pulse Width Distortion, |tPLH – tPHL|6 5 V/3 V Operation 3 V/5 V Operation Change versus Temperature 5 V/3 V Operation 3 V/5 V Operation Propagation Delay Skew (Equal Temperature)6, 8 5 V/3 V Operation 3 V/5 V Operation Symbol Min Typ Max Unit Test Conditions 0.3 0.1 0.8 0.3 mA mA 0.005 0.01 0.04 0.06 mA mA 2.2 2.0 3.5 2.8 mA mA 12.5 MHz Logic Signal Frequency 12.5 MHz Logic Signal Frequency 0.3 0.5 0.7 1.0 mA mA 12.5 MHz Logic Signal Frequency 12.5 MHz Logic Signal Frequency 4.5 4.0 7.0 6.0 mA mA 25 MHz Logic Signal Frequency 25 MHz Logic Signal Frequency 1.2 1.0 +0.01 3.3 3.0 0.0 0.04 0.3 5.0 4.6 0.0 0.03 0.3 1.6 1.5 +10 mA mA µA V V V V V V V V V V 25 MHz Logic Signal Frequency 25 MHz Logic Signal Frequency 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2 IO = –20 µA, VI = VIH IO = –2.5 mA, VI = VIH IO = 20 µA, VI = VIL IO = 400 µA, VI = VIL IO = 2.5 mA, VI = VIL IO = –20 µA, VI = VIH IO = –4 mA, VI = VIH IO = 20 µA, VI = VIL IO = 400 µA, VI = VIL IO = 4 mA, VI = VIL IDDI(Q) IDDO(Q) IDDI(25) IDDO(25) IDDI(50) IDDO(50) IIA VOH –10 VDD2 – 0.1 VDD2 – 0.5 VOL VOH VDD2 – 0.1 VDD2 – 0.8 VOL PW 0.1 0.1 0.4 0.1 0.1 0.8 40 ns CL = 15 pF, CMOS Signal Levels Mbps CL = 15 pF, CMOS Signal Levels 20 ns CL = 15 pF, CMOS Signal Levels Mbps CL = 15 pF, CMOS Signal Levels 13 16 21 26 ns ns CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels 0.5 0.5 2 3 ns ns CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels 25 PW 50 tPHL, tPLH PWD ps/ºC CL = 15 pF, CMOS Signal Levels ps/ºC CL = 15 pF, CMOS Signal Levels 3 10 tPSK1 12 15 –4– ns ns CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels REV. E ADuM1100 Parameter Symbol SWITCHING SPECIFICATIONS (continued) Propagation Delay Skew (Equal Temperature, Supplies)6, 8 5 V/3 V Operation 3 V/5 V Operation Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic Low/High Output8 Input Dynamic Power Dissipation Capacitance10 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Power Dissipation Capacitance10 5 V/3 V Operation 3 V/5 V Operation Min Typ Max Unit Test Conditions 9 12 3 ns ns ns CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels CL = 15 pF, CMOS Signal Levels 35 kV/µs VI = 0 or VDD1, VCM = 1000 V, Transient Magnitude = 800 V 35 47 pF pF 8 14 pF pF tPSK2 t R , tf |CML|, |CMH| CPD1 25 CPD2 NOTES 1 All voltages are relative to their respective ground. 2 Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by IDD2(L) = IDD2 + VDD2 × f × CL, where IDD2 is the unloaded output supply current, f is the input signal frequency, and CL is the output load capacitance. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL is measured from the 50% level of the falling edge of the V I signal to the 50% level of the falling edge of the V O signal. tPLH is measured from the 50% level of the rising edge of the V I signal to the 50% level of the rising edge of the V O signal. 6 Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input rise/fall times on these parameters. 7 Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature. 8 tPSK1 is the magnitude of the worst-case difference in t PHL and/or tPLH that will be measured between units at the same operating temperature and output load within the recommended operating conditions. t PSK2 is the magnitude of the worst-case difference in t PHL and/or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 9 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 10 The dynamic power dissipation capacitance is given by CPDi = (IDDi(100) – IDDi(Q))/(VDDi × f), where i = 1 or 2 and f is the input signal frequency. The supply current consumptions at a given frequency and output load are calculated as IDD1 = CPD1 × VDD1 × f + IDD1(Q); IDD2(L) = (CPD2 + CL) × VDD2 × f + IDD2(Q), where CL is the output load capacitance. Specifications subject to change without notice. PACKAGE CHARACTERISTICS Parameter Symbol 1 Resistance (Input-Output) Capacitance (Input-Output)1 Input Capacitance2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Package Power Dissipation Min Typ Max Unit RI–O CI–O CI θJCI 10 1 4.0 46 Ω pF pF °C/W θJCO 41 °C/W 12 PPD 240 mW NOTES 1 Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 2 Input capacitance is measured at Pin 2 (V I). REV. E –5– Test Conditions f = 1 MHz Thermocouple Located at Center Underside of Package ADuM1100 REGULATORY INFORMATION The ADuM1100 has been approved by the following organizations: UL CSA VDE Recognized under 1577 Approved under CSA Component Component Recognition Program1 Acceptance Notice No. 5A, C22.2 No. 1-98, C22.2 No. 14-95, and C22.2 No. 950-95 File E214100 File 205078 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–12 DIN EN 60950 (VDE 0805): 2001–12; EN60950: 2000 File 2471900-4880-0002 NOTES 1 In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (leakage detection current limit, I I–O ≤ 5 µA). 2 In accordance with DIN EN 60747-5-2, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 1050 VPEAK for 1 second (partial discharge detection limit ≤ 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Parameter Symbol Value Unit Conditions Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group 0.016 min mm >175 V IIIa DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS Description Symbol Characteristic Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification ADuM1100AR and ADuM1100BR ADuM1100UR Pollution Degree (DIN VDE 0110, Table I) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% Production Test, tM = 1 sec, Partial Discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tM = 10 sec, Partial Discharge < 5 pC After Input and/or Output Safety Test Subgroup 2/3 VIORM × 1.2 = VPR, tM = 10 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tINI = 60 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure, See Thermal Derating Curve, Figure 1 Case Temperature Input Current Output Current Insulation Resistance at TS, VIO = 500 V I to IV I to III I to II VIORM 40/105/21 40/125/21 2 560 VPEAK VPR VPR 1050 672 VPEAK VPEAK VPR 896 VPEAK VPR VTR 672 4000 VPEAK VPEAK TS IS, INPUT IS, OUTPUT Rs 150 160 170 >109 °C mA mA Ω This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. The * marking on the package denotes DIN EN 60747-5-2 approval for 560 V PEAK working voltage. –6– REV. E SAFETY-LIMITING CURRENT (mA) ADuM1100 180 ABSOLUTE MAXIMUM RATINGS 1 160 Parameter Symbol Min Max Unit Storage Temperature Ambient Operating Temperature Supply Voltages2 Input Voltage2 Output Voltage2 Average Current, per Pin3 Temperature ≤ 105°C Temperature ≤ 125°C Input Current Output Current Common-Mode Transients4 TST TA –55 –40 °C °C 140 OUTPUT CURRENT 120 100 INPUT CURRENT 80 60 40 20 0 0 50 100 150 CASE TEMPERATURE (ⴗC) 200 Figure 1. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2 +150 +125 VDD1, VDD2 –0.5 +6.5 V VI –0.5 VDD1 + 0.5 V VO –0.5 VDD2 + 0.5 V –25 +25 –7 +7 –20 +20 –100 +100 mA mA mA kV/µs NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Ambient temperature = 25°C, unless otherwise noted. 2 All voltages are relative to their respective ground. 3 See Figure 1 for information on maximum allowable current for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Operating Temperature ADuM1100AR and ADuM1100BR ADuM1100UR Supply Voltages1 Logic High Input Voltage, 5 V Operation1, 2 (See TPCs 7 and 8) Logic Low Input Voltage, 5 V Operation1, 2 (See TPCs 7 and 8) Logic High Input Voltage, 3.3 V Operation1, 2 (See TPCs 7 and 8) Logic Low Input Voltage, 3.3 V Operation1, 2 (See TPCs 7 and 8) Input Signal Rise and Fall Times TA TA VDD1, VDD2 VIH VIL VIH VIL –40 –40 3.0 2.0 0.0 1.5 0.0 +105 +125 5.5 VDD1 0.8 VDD1 0.5 1.0 °C °C V V V V V ms NOTES 1 All voltages are relative to their respective ground. 2 Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section and Figures 8 and 9 for information on immunity to external magnetic fields. REV. E –7– ADuM1100 Table I. Truth Table (Positive Logic) VI Input VDD1 State VDD2 State VO Output H L X X Powered Powered Unpowered Powered Powered Powered Powered Unpowered H L H* X* *VO returns to VI state within 1 µs of power restoration. Note: Package branding is as follows: ADuM1100AR, ADuM1100AR-RL7 8 ADuM1100BR, ADuM1100BR-RL7 8 8 AD1100B R YYWW* XXXXXX AD1100A R YYWW* XXXXXX PIN CONFIGURATION ADuM1100UR, ADuM1100UR-RL7 AD1100U R YYWW* XXXXXX VDD11 1 8 VDD2 VI 2 7 GND22 VDD11 3 GND1 4 1 where: * R YYWW XXXXXX 1 ADuM1100 6 VO TOP VIEW (Not to Scale) 5 GND22 1 NOTES 1PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR VDD1. 2PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2. = DIN EN 60747-5-2 mark = Package Designator (R denotes SOIC) = Date Code = Lot Code ORDERING GUIDE Model ADuM1100AR ADuM1100AR-RL7 ADuM1100ARZ* ADuM1100ARZ-RL7* ADuM1100BR ADuM1100BR-RL7 ADuM1100BRZ* ADuM1100BRZ-RL7* ADuM1100UR ADuM1100UR-RL7 ADuM1100URZ* ADuM1100URZ-RL7* ADuM1100EVAL Temperature Range Max Data Rate (Mbps) Min Pulse Width (ns) –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C 25 25 25 25 100 100 100 100 100 100 100 100 40 40 40 40 10 10 10 10 10 10 10 10 Package Description 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel 8-Lead SOIC 8-Lead SOIC, 1,000 Piece Reel Evaluation Board Package Option R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 *Z = Lead Free CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuM1100 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –8– REV. E Typical Performance Characteristics— ADuM1100 18 20 18 17 PROPAGATION DELAY (ns) 16 CURRENT (mA) 14 12 10 8 5V 6 3.3V 4 16 tPHL 15 tPLH 14 13 2 12 –50 0 0 25 50 75 100 DATA RATE (Mbps) 125 150 5 14 4 13 3 5V 2 3.3V 50 75 100 DATA RATE (Mbps) 75 100 125 tPLH 12 tPHL 11 9 –50 0 25 25 50 TEMPERATURE (ⴗC) 10 1 0 0 TPC 4. Typical Propagation Delays vs. Temperature, 3.3 V Operation PROPAGATION DELAY (ns) CURRENT (mA) TPC 1. Typical Input Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation –25 125 150 TPC 2. Typical Output Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation –25 0 25 50 TEMPERATURE (ⴗC) 75 100 125 TPC 5. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation 13 18 11 tPHL PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 17 12 tPLH 10 16 tPHL 15 tPLH 14 13 9 –50 –25 0 50 25 TEMPERATURE (ⴗC) 75 100 12 –50 125 TPC 3. Typical Propagation Delays vs. Temperature, 5 V Operation REV. E –25 0 25 50 TEMPERATURE (ⴗC) 75 100 125 TPC 6. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation –9– ADuM1100 1.4 1.7 1.3 INPUT THRESHOLD, V ITH (V) 1.6 INPUT THRESHOLD, V ITH (V) –40ⴗC +25ⴗC –40ⴗC 1.5 +25ⴗC 1.4 1.3 +125ⴗC 1.2 1.2 +125ⴗC 1.1 1.0 0.9 1.1 3.0 3.5 4.0 4.5 5.0 INPUT SUPPLY VOLTAGE, V DD1 (V) 0.8 3.0 5.5 TPC 7. Typical Input Voltage Switching Threshold, Low-to-High Transition The ADuM1100 digital isolator requires no external interface circuitry for the logic interfaces. A bypass capacitor is recommended at the input and output supply pins. The input bypass capacitor may most conveniently be connected between Pins 3 and 4 (Figure 2). Alternatively, the bypass capacitor may be located between Pins 1 and 4. The output bypass capacitor may be connected between Pins 7 and 8 or Pins 5 and 8. The capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. VDD1 VDD2 (OPTIONAL) VO (DATA OUT) GND2 GND1 Figure 2. Recommended Printed Circuit Board Layout INPUT (VI) Pulse width distortion is the maximum difference between tPLH and tPHL and provides an indication of how accurately the input signal’s timing is preserved in the component’s output signal. Propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple ADuM1100 components operated at the same operating temperature and having the same output load. Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). This is due to the fact that the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. This propagation delay difference is given by ∆ HL = t ' PHL − tPHL = (t f ) )) I 1 ITH (H −L where: tPLH, tPHL 50% Figure 3. Propagation Delay Parameters Propagation Delay-Related Parameters Propagation delay time describes the length of time it takes for a logic signal to propagate through a component. Propagation delay VI ( / 0.8V )(0.5V − V ∆ LH = t ' PLH − tPLH = (tr / 0.8VI ) 0.5V1 − VITH (L −H ) tPHL OUTPUT (VO) 5.5 time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and the respective output signal transition (Figure 3). 50% tPLH 4.0 4.5 5.0 INPUT SUPPLY VOLTAGE, V DD1 (V) TPC 8. Typical Input Voltage Switching Threshold, High-to-Low Transition APPLICATION INFORMATION PC Board Layout V1 (DATA) 3.5 = propagation delays as measured from the input 50% level. = propagation delays as measured from the t′PLH, t ′PHL input switching thresholds. = input 10% to 90% rise/fall time. tr , tf = amplitude of input signal (0 to VI levels VI assumed). VITH(L–H), VITH(H–L) = input switching thresholds. ⌬LH ⌬HL VITH(L–H) 50% VITH(H–L) tPLH INPUT (VI) tPHL t'PLH t'PHL 50% OUTPUT (VO) Figure 4. Impact of Input Rise/Fall Time on Propagation Delay –10– REV. E ADuM1100 6 PULSEWIDTH DISTORTION ADJUSTMENT, ⌬PWD (ns) PROPAGATION DELAY CHANGE, ⌬LH (ns) 4 3 5V INPUT SIGNAL 2 1 3.3V INPUT SIGNAL 0 2 3 4 5 7 6 8 INPUT RISE TIME (10%–90%, ns) 9 10 Figure 5. Typical Propagation Delay Change due to Input Rise Time Variation (for VDD1 = 3.3 V and 5 V) 5V INPUT SIGNAL 3 3.3V INPUT SIGNAL 2 1 1 2 4 5 7 3 6 8 INPUT RISE/FALL TIME (10%–90%, ns) 9 10 Figure 7. Typical Pulse Width Distortion Adjustment due to Input Rise/Fall Time Variation (at VDD1 = 3.3 V and 5 V) Method of Operation, DC Correctness, and Magnetic Field Immunity 0 PROPAGATION DELAY CHANGE, ⌬HL (ns) 4 0 1 Referring to the functional block diagram, the two coils act as a pulse transformer. Positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than 2 µs, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. If the decoder receives none of these update pulses for more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit. –1 5V INPUT SIGNAL –2 3.3V INPUT SIGNAL –3 –4 1 2 3 6 8 4 5 7 INPUT RISE TIME (10%–90%, ns) 9 10 Figure 6. Typical Propagation Delay Change due to Input Fall Time Variation (for VDD1 = 3.3 V and 5 V) The impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. This impact may either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of tPHL, tPLH, and PWD. The case of interest here is the condition that leads to the largest increase in pulse width distortion. The change in this case is given by ∆PWD = PWD′ – PWD = ∆LH – ∆HL = (t /0.8V1 )(V – VITH(L –H ) – VITH(H –L ) ), ( for t = tr = tf ) where: PWD = tPLH – tPHL PWD′ = t ′PLH – t ′PHL The limitation on the ADuM1100’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The analysis that follows defines the conditions under which this may occur. The ADuM1100’s 3.3 V operating condition is examined because it represents the most susceptible mode of operation. The pulses at the transformer output are greater than 1.0 V in amplitude. The decoder has sensing thresholds at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The induced voltage induced across the receiving coil is given by V = (– dβ / dt ) Σπ rn2 ; n = 1, 2, . . . . , N where: β = magnetic flux density (Gauss). N = number of turns in receiving coil. rn = radius of nth turn in receiving coil (cm). This adjustment in pulse width distortion is plotted as a function of input rise/fall time in Figure 7. REV. E 5 –11– ADuM1100 Given the geometry of the receiving coil in the ADuM1100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 8. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1100 transformers. Figure 9 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a current of 0.5 kA 5 mm away from the ADuM1100 to affect the component’s operation. 10 1000 1 MAXIMUM ALLOWABLE CURRENT (kA) MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (KGauss) 100 0.1 0.01 0.001 1k 100k 10k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 8. Maximum Allowable External Magnetic Field For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 KGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and will not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 9. Maximum Allowable Current for Various Current-to-ADuM1100 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. –12– REV. E ADuM1100 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 6.20 (0.2440) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) ⴛ 45ⴗ 0.25 (0.0099) 8ⴗ 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. E –13– ADuM1100 Revision History Location Page 10/03—Data Sheet changed from REV. D to REV. E. Changes to Product Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6/03—Data Sheet changed from REV. C to REV. D. Changed DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4/03—Data Sheet changed from REV. B to REV. C. Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Patent note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to INSULATION CHARACTERISTICS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to Method of Operation, DC Correctness, and Magnetic Field Immunity section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Replaced Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1/03—Data Sheet changed from REV. A to REV. B. Added ADuM1100UR Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changed ADuM1100AR/ADuM1100BR to ADuM1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V Operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated TPCs 3–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Deleted iCoupler in Field Bus Networks section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Added a new Figure 9 and related text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 11/02—Data Sheet changed from REV. 0 to REV. A. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Added Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 –14– REV. E –15– –16– C02462–0–10/03(E)