HY62LF16806A Series 512Kx16bit full CMOS SRAM Document Title 512K x16 bit 2.5V Super Low Power Full CMOS slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Draft Apr.10.2001 Preliminary 01 Change Logo - Hyundai à Hynix Apr.28.2001 02 Change DC Parameter - Isb1(LL) : 30uA à - Isb1(Typ) : 8uA à - Icc1(1us) : 5mA à Change Data Retention - IccDR(LL) : 25uA à Change AC Parameter - tOE : 40ns à Jan.28.2002 25uA 1uA 4mA 15uA 35ns@70ns This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 /Jan. 2002 Hynix Semiconductor HY62LF16806A Series DESCRIPTION FEATURES The HY62LF16806A is a high speed, super low power and 8Mbit full CMOS SRAM organized as 524,288 words by 16bits. The HY62LF16806A uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly wellsuited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(LL/SL-part) - 1.2V(min) data retention • Standard pin configuration - 48-uBGA Product Voltage Speed No. (V) (ns) HY62LF16806A-C 2.3~2.7 70/85/100 HY62LF16806A- I 2.3~2.7 70/85/100 Note 1. C : Commercial, I : Industrial 2. Current value is max. Operation Current/Icc(mA) 3 3 PIN CONNECTION ( Top View ) H /UB A3 A4 /CS1 IO1 IO10 IO11 A5 A6 IO2 IO3 Vss IO12 A17 A7 IO4 Vcc Vcc IO13 Vss A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 A18 IO16 NC A12 A13 /WE IO8 A18 A9 A10 A11 A8 NC MEMORY ARRAY 512K x 16 I/O1 I/O8 DATA I/O BUFFER G IO9 ROW DECODER WRITE DRIVER F 6 CS2 BLOCK DECODER E 5 A2 PRE DECODER D 4 A1 ADD INPUT BUFFER C 3 A0 BLOCK DIAGRAM COLUMN DECODER B 2 /OE Temperature (°C) 0~70 -45~85 SENSE AMP A 1 /LB Standby Current(uA) LL SL 30 8 30 8 I/O9 I/O16 /CS1 CS2 /OE /LB /UB /WE PIN DESCRIPTION Pin Name /CS1, CS2 /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Lower Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Rev.02/Jan. 2002 Pin Name I/O1~I/O16 A0~A18 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(2.3V~2.7V) Ground No Connection 2 HY62LF16806A Series ORDERING INFORMATION Part No. Speed HY62LF16806A-DMC 70/85/100 HY62LF16806A-SMC 70/85/100 HY62LF16806A-DMI 70/85/100 HY62LF16806A-SMI 70/85/100 Note 1. C : Commercial, I : Industrial Power LL-part SL-part LL-part SL-part Package uBGA uBGA uBGA uBGA Temp. C C I I ABSOLUTE MAXIMUM RATINGS (1) Symbol VIN, VOUT Vcc Parameter Input/Output Voltage Power Supply TA Operating Temperature TSTG PD TSOLDER Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.2 to 3.6 -0.2 to 4.6 0 to 70 -40 to 85 -55 to 150 1.0 260 • 10 Unit V V °C °C °C W °C • sec Remark HY62LF16806A-C HY62LF16806A-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS1 CS2 /WE /OE /LB /UB H X X L L L X L X H H H X X X H H H X X X H H L X X H L X L H L L H L X X H X L H L L H L L L H L X Mode Deselected Output Disabled Read Write I/O Pin I/O1~I/O8 I/O9~I/O16 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z DOUT DOUT DOUT DIN Hi-Z Hi-Z DIN DIN DIN Power Standby Active Active Active Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8. When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16. Rev.02/Jan. 2002 2 HY62LF16806A Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.3 0 2.0 -0.3(1) Typ. 2.5 0 - Max. 2.7 0 Vcc+0.3 0.6 Unit V V V V Note : 1. VIL = -1.5V for pulse width less than 30ns DC ELECTRICAL CHARACTERISTICS Vcc = 2.3V~2.7V, TA = 0°C to 70°C / -40°C to 85°C Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc Vss < VOUT < Vcc, /CS1 = VIH or CS2=VIL or ILO Output Leakage Current /OE = VIH or /WE = VIL or /UB = VIH , /LB = VIH /CS1 = VIL, CS2=VIH, Icc Operating Power Supply Current VIN = VIH or VIL, II/O = 0mA /CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA ICC1 Average Operating Current /CS1 < 0.2V, CS2 > Vcc-0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS1 = VIH or CS2 = VIL or ISB Standby Current (TTL Input) /UB, /LB = VIH VIN = VIH or VIL /CS1 > Vcc - 0.2V or SL CS2 < Vss + 0.2V or ISB1 Standby Current (CMOS Input) /UB, /LB > Vcc - 0.2V LL VIN > Vcc - 0.2V or VIN < Vss + 0.2V VOL Output Low IOL = 0.5mA VOH Output High IOH = -0.5mA Min -1 -1 2.0 Typ1. - Max 1 1 Unit uA uA 3 mA 30 mA 4 mA 0.3 mA - 8 uA 1 25 uA - 0.4 - V V Note : 1. Typical values are at Vcc = 2.5V, TA = 25°C 2. Typical values are not 100% tested CAPACITANCE (Temp = 25°C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE) COUT Output Capacitance (I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF Note : These parameters are sampled and not 100% tested Rev.02/Jan. 2002 3 HY62LF16806A Series AC CHARACTERISTICS Vcc = 2.3V~2.7V, TA= 0°C to 70°C/ -40°C to 85°C, unless otherwise specified -70 -85 # Symbol Parameter Min. Max. Min. Max. READ CYCLE 1 tRC Read Cycle Time 70 85 2 tAA Address Access Time 70 85 3 tACS Chip Select Access Time 70 85 4 tOE Output Enable to Output Valid 35 45 5 tBA /LB, /UB Access Time 70 85 6 tCLZ Chip Select to Output in Low Z 10 10 7 tOLZ Output Enable to Output in Low Z 5 5 8 tBLZ /LB, /UB Enable to Output in Low Z 10 10 9 tCHZ Chip Deselection to Output in High Z 0 30 0 30 10 tOHZ Out Disable to Output in High Z 0 30 0 30 11 tBHZ /LB, /UB Disable to Output in High Z 0 30 0 30 12 tOH Output Hold from Address Change 10 10 WRITE CYCLE 13 tWC Write Cycle Time 70 85 14 tCW Chip Selection to End of Write 60 70 15 tAW Address Valid to End of Write 60 70 16 tBW /LB, /UB Valid to End of Write 60 70 17 tAS Address Set-up Time 0 0 18 tWP Write Pulse Width 50 55 19 tWR Write Recovery Time 0 0 20 tWHZ Write to Output in High Z 0 25 0 30 21 tDW Data to Write Time Overlap 30 35 22 tDH Data Hold from Write Time 0 0 23 tOW Output Active from End of Write 5 5 - Min -10 Max. Unit 100 10 5 10 0 0 0 15 100 100 50 100 30 30 30 - ns ns ns ns ns ns ns ns ns ns ns ns 100 80 80 80 0 75 0 0 45 0 10 35 - ns ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA= 0°C to 70°C(Commercial)/ -40°C to 85°C, unless otherwise specified PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW Output Load Other Value 0.4V to 2.2V 5ns 1.1V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS V TM = 2.3V 3067 Ohm D OUT CL(1) 3345 Ohm Note 1. Including jig and scope capacitance Rev.02/Jan. 2002 4 HY62LF16806A Series TIMING DIAGRAM READ CYCLE 1(Note 1,4) tRC ADDR tAA tOH tACS /CS1 CS2 tCHZ(3) tBA /UB ,/ LB tBHZ(3) tOE /OE Data Out High-Z tCLZ(3) tOLZ(3) tBLZ(3) tOHZ(3) Data Valid READ CYCLE 2(Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,2,4) /CS1 /UB, /LB CS2 tACS tCLZ(3) Data Out tCHZ(3) Data Valid Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active Rev.02/Jan. 2002 5 HY62LF16806A Series WRITE CYCLE 1 (1,4,8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS1 CS2 tAW tBW /UB,/LB tWP /WE tAS Data In tDW High-Z tDH Data Valid tWHZ(3,7) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled) tWC ADDR tAS tCW tWR(2) /CS1 tAW CS2 tBW /UB,/LB tWP /WE tDW Data In Data Out Rev.02/Jan. 2002 High-Z tDH Data Valid High-Z 6 HY62LF16806A Series Notes: 1. A write occurs whenever a low on the /WE while /UB and/or /LB and /CS1 and CS2 are in active state. 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active DATA RETENTION ELECTRIC CHARACTERISTIC TA= 0°C to 70°C(Commercial)/ -40°C to 85°C Symbol Parameter Test Condition /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or VDR Vcc for Data Retention /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, SL /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or Iccdr Data Retention Current /UB, /LB > Vcc - 0.2V LL VIN > Vcc - 0.2V or VIN < Vss + 0.2V Chip Deselect to Data tCDR Retention Time See Data Retention Timing Diagram tR Operating Recovery Time Min 1.2 Typ1. - Max 2.7 Unit V - - 8 uA - - 15 uA 0 - - ns tRC - - ns Notes: 1. Typical values are under the condition of TA = 25°C . 2. tRC is read cycle time. DATA RETENTION TIMING DIAGRAM 1 DATA RETENTION MODE VCC 2.3V tCDR tR VIH VDR CS1>VCC-0.2V /CS1 VSS Rev.02/Jan. 2002 7 HY62LF16806A Series DATA RETENTION TIMING DIAGRAM 2 DATA RETENTION MODE VCC 2.3V tCDR tR CS2 VDR 0.4V VSS Rev.02/Jan. 2002 CS2<0.2V 8 HY62LF16806A Series PACKAGE INFORMATION 48ball Micro Ball Grid Array Package(M) BOTTOM VIEW TOP VIEW B A A1 CORNER INDEX AREA 6 5 4 3 2 1 A A B C D C C1 E 3.0 X 5.0 MIN FLAT AREA F G C1/2 H B1/2 B1 SIDE VIEW 5 E1 E2 C E SEATING PLANE A 4 r 3 D(DIAMETER) Symbol A B B1 C C1 D E E1 E2 r Rev.02/Jan. 2002 Min. 0.3 0.85 0.6 0.2 - Typ. 0.75 3.75 7.4 5.25 8.5 0.35 0.9 0.65 0.25 - Max. 0.4 0.95 0.7 0.3 0.08 Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION. 9 HY62LF16806A Series MARKING INSTRUCTION Package uBGA Marking Example H Y L F c s s t x x x x 6 8 0 6 A y w w p K O R x Index l HYLF6806A : Part Name l c : Power Consumption -D -S l ss : Speed - 55 - 70 - 85 l t : Low Low Power : Super Low Power : Temperature -C -I : 55ns : 70ns : 85ns : Commercial ( -0 ~ 70 C ) : Industrial ( -40 ~ 85 C ) l y : Year (ex : 0 = year 2000, 1= year2001) l ww : Work Week ( ex : 12 = work week 12) l p : Process Code l xxxxx : Lot No. l KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item Rev.02/Jan. 2002 10