IDT7164S IDT7164L CMOS Static RAM 64K (8K x 8-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description High-speed address/chip select access time – Military: 20/25/35/45/55/70/85/100ns (max.) – Industrial: 25/35ns (max.) – Commercial: 15/20/25/35ns (max.) Low power consumption Battery backup operation – 2V data retention voltage (L Version only) Produced with advanced CMOS high-performance technology Inputs and outputs directly TTL-compatible Three-state outputs Available in 28-pin DIP, CERDIP and SOJ Military product compliant to MIL-STD-883, Class B The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address access times as fast as 15ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a lowpower stand by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28pin 600 mil CERDIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Functional Block Diagram A0 VCC GND 65,536 BIT MEMORY ARRAY ADDRESS DECODER A12 7 0 I/O 0 I/O CONTROL I/O7 CS1 CS2 OE CONTROL LOGIC 2967 drw 01 WE DECEMBER 2001 1 ©2000 Integrated Device Technology, Inc. DSC-2967/11 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configurations NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 2 27 3 26 4 5 6 7 8 25 24 D28-1 D28-3 P28-1 P28-2 SO28-5 23 22 21 9 20 10 19 11 12 18 17 13 16 14 15 Symbol VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 VTERM Rating (2) Terminal Voltage with Respect to GND Unit -0.5 to +7.0 -0.5 to +7.0 V TA Operating Temperature 0 to +70 -55 to +125 o C TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -55 to +125 -65 to +150 o C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 2967 tbl 02 , DIP/SOJ Top View Truth Table(1,2,3) Pin Descriptions Name Description WE CS1 CS2 OE I/O Function A0 - A12 Address X H X X High-Z Deselected - Standby (ISB) I/O0 - I/O7 Data Input/Output X X L X High-Z Deselected - Standby (ISB) CS1 Chip Select X VHC VHC or VLC X High-Z Deselected - Standby (ISB1) CS2 Chip Select X X VLC X High-Z Deselected - Standby (ISB1) WE Write Enable H L H H High-Z Output Disabled OE Output Enable H L H L DATA OUT Read Data GND Ground L L H X DATAIN Write Data VCC Power Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V Recommended Operating Temperature and Supply Voltage Grade Military Input HIGH Voltage Input LOW Voltage 2.2 -0.5(1) ____ VCC + 0.5 0.8 NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. Temperature GND Vcc 0V 5V ± 10% -40 C to +85 C 0V 5V ± 10% 0OC to +70OC 0V 5V ± 10% O O -55 C to +125 C V Industrial ____ 2967 tbl 03 NOTES: 1. CS2 will power-down CS1, but CS1 will not power-down CS2. 2. H = VIH , L = VIL, X = don't care. 3. VLC = 0.2V, VHC = VCC - 0.2V 2967 tbl 01 VIL Mil. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 2967 drw 02 V IH Com'l. O O V Commercial 2967 tbl 05 2967 tbl 04 2 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 0V 8 pF CI/O I/O Capacitance VOUT = 0V 8 pF 2967 tbl 06 NOTE: 1. This parameter is determined by device characterization, but is not production tested. DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7164S15 7164L15 Symbol ICC1 ICC2 ISB ISB1 7164S20 7164L20 7164S25 7164L25 Power Com'l. Com'l. Mil. Com'l. Ind. Mil. Unit Operating Power Supply Current CS1 = VIL, CS 2 = VIH, Outputs Open V CC = Max., f = 0(2) S 110 100 110 90 90 110 mA L 100 90 100 80 80 100 Dynamic Operating Current CS1 = VIL, CS 2 = VIH, Outputs Open V CC = Max., f = fMAX(2) S 180 170 180 170 170 180 L 150 150 160 150 150 160 Standby Power Supply Current (TTL Level), CS1 > VIH, CS 2 < VIL, Outputs Open, VCC = Max., f = fMAX(2) S 20 20 20 20 20 20 L 3 3 5 3 3 5 Full Standby Power Supply Current (CMOS Level), f = 0 (2), VCC = Max. 1. CS1 > VHC and CS2 > VHC, or 2. CS2 < VLC S 15 15 20 15 15 20 L 0.2 0.2 1 0.2 0.2 1 Parameter mA mA mA 2967 tbl 07 7164S35 7164L35 Symbol ICC1 ICC2 ISB ISB1 Parameter Power Com'l. 7164S45 7164L45 7164S55 7164L55 7164S70 7164L70 7164S85/100 7164L85/100 Ind. Mil. Mil. Mil. Mil. Mil. Unit mA Operating Power Supply Current CS1 = VIL, CS 2 = VIH, Outputs Open VCC = Max., f = 0(2) S 90 90 100 100 100 100 100 L 80 80 90 90 90 90 90 Dynamic Operating Current CS1 = VIL, CS 2 = VIH, Outputs Open VCC = Max., f = fMAX(2) S 150 150 160 160 160 160 160 L 130 130 140 130 125 120 120 Standby Power Supply Current (TTL Level), CS1 > VIH, CS 2 < VIL, Outputs Open, VCC = Max., f = fMAX(2) S 20 20 20 20 20 20 20 L 3 3 5 5 5 5 5 Full Standby Power Supply Current (CMOS Level), f = 0(2) , VCC = Max. 1. CS1 > VHC and CS2 > VHC, or 2. CS2 < VLC S 15 15 20 20 20 20 20 L 0.2 0.2 1 1 1 1 1 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 6.42 3 mA mA mA 2967 tbl 08 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V ± 10%) IDT7164S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions IDT7164L Min. Max. Min. Max. Unit 10 5 ____ 5 2 µA 10 5 ____ ____ ____ 5 2 µA IOL = 8mA, VCC = Min. ____ 0.4 ____ 0.4 V IOL = 10mA, VCC = Min. ____ 0.5 ____ 0.5 2.4 ____ 2.4 ____ VCC = Max., VIN = GND to VCC MIL. COM'L. & IND ____ VCC = Max., CS1 = VIH, VOUT = GND to V CC MIL. COM'L. & IND ____ ____ IOH = -4mA, VCC = Min. ____ V 2967 tbl 09 Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Typ.(1) VCC @ Symbol Parameter Test Condition V DR VCC for Data Retention ____ ICCDR Data Retention Current MIL. COM'L. & IND tCDR(3) Chip Deselect to Data Retention Time tR(3) Operation Recovery Time IILII(3) Input Leakage Current 1. CS1 > VHC CS 2 > VHC, or 2. CS2 < VLC Max. VCC @ Min. 2.0V 3.0V 2.0V 3.0V Unit 2.0 ____ ____ ____ ____ V ____ 10 10 15 15 200 60 300 90 µA 0 ____ ____ ____ ____ ns tRC(2) ____ ____ ____ ____ ns ____ ____ ____ 2 2 µA ____ 2967 tbl 10 NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2967 tbl 11 5V 5V 480Ω 480Ω DATAOUT DATAOUT 255Ω 255Ω 30pF* 5pF* , , 2967 drw 04 2967 drw 03 Figure 2. AC Test Load (for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load *Includes scope and jig capacitances 4 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges) 7164S15(1) 7164L15(1) Symbol Parameter 7164S20(2) 7164L20(2) 7164S25 7164L25 7164S35 7164L35 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 15 ____ 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 15 ____ 19 ____ 25 ____ 35 ns tACS1(3) Chip Select-1 Access Time ____ 15 ____ 20 ____ 25 ____ 35 ns tACS2(3) Chip Select-2 Access Time ____ 20 ____ 25 ____ 30 ____ 40 ns tCLZ1,2(4) Chip Select-1, 2 to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ ns tOE Output Enable to Output Valid ____ 7 ____ 8 ____ 12 ____ 18 ns 0 ____ 0 ____ 0 ____ 0 ____ ns (4) tOLZ Output Enab le to Output in Low-Z tCHZ1,2(4) Chip Select-1,2 to Output in High-Z ____ 8 ____ 9 ____ 13 ____ 15 ns tOHZ(4) Output Disab le to Output in High-Z ____ 7 ____ 8 ____ 10 ____ 15 ns tOH Output Hold from Address Change 5 ____ 5 ____ 5 ____ 5 ____ ns tPU(4) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(4) Chip Deselect to Power Down Time ____ 15 ____ 20 ____ 25 ____ 35 ns Write Cycle tWC Write Cycle Time 15 ____ 20 ____ 25 ____ 35 ____ ns tCW1,2 Chip Select to End-of-Write 14 ____ 15 ____ 18 ____ 25 ____ ns tAW Address Valid to End-of-Write 14 ____ 15 ____ 18 ____ 25 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 15 ____ 21 ____ 25 ____ ns tAS Address Set-up Time tWP Write Pulse Width 14 ____ tWR1 Write Recovery Time (CS1, WE) 0 ____ 0 ____ 0 ____ 0 ____ ns tWR2 Write Recovery Time (CS2) 5 ____ 5 ____ 5 ____ 5 ____ ns tWHZ(4) Write Enab le to Output in High-Z ____ 6 ____ 8 ____ 10 ____ 14 ns tDW Data to Write Time Overlap 8 ____ 10 ____ 13 ____ 15 ____ ns tDH1 Data Hold from Write Time (CS1, WE) 0 ____ 0 ____ 0 ____ 0 ____ ns tDH2 Data Hold from Write Time (CS 2) 5 ____ 5 ____ 5 ____ 5 ____ ns 4 ____ 4 ____ 4 ____ 4 ____ ns (4) tOW Output Active from End-of-Write NOTES: 1. 0° to +70°C temperature range only. 2. 0° to +70°C and –55°C to +125°C temperature ranges only. 3. Both chip selects must be active for the device to be selected. 4. This parameter is guaranteed by device characterization, but is not production tested. 6.42 5 2967 tbl 12 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges) 7164S45 7164L45 Symbol Parameter 7164S55 7164L55 7164S70 7164L70 7164S85/100 7164L85/100 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 45 ____ 55 ____ 70 ____ 85/100 ____ ns tAA Address Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS1(1) Chip Select-1 Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS2(1) Chip Select-2 Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tCLZ1,2(2) Chip Select-1, 2 to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ ns ____ 25 ____ 30 ____ 35 ____ 40 ns 0 ____ 0 ____ 0 ____ 0 ____ ns tOE Output Enable to Output Valid tOLZ(2) Output Enab le to Output in Low-Z tCHZ1,2(2) Chip Select-1,2 to Output in High-Z ____ 20 ____ 25 ____ 30 ____ 35 ns tOHZ(2) Output Disab le to Output in High-Z ____ 20 ____ 25 ____ 30 ____ 35 ns tOH Output Hold from Address Change 5 ____ 5 ____ 5 ____ 5 ____ ns tPU(2) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(2) Chip Deselect to Power Down Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns 45 ____ 55 ____ 70 ____ 85/100 ____ ns 50 ____ 60 ____ 75 ____ ns Write Cycle tWC Write Cycle Time tCW1,2 Chip Select to End-of-Write 33 ____ tAW Address Valid to End-of-Write 33 ____ 50 ____ 60 ____ 75 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns 25 ____ 50 ____ 60 ____ 75 ____ ns 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width tWR1 Write Recovery Time (CS1, WE) 0 ____ tWR2 Write Recovery Time (CS2) 5 ____ 5 ____ 5 ____ 5 ____ ns tWHZ(2) Write Enab le to Output in High-Z ____ 18 ____ 25 ____ 30 ____ 35 ns tDW Data to Write Time Overlap 20 ____ 25 ____ 30 ____ 35 ____ ns tDH1 Data Hold from Write Time (CS1, WE) 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ ns 4 ____ 4 ____ 4 ____ ns tDH2 Data Hold from Write Time (CS 2) 5 ____ tOW(2) Output Active from End-of-Write 4 ____ NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. 6 2967 tbl 13 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tOH tAA OE tOE tOLZ (5) CS2 tACS2 tCHZ2 (5) tCLZ2 (5) CS1 tOHZ (5) tCHZ1 (5) tACS1 tCLZ1(5) DATAOUT DATA VALID 2967 drw 05 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH tOH DATAOUT DATA VALID 2967 drw 06 Timing Waveform of Read Cycle No. 3(1,3,4) CS1 CS2 tACS2 tCLZ2 (5) tACS1 tCLZ1 (5) DATAOUT POWER SUPPLY CURRENT tCHZ2 tCHZ1 (5) (5) DATA VALID tPU ICC ISB tPD NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 7 2967 drw 07 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5) tWC ADDRESS CS2 CS1 tWR1(2) tAW tAS WE (3) tWP (5) tOW(6) DATAOUT tDH1,2 tDW tWHZ (6) DATAIN DATA VALID 2967 drw 08 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1) tWC ADDRESS tWR2(2) tAS CS2 tWR1(2) tCW CS1 (4) tAW WE tDW DATAIN tDH1,2 DATA VALID 2967 drw 09 NOTES: 1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified t WP. 6. Transition is measured ±200mV from steady state. 8 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V VDR ≥ 2V tCDR CS VIH tR VIH VDR 2967 drw 10 Ordering Information Commercial IDT 7164 Device Type X XX XXX X Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) Y* P** TP* 300 mil SOJ (SO28-5) 600 mil Plastic DIP (P28-1) 300 mil Plastic DIP (P28-2) 15 20 25 35 Speed in nanoseconds S L Standard Power Low Power * Available for 15ns and 20ns speed grades only. ** Available for 25ns and 35ns speed grades only. 2967 drw 11 6.42 9 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Ordering Information Industrial IDT 7164 Device Type X XX XXX X Power Speed Package Process/ Temperature Range I Industrial (–40°C to +85°C) P Y 600 mil Plastic DIP (P28-1) 300 mil Plastic SOJ (PJ28) 25 35 Speed in nanoseconds S L Standard Power Low Power 2967 drw 12 Ordering Information Military IDT 7164 Device Type X XX XXX X Power Speed Package Process/ Temperature Range B Military (–55°C to +125°C) Compliant with MIL-STD-883, Class B D TD 600 mil CERDIP (D28-1) 300 mil CERDIP (D28-3) 20* 25 35 45 55 70 85 100** Speed in nanoseconds S L Standard Power Low Power * Available only in 600mil CERDIP (D28-1) and 300mil CERDIP (D28-1) and 300mil CERDIP (D28-3) packaging for a low power. ** Available only in 600 mil CERDIP (D28-1) packaging. 2967 drw 13 10 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Datasheet Document History 1/13/2000 Pp. 1, 2, 3, 5, 10 Pp. 1, 3, 9 Pp. 1, 3, 6, 10 Pg. 3 Pp. 5, 6 Pg. 8 Pp. 9, 10 Pg. 11 08/09/00 02/01/01 12/07/01 Pg. 10 Updated to new format Added Industrial Temperature range offerings Removed commercial 70ns speed grade offering Added 100ns speed grade specification details Revised notes and footnotes in DC Electrical tables Revised notes and footnotes in AC Electrical tables Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes Separated Ordering Information into commercial, industrial, and military offerings Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Add PJ28 to Industrial temperature. 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