SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs ADAU1401 FEATURES GENERAL DESCRIPTION 28-/56-bit, 50 MIPS digital audio processor 2 ADCs: SNR of 100 dB, THD + N of −83 dB 4 DACs: SNR of 104 dB, THD + N of −90 dB Complete standalone operation Self-boot from serial EEPROM Auxiliary ADC with 4-input mux for analog control GPIOs for digital controls and outputs Fully programmable with SigmaStudio graphical tool 28-bit × 28-bit multiplier with 56-bit accumulator for full double-precision processing Clock oscillator for generating master clock from crystal PLL for generating master clock from 64 × fS, 256 × fS, 384 × fS, or 512 × fS clocks Flexible serial data input/output ports with I2S-compatible, left-justified, right-justified, and TDM modes Sampling rates of up to 192 kHz supported On-chip voltage regulator for compatibility with 3.3 V systems 48-lead, plastic LQFP The ADAU1401 is a complete single-chip audio system with a 28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like control interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image widening. This processing can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, providing dramatic improvements in perceived audio quality. Its signal processing is comparable to that found in high end studio equipment. Most processing is done in full 56-bit, double-precision mode, resulting in very good low level signal performance. The ADAU1401 is a fully programmable DSP. The easy to use SigmaStudio™ software allows the user to graphically configure a custom signal processing flow using blocks such as biquad filters, dynamics processors, level controls, and GPIO interface controls. APPLICATIONS ADAU1401 programs can be loaded on power-up either from a serial EEPROM through its own self-boot mechanism or from an external microcontroller. On power-down, the current state of the parameters can be written back to the EEPROM from the ADAU1401 to be recalled the next time the program is run. Multimedia speaker systems MP3 player speaker docks Automotive head units Minicomponent stereos Digital televisions Studio monitors Speaker crossovers Musical instrument effects processors In-seat sound systems (aircraft/motor coaches) Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog input to analog output dynamic. Each ADC has a THD + N of −83 dB, and each DAC has a THD + N of −90 dB. Digital input and output ports allow a glueless connection to additional ADCs and DACs. The ADAU1401 communicates through an I2C® bus or a 4-wire SPI port. FUNCTIONAL BLOCK DIAGRAM PLL DIGITAL DIGITAL ANALOG ANALOG PLL LOOP VDD GROUND VDD GROUND MODE FILTER 3.3V 3 3 3 3 3 1.8V REGULATOR CRYSTAL 2 CLOCK OSCILLATOR PLL ADAU1401 2-CHANNEL ANALOG INPUT FILTA/ ADC_RES 2 DAC STEREO ADC 28-/56-BIT, 50MIPS AUDIO PROCESSOR CORE 40ms DELAY MEMORY 2 RESET/ MODE SELECT CONTROL INTERFACE AND SELFBOOT 8-BIT AUX ADC 8-CH DIGITAL INPUT DAC FILTD/CM 4-CHANNEL ANALOG OUTPUT 8-CH DIGITAL OUTPUT GPIO 5 RESET SELF BOOT I2C/SPI AND WRITEBACK 4 DIGITAL IN OR GPIO 4 4 AUX ADC DIGITAL OUT OR OR GPIO GPIO 06752-001 INPUT/OUTPUT MATRIX Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADAU1401 TABLE OF CONTENTS Features .............................................................................................. 1 RAMs and Registers....................................................................... 29 Applications....................................................................................... 1 Address Maps.............................................................................. 29 General Description ......................................................................... 1 Parameter RAM.......................................................................... 29 Functional Block Diagram .............................................................. 1 Data RAM ................................................................................... 29 Revision History ............................................................................... 2 Read/Write Data Formats ......................................................... 29 Specifications..................................................................................... 3 Control Register Map..................................................................... 31 Analog Performance .................................................................... 3 Control Register Details ................................................................ 33 Digital Input/Output.................................................................... 4 2048 to 2055 (0x0800 to 0x0807)—Interface Registers......... 33 Power.............................................................................................. 5 2056 (0x808)—GPIO Pin Setting Register.............................. 34 Temperature Range ...................................................................... 5 PLL and Oscillator........................................................................ 5 2057 to 2060 (0x809 to 0x80C)—Auxiliary ADC Data Registers ............................................................................. 35 Regulator........................................................................................ 5 2064 to 2068 (0x0810 to 0x814)—Safeload Data Registers.........36 Digital Timing Specifications ..................................................... 6 2069 to 2073 (0x0815 to 0x819) Safeload Address Registers ......36 Digital Timing Diagrams................................................................. 7 2074 to 2075 (0x081A to 0x081B)—Data Capture Registers......37 Absolute Maximum Ratings............................................................ 9 2076 (0x081C)—DSP Core Control Register ......................... 38 Thermal Resistance ...................................................................... 9 2078 (0x081E)—Serial Output Control Register ................... 39 ESD Caution.................................................................................. 9 2079 (0x081F)—Serial Input Control Register....................... 40 Pin Configuration and Function Descriptions........................... 10 2080 to 2081 (0x0820 to 0x0821)—Multipurpose Pin Configuration Registers............................................................. 41 Typical Performance Characteristics ........................................... 13 System Block Diagram ................................................................... 14 Overview.......................................................................................... 15 Initialization .................................................................................... 16 Power-Up Sequence ................................................................... 16 Control Registers Setup ............................................................. 16 Recommended Program/Parameter Loading Procedure ..... 16 Power-Reduction Modes ........................................................... 16 Using the Oscillator.................................................................... 17 Setting Master Clock/PLL Mode .............................................. 17 Voltage Regulator ....................................................................... 18 Audio ADCs .................................................................................... 19 Audio DACs .................................................................................... 20 Control Ports................................................................................... 21 I2C Port ........................................................................................ 22 SPI Port ........................................................................................ 25 Self-Boot ...................................................................................... 26 Signal Processing ............................................................................ 28 2082 (0x0822)—Auxiliary ADC and Power Control ............ 42 2084 (0x0824)—Auxiliary ADC Enable.................................. 42 2086 (0x0826)—Oscillator Power-Down................................ 42 2087 (0x0827)—DAC Setup...................................................... 43 Multipurpose Pins .......................................................................... 44 Auxiliary ADC............................................................................ 44 General-Purpose Input/Output Pins....................................... 44 Serial Data Input/Output Ports ................................................ 44 Layout Recommendations............................................................. 47 Parts Placement .......................................................................... 47 Grounding ................................................................................... 47 Typical Application Schematics.................................................... 48 Self-Boot Mode........................................................................... 48 I2C Control .................................................................................. 49 SPI Control.................................................................................. 50 Outline Dimensions ....................................................................... 51 Ordering Guide .......................................................................... 51 Numeric Formats........................................................................ 28 Programming .............................................................................. 28 REVISION HISTORY 7/07—Revision 0: Initial Version Rev. 0 | Page 2 of 52 ADAU1401 SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted. ANALOG PERFORMANCE Specifications are guaranteed at 25°C (ambient). Table 1. Parameter ADC INPUTS Number of Channels Resolution Full-Scale Input Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk DC Bias Gain Error DAC OUTPUTS Number of Channels Resolution Full-Scale Analog Output Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted Total Harmonic Distortion + Noise Crosstalk Interchannel Gain Mismatch Gain Error DC Bias VOLTAGE REFERENCE Absolute Voltage (CM) AUXILIARY ADC Full-Scale Analog Input INL DNL Offset Input Impedance Min Typ Max Unit 2 24 100 (283) Bits μArms (μA p-p) 100 dB 100 −83 25 −82 1.5 dB dB mdB dB V % Test Conditions/Comments Stereo input 2 Vrms input with 20 kΩ (18 kΩ external + 2 kΩ internal) series resistor −60 dB with respect to full-scale analog input 95 1.4 −11 250 1.6 +11 4 24 0.9 (2.5) Bits Vrms (V p-p) 104 dB 104 −90 −100 25 dB dB dB mdB % V −3 dB with respect to full-scale analog input Analog channel-to-channel crosstalk Two stereo output channels −60 dB with respect to full-scale analog output 99 −10 1.4 1.5 250 +10 1.6 1.4 1.5 1.6 V 2.8 3.0 0.5 1.0 15 30 3.1 42 V LSB LSB mV kΩ Typ Max Unit 17.8 −1 dB with respect to full-scale analog output Analog channel-to-channel crosstalk Specifications are guaranteed at 130°C (ambient). Table 2. Parameter ADC INPUTS Number of Channels Resolution Full-Scale Input Min 2 24 100 (283) Test Conditions/Comments Stereo input Bits μArms (μA p-p) Rev. 0 | Page 3 of 52 2 Vrms input with 20 kΩ (18 kΩ external + 2 kΩ internal) series resistor ADAU1401 Parameter Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk DC Bias Gain Error DAC OUTPUTS Number of Channels Resolution Full-Scale Analog Output Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted Total Harmonic Distortion + Noise Crosstalk Interchannel Gain Mismatch Gain Error DC Bias VOLTAGE REFERENCE Absolute Voltage (CM) AUXILIARY ADC Full-Scale Analog Input INL DNL Offset Input Impedance Min Typ Max Unit 100 dB 100 −83 25 −82 1.5 dB dB mdB dB V % Test Conditions/Comments −60 dB with respect to full-scale analog input 92 1.4 −11 250 1.6 +11 −3 dB with respect to full-scale analog input Analog channel-to-channel crosstalk 4 24 0.9 (2.5) Bits Vrms (V p-p) Two stereo output channels 104 dB 104 −90 −100 25 dB dB dB mdB % V −60 dB with respect to full-scale analog output 98 −10 1.4 1.5 250 +10 1.6 1.4 1.5 1.6 V 2.8 3.0 0.5 1.0 15 30 3.1 V LSB LSB mV kΩ 17.8 42 −1 dB with respect to full-scale analog output Analog channel-to-channel crosstalk DIGITAL INPUT/OUTPUT Table 3. Parameter Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Leakage, High (IIH) Input Leakage, Low (IIL) Bidirectional Pin Pull-Up Current, Low MCLKI Input Leakage, High (IIH) MCLKI Input Leakage, Low (IIL) High Level Output Voltage (VOH), IOH = 2 mA Low Level Output Voltage (VOL), IOL = 2 mA Input Capacitance GPIO Output Drive 1 Min 2.0 Typ Max 1 IOVDD 0.8 1 1 150 3 3 2.0 0.8 5 2 Unit V V μA μA μA μA μA V V pF mA Comments Excluding MCLKI Excluding MCLKI and bidirectional pins Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. Rev. 0 | Page 4 of 52 ADAU1401 POWER Table 4. Parameter SUPPLY VOLTAGE Analog Voltage Digital Voltage PLL Voltage IOVDD Voltage SUPPLY CURRENT Analog Current (AVDD and PVDD) Digital Current (DVDD) Analog Current, Reset Digital Current, Reset DISSIPATION Operation (AVDD, DVDD, PVDD) 2 Reset, All Supplies POWER SUPPLY REJECTION RATIO (PSRR) 1 kHz, 200 mV p-p Signal at AVDD 1 2 Min Max 1 Typ Unit 3.3 1.8 3.3 3.3 V V V V 50 40 35 1.5 85 60 55 4.5 mA mA mA mA 286.5 118 mW mW 50 dB Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins. TEMPERATURE RANGE Table 5. Parameter Functionality Guaranteed Min −40 Typ Max 105 Unit °C ambient PLL AND OSCILLATOR Table 6. PLL and Oscillator 1 Parameter PLL Operating Range PLL Lock Time Crystal Oscillator Transconductance (gm) 1 Min MCLK_Nom − 20% Typ Max MCLK_Nom + 20% 20 78 Unit MHz ms mmho Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. REGULATOR Table 7. Regulator 1 Parameter DVDD Voltage 1 Min 1.7 Typ 1.8 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit. Rev. 0 | Page 5 of 52 Max 1.84 Unit V ADAU1401 DIGITAL TIMING SPECIFICATIONS Table 8. Digital Timing 1 Parameter MASTER CLOCK tMP tMP tMP tMP SERIAL PORT tBIL tBIH tLIS tLIH tSIS tSIH tLOS tLOH tTS tSODS tSODM SPI PORT fCCLK tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tSCR tSCF tSDR tSDF tBFT MULTIPURPOSE PINS AND RESET tGRT tGFT tGIL tRLPW 1 tMIN 36 48 73 291 Limit tMAX Unit Description 244 366 488 1953 ns ns ns ns MCLKI period, 512 × fS mode. MCLKI period, 384 × fS mode. MCLKI period, 256 × fS mode. MCLKI period, 64 × fS mode. 5 40 40 ns ns ns ns ns ns ns ns ns ns ns INPUT_BCLK low pulse width. INPUT_BCLK high pulse width. INPUT_LRCLK setup. Time to INPUT_BCLK rising. INPUT_LRCLK hold. Time from INPUT_BCLK rising. SDATA_INx setup. Time to INPUT_BCLK rising. SDATA_INx hold. Time from INPUT_BCLK rising. OUTPUT_LRCLK setup in slave mode. OUTPUT_LRCLK hold in slave mode. OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew. SDATA_OUTx delay in slave mode. Time from OUTPUT_BCLK falling. SDATA_OUTx delay in master mode. Time from OUTPUT_BCLK falling. MHz ns ns ns ns ns ns ns ns CCLK frequency. CCLK pulse width low. CCLK pulse width high. CLATCH setup. Time to CCLK rising. CLATCH hold. Time from CCLK rising. CLATCH pulse width high. CDATA setup. Time to CCLK rising. CDATA hold. Time from CCLK rising. COUT delay. Time from CCLK falling. kHz μs μs μs μs ns ns ns ns ns SCL frequency. SCL high. SCL low. Setup time, relevant for repeated start condition. Hold time. After this period, the first clock is generated. Data setup time. SCL rise time. SCL fall time. SDA rise time. SDA fall time. Bus-free time. Time between stop and start. ns ns μs ns GPIO rise time. GPIO fall time. GPIO input latency. Time until high/low value is read by core. RESET low pulse width. 40 40 10 10 10 10 10 10 6.25 80 80 0 100 80 0 80 101 400 0.6 1.3 0.6 0.6 100 300 300 300 300 0.6 50 50 1.5 × 1/fS 20 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 67). Rev. 0 | Page 6 of 52 ADAU1401 DIGITAL TIMING DIAGRAMS tLIH tBIH INPUT_BCLK tBIL tLIS INPUT_LRCLK tSIS SDATA_INx LEFT-JUSTIFIED MODE MSB MSB–1 tSIH tSIS SDATA_INx I2S MODE MSB tSIH tSIS tSIS SDATA_INx RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 06752-002 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) Figure 2. Serial Input Port Timing tLCH tBIH tTS OUPUT_BCLK tBIL tLOS OUPUT_LRCLK SDATA_OUTx I2S MODE tSODS tSODM MSB MSB–1 tSODS tSODM MSB tSODS tSODM SDATA_OUTx RIGHT-JUSTIFIED MODE MSB LSB 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 06752-003 SDATA_OUTx LEFT-JUSTIFIED MODE 16-BIT CLOCKS (16-BIT DATA) Figure 3. Serial Output Port Timing Rev. 0 | Page 7 of 52 ADAU1401 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS COUT 06752-004 tCOD Figure 4. SPI Port Timing tDS tSCH tSCH SDA tSCLH SCL tSCLL tSCS tSCF tBFT 06752-005 tSCR 2 Figure 5. I C Port Timing tMP RESET tRLPW Figure 6. Master Clock and RESET Timing Rev. 0 | Page 8 of 52 06752-006 MCLKI ADAU1401 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 9. Parameter DVDD to GND AVDD to GND IOVDD to GND Digital Inputs Maximum Junction Temperature Storage Temperature Range Soldering (10 sec) Rating 0 V to 2.2 V 0 V to 4.0 V 0 V to 4.0 V DGND − 0.3 V, IOVDD + 0.3 V 135°C −65°C to +150°C 300°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 10. Thermal Resistance Package Type 48-Lead LQFP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 52 θJA 72 θJC 19.5 Unit °C/W ADAU1401 AGND PLL_MODE0 PLL_MODE1 CM FILTD AGND VOUT3 VOUT2 VOUT1 VOUT0 FILTA AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 ADC1 2 ADC_RES 36 AVDD 35 PLL_LF 3 34 PVDD ADC0 4 33 PGND RESET 5 32 MCLKI 31 OSCO 30 RSVD PIN 1 INDICATOR ADAU1401 TOP VIEW (Not to Scale) SELFBOOT 6 ADDR0 7 MP4 8 29 MP2 MP5 9 28 MP3 MP1 10 MP0 11 27 MP8 26 MP9 DGND 12 25 DGND 06752-007 DVDD SCL/CCLK SDA/COUT CLATCH/WP ADDR1/CDATA/WB MP11 IOVDD VDRIVE MP10 MP6 MP7 DVDD 13 14 15 16 17 18 19 20 21 22 23 24 Figure 7. 48-Lead LQFP Pin Configuration Table 11. Pin Function Descriptions Pin No. 1, 37, 42 Mnemonic AGND Type 1 PWR Page No. 2 ADC1 A_IN 19 3 ADC_RES A_IN 19 4 ADC0 A_IN 19 5 RESET D_IN 6 SELFBOOT D_IN 26 7 ADDR0 D_IN 22 8 9 10 11 12, 25 MP4 MP5 MP1 MP0 DGND D_IO D_IO D_IO D_IO PWR 44 44 44 44 13, 24 DVDD PWR Description Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. AGND should be decoupled to an AVDD pin with a 100 nF capacitor. Analog Audio Input 1. Full-scale 100 μArms input. Current input allows input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 Vrms full-scale input. ADC Reference Current. The full-scale current of the ADCs can be set with an external 18 kΩ resistor connected between this pin and ground. Analog Audio Input 0. Full-scale 100 μArms input. Current input allows input voltage level to be scaled with an external resistor. An 18 kΩ resistor gives a 2 Vrms full-scale input. Active Low Reset Input. Reset is triggered on a high-to-low edge, and the ADAU1401 exits reset on a low-to-high edge. For more information about initialization, see the Power-Up Sequence section. Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot (high). Setting this pin high initiates a self-boot operation when the ADAU1401 is brought out of a reset. This pin can be tied directly to the control voltage or pulled up/down with a resistor. I2C and SPI Address 0. In combination with ADDR1, this pin allows up to four ADAU1401s to be used on the same I2C bus and up to two ICs to be used with a common SPI CLATCH signal. Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK). Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK). Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0). Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1). Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. DGND should be decoupled to a DVDD pin with a 100 nF capacitor. 1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND with a 100 nF capacitor. Rev. 0 | Page 10 of 52 ADAU1401 Pin No. 14 15 Mnemonic MP7 MP6 Type 1 D_IO D_IO Page No. 44 44 16 17 MP10 VDRIVE D_IO A_OUT 44 18 18 IOVDD PWR 19 20 MP11 ADDR1/CDATA/WB D_IO D_IN 44 22, 25, 26 21 CLATCH/WP D_IO 24, 26 22 SDA/COUT D_IO 22, 25 23 SCL/CCLK D_IO 22, 25 26 MP9 D_IO/A_IO 44 27 MP8 D_IO/A_IO 44 28 MP3 D_IO/A_IO 44 29 MP2 D_IO/A_IO 44 30 31 RSVD OSCO X D_OUT 17 32 MCLKI D_IN 17 33 PGND PWR 34 PVDD PWR 35 PLL_LF A_OUT 36, 48 AVDD PWR 17 Description Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0). Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is driven from VDRIVE. Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage that should be seen on the digital input pins. This pin is also the supply for the digital output signals on the control port and MP pins. IOVDD should always be set to 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). ADDR1: I2C Address 1. In combination with ADDR0, this sets the I2C address of the IC so that four ADAU1401s can be used on the same I2C bus. CDATA: SPI Data Input. WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the EEPROM messages) edge on this pin triggers a writeback of the interface registers to the external EEPROM. This function can be used to save parameter data on power-down. CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction can take a different number of CCLKs to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output when in self-boot mode. The ADAU1401 pulls this low to prohibit writes to an external EEPROM. This pin should be pulled high to 3.3 V. SDA: I2C Data. This pin is a bidirectional open-collector. The line connected to this pin should have a 2.2 kΩ pull-up resistor. COUT: This SPI data output is used for reading back registers and memory locations. It is three-stated when an SPI read is not active. SCL: I2C Clock. This pin is always an open-collector input when in I2C control mode. In self-boot mode, this pin is an open-collector output (I2C master). The line connected to this pin should have a 2.2 kΩ pull-up resistor. CCLK: SPI Clock. This pin can either run continuously or be gated off between SPI transactions. Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0. Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3. Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary ADC Input 2. Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary ADC Input 1. Reserved. Tie to ground, either directly or through a pull-down resistor. Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be connected between this pin and the crystal. This output should not be used to directly drive a clock to another IC. If the crystal oscillator is not used, this pin can be left disconnected. Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or be the input from the crystal oscillator circuit. PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor. 3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This should be decoupled to PGND with a 100 nF capacitor. PLL Loop Filter Connection. Two capacitors and a resistor need to be connected to this pin, as shown in Figure 15. 3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF capacitor. Rev. 0 | Page 11 of 52 ADAU1401 Pin No. 38 39 Mnemonic PLL_MODE0 PLL_MODE1 Type 1 D_IN D_IN 40 CM A_OUT 41 FILTD A_OUT 43 44 45 46 47 VOUT3 VOUT2 VOUT1 VOUT0 FILTA A_OUT A_OUT A_OUT A_OUT A_OUT Page No. 17 17 20 20 20 20 Description PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency of the master clock PLL. See the Setting Master Clock/PLL Mode section for more details. 1.5 V Common-Mode Reference. A 47 μF decoupling capacitor should be connected between this pin and ground to reduce crosstalk between the ADCs and DACs. The material of the capacitors is not critical. This pin can be used to bias external analog circuits, as long as those circuits are not drawing current from the pin (such as when CM is connected to the noninverting input of an op amp). DAC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and ground. The capacitor material is not critical. The voltage on this pin is 1.5 V. VOUT0 to VOUT3 are the DAC Outputs. The full-scale output voltage is 0.9 Vrms. These outputs can be used with either active or passive output reconstruction filters. ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between this pin and ground. The capacitor material is not critical. The voltage on this pin is 1.5 V. 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog input/output. Rev. 0 | Page 12 of 52 ADAU1401 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.20 fS = 48kHz 0.15 fS = 48kHz 0.08 0.06 0.10 0.04 0.02 (dB) (dB) 0.05 0 0 –0.02 –0.05 –0.04 –0.10 06752-008 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 06752-010 –0.06 –0.15 –0.08 –0.10 2.2 0 0.5 1.0 Figure 8. ADC Pass-Band Filter Response 10 –10 –20 –20 –30 –30 –40 –40 (dB) –10 –50 –50 –60 –70 –70 –80 –80 06752-009 –60 –90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fS = 48kHz 0 fS = 48kHz 4.5 06752-011 0 (dB) 2.0 Figure 10. DAC Pass-Band Filter Response 10 –100 1.5 FREQUENCY (kHz) FREQUENCY (kHz) –90 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (kHz) FREQUENCY (kHz) Figure 11. DAC Stop-Band Filter Response Figure 9. ADC Stop-Band Filter Response Rev. 0 | Page 13 of 52 1.8 2.0 ADAU1401 SYSTEM BLOCK DIAGRAM 3.3V 100nF 100nF 3.3V TO 1.8V REGULATOR CIRCUIT 100nF 100nF 10µF + 10µF + IOVDD PVDD AVDD DVDD VDRIVE 18kΩ ADC0 AUDIO ADC INPUT SIGNALS 18kΩ 18kΩ VOUT0 ADC1 VOUT1 DAC OUTPUT FILTERS (ACTIVE OR PASSIVE) ADC_RES VOUT2 + 10µF FILTA VOUT3 100nF FILTD ADCs 10µF MP0 MULTIPURPOSE PIN INTERFACES + 100nF MP1 ADAU1401 MP2 DACs MP3 CM MP4 10µF MP5 + 100nF MP6 MP7 MP8 MP9 MP10 ADDR0 MP11 ADDR1/CDATA/WB CLATCH/WP 3.3V SDA/COUT 475Ω 3.3nF 56nF SCL/CCLK PLL_LF PLL_MODE0 PLL SETTINGS EEPROM, MICROCONTROLLER, AND/OR SELFBOOT LOGIC SELFBOOT PLL_MODE1 MCLKI RESET RESET LOGIC 3MHz TO 25MHz 22pF 100Ω OSCO AGND DGND PGND 06752-012 22pF RSVD Figure 12. System Block Diagram Rev. 0 | Page 14 of 52 ADAU1401 OVERVIEW The core of the ADAU1401 is a 28-bit DSP (56-bit with doubleprecision processing) optimized for audio processing. The program and parameter RAMs can be loaded with a custom audio processing signal flow built by using SigmaStudio graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks, such as equalization filters, dynamics processors, audio delays, and mixer levels. A safeload feature allows for transparent parameter updates and prevents clicks in the output signals. The program RAM, parameter RAM, and register contents can be saved in an external EEPROM, from which the ADAU1401 can self-boot on startup. In this standalone mode, parameters can be controlled through the on-board multipurpose pins. The ADAU1401 can accept controls from switches, potentiometers, rotary encoders, and IR receivers. Parameters such as volume and tone settings can be saved to the EEPROM on power-down and recalled again on power-up. The ADAU1401 can operate with digital or analog inputs and outputs, or a mix of both. The stereo ADC and four DACs each have an SNR of at least +100 dB and a THD + N of at least −83 dB. The 8-channel, flexible serial data input/output ports allow glueless interconnection to a variety of ADCs, DACs, general-purpose DSPs, S/PDIF receivers and transmitters, and sample rate converters. The serial ports of the ADAU1401 can be configured in I2S, left-justified, right-justified, or TDM serial port compatible modes. Twelve multipurpose (MP) pins allow the ADAU1401 to receive external control signals as input and to output flags or controls to other devices in the system. The MP pins can be configured as digital I/Os, inputs to the 4-channel auxiliary ADC, or serial data I/O ports. As inputs, they can be connected to buttons, switches, rotary encoders, potentiometers, IR receivers, or other external circuitry to control the internal signal processing program. When configured as outputs, these pins can be used to drive LEDs, control other ICs, or connect to other external circuitry in an application. The ADAU1401 has a sophisticated control port that supports complete read/write capability of all memory locations. Control registers are provided to offer complete control of the chip’s configuration and serial modes. The ADAU1401 can be configured for either SPI or I2C control, or can self-boot from an external EEPROM. An on-board oscillator can be connected to an external crystal to generate the master clock. In addition, a master clock phaselocked loop (PLL) allows the ADAU1401 to be clocked from a variety of different clock speeds. The PLL can accept inputs of 64 × fS, 256 × fS, 384 × fS, or 512 × fS to generate the internal master clock of the core. The SigmaStudio software is used to program and control the SigmaDSP® through the control port. Along with designing and tuning a signal flow, the tools can be used to configure all of the DSP registers and burn a new program into the external EEPROM. SigmaStudio’s graphical interface allows anyone with digital or analog audio processing knowledge to easily design a DSP signal flow and port it to a target application. At the same time, it provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design. In SigmaStudio, the user can connect graphical blocks (such as biquad filters, dynamics processors, mixers, and delays), compile the design, and load the program and parameter files into the ADAU1401 memory through the control port. Signal processing blocks available in the provided libraries include • • • • • • • • • • • • • Single- and double-precision biquad filters Processors with peak or rms detection for monochannel and multichannel dynamics Mixers and splitters Tone and noise generators Fixed and variable gain Loudness Delay Stereo enhancement Dynamic bass boost Noise and tone sources FIR filters Level detectors GPIO control and conditioning Additional processing blocks are always being developed. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms. The ADAU1401 operates from a 1.8 V digital power supply and a 3.3 V analog supply. An on-board voltage regulator can be used to operate the chip from a single 3.3 V supply. It is fabricated on a single monolithic, integrated circuit and is packaged in a 48-lead LQFP for operation over the 0°C to +70°C temperature range. Rev. 0 | Page 15 of 52 ADAU1401 INITIALIZATION 1. 2. 3. 4. 5. Apply power to ADAU1401. Wait for PLL to lock. Load SigmaDSP program and parameters. Set up registers (including multipurpose pins and digital interfaces). Turn off the default muting of the converters, clear the data registers, and initialize the DAC setup register (see the Control Registers Setup section for specific settings). To only test analog audio pass-through (ADCs to DACs), Steps 3 and 4 can be skipped and the default internal program can be used. Table 12 lists typical times to boot the ADAU1401 into an application’s operational state, assuming a 400 kHz I2C clock loading a full program, parameter set, and all registers (about 8.5 kB). In reality, most applications will not fill the RAMs and therefore boot time (Column 3 of Table 12) will be less. CONTROL REGISTERS SETUP The following registers must be set as described in this section to initialize the ADAU1401. These settings are the basic minimum settings needed to operate the IC with an analog input/output of 48 kHz. More registers may need to be set, depending on the application. See the RAMs and Registers section for additional settings. DSP Core Control Register (Address 2076) POWER-UP SEQUENCE Set Bits [4:2] (ADM, DAM, and CR) each to 1. The ADAU1401 has a built-in power-up sequence that initializes the contents of all internal RAMs on power-up or when the device is brought out of a reset. On the positive edge of RESET, the contents of the internal program boot ROM are copied to the internal program RAM memory, the parameter RAM is filled with values (all 0s) from its associated boot ROM, and all registers are initialized to 0s. The default boot ROM program copies audio from the inputs to the outputs without processing it (see Figure 13). In this program, serial digital Input 0 and Input 1 are output on DAC0 and DAC1 and serial digital Output 0 and Output 1. ADC0 and ADC1 are output on DAC2 and DAC3. The data memories are also zeroed at powerup. New values should not be written to the control port until the initialization is complete. DAC Setup Register (Address 2087) Table 12. Power-Up Time 3. 4. 5. MCLKI Input 3.072 MHz (64 × fS) 11.289 MHz (256 × fS) 12.288 MHz (256 × fS) 18.432 MHz (384 × fS) 24.576 MHz (512 × fS) Init. Time 85 ms 23 ms 21 ms 16 ms 11 ms Max Program/ Parameter/Register Boot Time (I2C) 175 ms 175 ms 175 ms 175 ms 175 ms Set Bits [0:1] (DS [1:0]) to 01. RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE When writing large amounts of data to the program or parameter RAM in direct write mode, the processor core should be disabled to prevent unpleasant noises from appearing in the audio output. 1. 2. Total 260 ms 198 ms 196 ms 191 ms 186 ms The PLL start-up time lasts for 218 cycles of the clock on the MCLKI pin. This time ranges from 10.7 ms for a 24.576 MHz (512 × fS) input clock to 85.3 ms for a 3.072 MHz (64 × fS) input clock and is measured from the rising edge of RESET. Following the PLL startup, the duration of the ADAU1401 boot cycle is about 42 μs for a fS of 48 kHz. The user should avoid writing to or reading from the ADAU1401 during this start-up time. For an MCLK input of 12.288 MHz, the full initialization sequence (PLL startup plus boot cycle) is approximately 21 ms. As the device comes out of a reset, the clock mode is immediately set by the PLL_MODE0 and PLL_MODE1 pins. The reset is synchronized to the falling edge of the internal clock. Set Bit 3 and Bit 4 (active low) of the core control register to 1 to mute the ADCs and DACs. This begins a volume ramp-down. Set Bit 2 (active low) of the core control register to 1. This zeroes the SigmaDSP accumulators, the data output registers, and the data input registers. Fill the program RAM using burst mode writes. Fill the parameter RAM using burst mode writes. Deassert Bit 2 to Bit 4 of the core control register. DAC0 SDATA_OUT0 SDATA_IN0 DAC1 ADC0 DAC2 ADC1 DAC3 06752-013 This section details the procedure for properly setting up the ADAU1401. The following five-step sequence provides an overview of how to initialize the IC: Figure 13. Default Program Signal Flow POWER-REDUCTION MODES Sections of the ADAU1401 chip can be turned on and off as needed to reduce power consumption. These include the ADCs, DACs, and voltage reference. The individual analog sections can be turned off by writing to the auxiliary ADC and power control register. By default, the ADCs, DACs, and reference are enabled (all bits set to 0). Each of these can be turned off by writing a 1 to the appropriate bits in this register. The ADC power-down mode powers down both Rev. 0 | Page 16 of 52 ADAU1401 USING THE OSCILLATOR The ADAU1401 can use an on-board oscillator to generate its master clock. The oscillator is designed to work with a 256 × fS master clock, which is 12.288 MHz for a fS of 48 kHz and 11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscillator circuit should be an AT-cut, parallel resonator operating at its fundamental frequency. Figure 14 shows the external circuit recommended for proper operation. ADAU1401 100Ω OSCO C2 MCLKI 06752-014 C1 Figure 14. Crystal Oscillator Circuit The 100 Ω damping resistor on OSCO gives the oscillator a voltage swing of approximately 2.2 V. The crystal shunt capacitance should be 7 pF. Its load capacitance should be about 18 pF, although the circuit supports values of up to 25 pF. The necessary values of the C1 and C2 load capacitors can be calculated from the crystal load capacitance as follows: CL = C1 × C2 + C stray C1 + C2 where Cstray is the stray capacitance in the circuit and is usually assumed to be approximately 2 pF to 5 pF. OSCO should not be used to directly drive the crystal signal to another IC. This signal is an analog sine wave, and it is not appropriate to use it to drive a digital input. There are two options for using the ADAU1401 to provide a master clock to other ICs in the system. The first, and less recommended, method is to use a high impedance input digital buffer on the OSCO signal. If this is done, minimize the trace length to the buffer input. The second method is to use a clock from the serial output port. Pin MP11 can be set as an output (master) clock divided down from the internal core clock. If this pin is set to serial output port (OUTPUT_BCLK) mode in the multipurpose pin configuration register (2081) and the port is set to master in the serial output control register (2078), the desired output frequency can also be set in the serial output control register with Bits OBF [1:0] (see Table 50). If the oscillator is not utilized in the design, it can be powered down to save power. This can be done if a system master clock is already available in the system. By default, the oscillator is powered on. The oscillator powers down when a 1 is written to the OPD bit of the oscillator power-down register (see Table 61). SETTING MASTER CLOCK/PLL MODE The MCLKI input of the ADAU1401 feeds a PLL, which generates the 50 MIPS SigmaDSP core clock. In normal operation, the input to MCLKI must be one of the following: 64 × fS, 256 × fS, 384 × fS, or 512 × fS, where fS is the input sampling rate. The mode is set on PLL_MODE0 and PLL_MODE1 as described in Table 13. If the ADAU1401 is set to receive double-rate signals (by reducing the number of program steps per sample by a factor of 2 using the core control register), the master clock frequency must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1401 is set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the core control register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS, or 128 × fS. On power-up, a clock signal must be present on MCLK so that the ADAU1401 can complete its initialization routine. Table 13. PLL Modes MCLKI Input 64 × fS 256 × fS 384 × fS 512 × fS PLL_MODE0 0 0 1 1 PLL_MODE1 0 1 0 1 The clock mode should not be changed without also resetting the ADAU1401. If the mode is changed during operation, a click or pop can result in the output signals. The state of the PLL_MODEx pins should be changed while RESET is held low. The PLL loop filter should be connected to the PLL_LF pin. This filter, shown in Figure 15, includes three passive components— two capacitors and a resistor. The values of these components do not need to be exact; the tolerance can be up to 10% for the resistor and up to 20% for the capacitors. The 3.3 V signal shown in Figure 15 can be connected to the AVDD supply of the chip. 3.3V 475Ω 3.3nF 56nF ADAU1401 PLL_LF 06752-015 ADCs, and each DAC can be powered down individually. The current savings is about 15 mA when the ADCs are powered down and about 4 mA for each DAC that is powered down. The voltage reference, which is supplied to both the ADCs and DACs, should only be powered down if all ADCs and DACs are powered down. The reference is powered down by setting both Bit 6 and Bit 7 of the control register. Figure 15. PLL Loop Filter Rev. 0 | Page 17 of 52 ADAU1401 The digital voltage of the ADAU1401 must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems without an available 1.8 V supply but with an available 3.3 V supply. The only external components needed in such instances are a PNP transistor, a resistor, and a few bypass capacitors. Only one pin, VDRIVE, is necessary to support the regulator. The recommended design for the voltage regulator is shown in Figure 16. The 10 μF and 100 nF capacitors shown in this configuration are recommended for bypassing, but are not necessary for operation. Each DVDD pin should have its own 100 nF bypass capacitor, but only one bulk capacitor (10 μF to 47 μF) is needed for both DVDD pins. With this configuration, 3.3 V is the main system voltage; 1.8 V is generated at the transistor’s collector, which is connected to the DVDD pins. VDRIVE is connected to the base of the PNP transistor. If the regulator is not used in the design, VDRIVE can be tied to ground. Two specifications must be considered when choosing a regulator transistor: The transistor’s current amplification factor (hFE or beta) should be at least 100, and the transistor’s collector must be able to dissipate the heat generated when regulating from 3.3 V to 1.8 V. The maximum digital current drawn from the ADAU1401 is 60 mA. The equation to determine the minimum power dissipation of the transistor is as follows: (3.3 V − 1.8 V) × 60 mA = 90 mW There are many transistors, such as the FZT953 from Zetex Semiconductors, with these specifications available in small SOT-23 or SOT-223 packages. 3.3V 10µF + 1kΩ 100nF ADAU1401 DVDD VDRIVE 06752-016 VOLTAGE REGULATOR Figure 16. Voltage Regulator Configuration Rev. 0 | Page 18 of 52 ADAU1401 AUDIO ADCs The stereo audio ADCs are current input; therefore, a voltageto-current resistor is required on the inputs. This means that the voltage level of the input signals to the system can be set to any level; only the input resistors need to be scaled to provide the proper full-scale current input. The ADC0 and ADC1 input pins, as well as ADC_RES, have an internal 2 kΩ resistor for ESD protection. The voltage seen directly on the ADC input pins is the 1.5 V common mode. The external resistor connected to ADC_RES sets the full-scale current input of the ADCs. The full range of the ADC inputs is 100 μArms with an external 18 kΩ resistor on ADC_RES (20 kΩ total, because it is in series with the internal 2 kΩ). The only reason to change the ADC_RES resistor is if a sampling rate other than 48 kHz is used. The voltage-to-current resistors connected to ADC0/ADC1 set the full-scale voltage input of the ADCs. With a full-scale current input of 100 μArms, a 2.0 Vrms signal with an external 18 kΩ resistor (in series with the 2 kΩ internal resistor) results in an input using the full range of the ADC. The matching of these resistors to the ADC_RES resistor is important to the operation of the ADCs. For these three resistors, a 1% tolerance is recommended. The values of the resistors (internal plus external) in series with the ADC0 and ADC1 pins can be calculated as follows: R Input Total = (RMS Input Voltage) × 10 kΩ × Table 14 lists the external and total resistor values for common signal input levels at a 48 kHz sampling rate. A full-scale rms input voltage of 0.9 V is shown in the table because a full-scale signal at this input level is equal to a full-scale output on the DACs. Table 14. ADC Input Resistor Values Full-Scale RMS Input Voltage (V) 0.9 1.0 2.0 ADC_RES Value (kΩ) 18 18 18 ADC0/ADC1 Resistor Value (kΩ) 7 8 18 Total ADC0/ADC1 Input Resistance (External + Internal) (kΩ) 9 10 20 Figure 17 shows a typical configuration of the ADC inputs for a 2.0 Vrms input signal for a fS of 48 kHz. The 47 μF capacitors are used to ac-couple the signals so that the inputs are biased at 1.5 V. Either the ADC0 and/or ADC1 input pins can be left unconnected if that channel of the ADC is unused. ADAU1401 47µF 48,000 f S _ NEW Rev. 0 | Page 19 of 52 18kΩ ADC0 47µF These calculations of resistor values assume a 48 kHz sample rate. The recommended input and current setting resistors scale linearly with the sample rate because the ADCs have a switched-capacitor input. The total value (2 kΩ internal plus external resistor) of the ADC_RES resistor with sample rate fS_NEW can be calculated as follows: R total = 20 kΩ × 48,000 f S _ NEW 18kΩ ADC1 18kΩ ADC_RES 06752-017 The ADAU1401 has two Σ-Δ ADCs. The signal-to-noise ratio (SNR) of the ADCs is 100 dB, and the THD + N is −83 dB. Figure 17. Audio ADC Input Configuration ADAU1401 AUDIO DACs To properly initialize the DACs, Bits DS [1:0] in the DAC setup register (Address 2087) should be set to 01. 47µF DAC_OUT The DAC outputs can be filtered with either an active or a passive reconstruction filter. A single-pole, passive, low-pass filter with a 50 kHz corner frequency, as shown in Figure 18, is sufficient to filter the DAC out-of-band noise, although an active filter may provide better audio performance. Figure 19 560Ω FILTER_OUT 5.6nF Figure 18. Passive DAC Output Filter + C8 470µF 47µF 150pF 604Ω AD8606 3.3nF FILTER_OUT Figure 19. Active DAC Output Filter Rev. 0 | Page 20 of 52 49.9kΩ 06752-019 4.75kΩ 4.75kΩ + DAC_OUT 06752-018 The DACs are in an inverting configuration. If a signal inversion from input to output is undesirable, it can be reversed either by using an inverting configuration for the output filter or by simply inverting the signal in the SigmaDSP program flow. shows a triple-pole, active, low-pass filter that provides a steeper roll-off and better stop-band attenuation than the passive filter. In this configuration, the V+ and V− pins of the AD8606 op amp are set to VDD and ground, respectively. + The ADAU1401 includes four Σ-Δ DACs. The SNR of the DAC is 104 dB, and the THD + N is −90 dB. A full-scale output on the DACs is 0.9 Vrms (2.5 V p-p). ADAU1401 CONTROL PORTS The ADAU1401 can operate in one of three control modes: • • • I2C control SPI control Self-boot (no external controller) The ADAU1401 has both a 4-wire SPI control port and a 2-wire I2C bus control port. Each can be used to set the RAMs and registers. When the SELFBOOT pin is low at power-up, the part defaults to I2C mode but can be put into SPI control mode by pulling the CLATCH/WP pin low three times. When the SELFBOOT pin is set high at power-up, the ADAU1401 loads its program, parameters, and register settings from an external EEPROM on startup. The control port is capable of full read/write operation for all addressable memory and registers. Most signal processing parameters are controlled by writing new values to the parameter RAM using the control port. Other functions, such as mute and input/output mode control, are programmed by writing to the registers. All addresses can be accessed in a single-address mode or a burst mode. The first byte (Byte 0) of a control port write contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the memory or register location within the ADAU1401. This subaddress must be two bytes because the memory locations within the ADAU1401 are directly addressable and their sizes exceed the range of single-byte addressing. All subsequent bytes (starting with Byte 3) contain the data, such as control port data, program data, or parameter data. The number of bytes per word depends on the type of data that is being written. The exact formats for specific types of writes are shown in Table 23 to Table 32. The ADAU1401 has several mechanisms for updating signal processing parameters in real time without causing pops or clicks. If large blocks of data need to be downloaded, the output of the DSP core can be halted (using the CR bit in the DSP core control register (Address 2076)), new data can be loaded, and then the device can be restarted. This is typically done during the booting sequence at startup or when loading a new program into RAM. In cases where only a few parameters need to be changed, they can be loaded without halting the program. To avoid unwanted side effects while loading parameters on the fly, the SigmaDSP provides the safeload registers. The safeload registers can be used to buffer a full set of parameters (for example, the five coefficients of a biquad) and then transfer these parameters into the active program within one audio frame. The safeload mode uses internal logic to prevent contention between the DSP core and the control port. The control port pins are multifunctional, depending on the mode in which the part is operating. Table 15 details these multiple functions. Table 15. Control Port Pins and SELFBOOT Pin Functions Pin SCL/CCLK SDA/COUT ADDR1/CDATA/WB CLATCH/WP ADDR0 I2C Mode SCL—input SDA—open-collector output ADDR1—input Unused input—tie to ground or IOVDD ADDR0—input SPI Mode CCLK—input COUT—output CDATA—input CLATCH—input ADDR0—input Rev. 0 | Page 21 of 52 Self-Boot SCL—output SDA—open-collector output WB—writeback trigger WP—EEPROM write protect, open-collector output Unused input—tie to ground or IOVDD ADAU1401 I2C PORT Addressing 2 The ADAU1401 supports a 2-wire serial (I C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAU1401 and the system I2C master controller. In I2C mode, the ADAU1401 is always a slave on the bus, meaning it cannot initiate a data transfer. Each slave device is recognized by a unique address. The address byte format is shown in Table 16. The ADAU1401 slave addresses are set with the ADDR0 and ADDR1 pins. The address resides in the first seven bits of the I2C write. The LSB of this byte sets either a read or write operation. Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Bit 5 and Bit 6 of the address are set by tying the ADDRx pins of the ADAU1401 to Logic Level 0 or Logic Level 1. The full byte addresses, including the pin settings and read/write bit, are shown in Table 17. Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically after a single-word write unless a stop condition is encountered. The registers and RAMs in the ADAU1401 range in width from one to five bytes, so the autoincrement feature knows the mapping between subaddresses and the word length of the destination register (or memory location). A data transfer is always terminated by a stop condition. Both SDA and SCL should have 2.2 kΩ pull-up resistors on the lines connected to them. The voltage on these signal lines should not be more than IOVDD (3.3 V). Table 16. ADAU1401 I2C Address Byte Format Bit 0 0 Bit 1 1 Bit 2 1 Bit 3 0 Bit 4 1 Bit 5 ADDR1 Bit 6 ADDR0 Table 17. ADAU1401 I2C Addresses ADDR1 0 0 0 0 1 1 1 1 ADDR0 0 0 1 1 0 0 1 1 Read/Write 0 1 0 1 0 1 0 1 Slave Address 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F Bit 7 R/W Initially, each device on the I2C bus is in an idle state monitoring the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream follows. All devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit) MSB first. The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means the master will write information to the peripheral, whereas a Logic 1 means the master will read information from the peripheral after writing the subaddress and repeating the start address. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. Figure 20 shows the timing of an I2C write, and Figure 21 shows an I2C read. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1401 immediately jumps to the idle condition. During a given SCL high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAU1401 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. In read mode, the ADAU1401 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no-acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. On the other hand, if the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADAU1401, and the part returns to the idle condition. Rev. 0 | Page 22 of 52 ADAU1401 SCK SDA START BY MASTER 0 0 0 0 0 0 ADR SEL R/W ACK BY ADAU1401 ACK BY ADAU1401 FRAME 1 CHIP ADDRESS BYTE FRAME 2 SUBADDRESS BYTE 1 SCK (CONTINUED) ACK BY ADAU1401 FRAME 2 SUBADDRESS BYTE 2 FRAME 3 DATA BYTE 1 ACK BY ADAU1401 STOP BY MASTER 06752-020 SDA (CONTINUED) Figure 20. I2C Write to ADAU1401 Clocking SCK ADR SEL SDA R/W ACK BY ADAU1401 ACK BY ADAU1401 START BY MASTER FRAME 1 CHIP ADDRESS BYTE FRAME 2 SUBADDRESS BYTE 1 SCK (CONTINUED) SDA (CONTINUED) ADR SEL FRAME 3 SUBADDRESS BYTE 2 ACK BY ADAU1401 REPEATED START BY MASTER R/W ACK BY ADAU1401 FRAME 4 CHIP ADDRESS BYTE SCK (CONTINUED) ACK BY MASTER FRAME 5 READ DATA BYTE 1 ACK BY MASTER FRAME 6 READ DATA BYTE 2 Figure 21. I2C Read from ADAU1401 Clocking Rev. 0 | Page 23 of 52 STOP BY MASTER 06752-021 SDA (CONTINUED) ADAU1401 I2C Read and Write Operations data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1401. Figure 22 shows the timing of a single-word write operation. Every ninth clock, the ADAU1401 issues an acknowledge by pulling SDA low. Figure 25 shows the timing of a burst mode read sequence. This figure shows an example where the target read registers are two bytes. The ADAU1401 increments its subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. Other addresses may have word lengths ranging from one to five bytes. The ADAU1401 always decodes the subaddress and sets the autoincrement circuit so that the address increments after the appropriate number of bytes. Figure 23 shows the timing of a burst mode write sequence. This figure shows an example where the target destination registers are two bytes. The ADAU1401 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length. The timing of a single-word read operation is shown in Figure 24. Note that the first R/W bit is 0, indicating a write operation. This is because the subaddress still needs to be written to set up the internal address. After the ADAU1401 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W set to 1 (read). This causes the ADAU1401 SDA to reverse and begin driving S Chip address, R/W = 0 AS Subaddress high AS Figure 22 to Figure 25 use the following abbreviations: S = start bit P = stop bit AM = acknowledge by master AS = acknowledge by slave Subaddress low AS Data Byte 1 AS Data Byte 2 … AS Data Byte N P Figure 22. Single-Word I2C Write Format S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS DataWord 1, Byte 1 AS AS DataWord 2, Byte 1 Data Byte 1 AM DataWord 1, Byte 2 AS DataWord 2, Byte 2 AS … P Data Byte N P Figure 23. Burst Mode I2C Write Format S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS S Chip address, R/W = 1 AS Data Byte 2 … AM Figure 24. Single-Word I2C Read Format S Chip address, R/W = 0 AS Subaddress high AS Subaddress low AS S Chip address, R/W = 1 Figure 25. Burst Mode I2C Read Format Rev. 0 | Page 24 of 52 AS DataWord 1, Byte 1 AM DataWord 1, Byte 2 AM … P ADAU1401 SPI PORT Table 18. ADAU1401 SPI Address Byte Format 2 By default, the ADAU1401 is in I C mode, but it can be put into SPI control mode by pulling CLATCH/WP low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and COUT signals, and is always a slave port. The CLATCH signal should go low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches CDATA during a low-to-high transition. COUT data is shifted out of the ADAU1401 on the falling edge of CCLK and should be clocked into a receiving device, such as a microcontroller, on the CCLK rising edge. The CDATA signal carries the serial input data, and the COUT signal is the serial output data. The COUT signal remains three-stated until a read operation is requested. This allows other SPI-compatible peripherals to share the same readback line. All SPI transactions have the same basic format shown in Table 19. A timing diagram is shown in Figure 4. All data should be written MSB first. The ADAU1401 cannot be taken out of SPI mode without a full reset. Bit 0 0 Bit 1 0 Bit 2 0 Bit 3 0 Bit 4 0 Bit 5 0 Bit 6 ADDR0 Subaddress The 12-bit subaddress word is decoded into a location in one of the memories or registers. This subaddress is the location of the appropriate RAM location or register. The MSBs of the subaddress are zero-padded to bring the word to a full 2-byte length. Data Bytes The number of data bytes varies according to the register or memory being accessed. During a burst mode write, an initial subaddress is written followed by a continuous sequence of data for consecutive memory/register locations. The detailed data format for continuous mode operation is shown in Table 24 and Table 26 in the Read/Write Data Formats section. A sample timing diagram for a single-write SPI operation to the parameter RAM is shown in Figure 26. A sample timing diagram of a single-read SPI operation is shown in Figure 27. The COUT pin goes from three-state to being driven at the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses and the R/W bit and subsequent bytes carry the data. Chip Address R/W The first byte of an SPI transaction includes the 7-bit chip address and a R/W bit. The chip address is set by the ADDR0 pin. This allows two ADAU1401s to share a CLATCH signal, yet still operate independently. When ADDR0 is low, the chip address is 0000000; when it is high, the address is 0000001 (see Table 18). The LSB of this first byte determines whether the SPI transaction is a read (Logic Level 1) or a write (Logic Level 0). Table 19. Generic Control Word Format Byte 0 chip_adr [6:0], R/W Byte 2 subadr [7:0] Byte 4 1 data Byte 3 data Continues to end of data. CLATCH CDATA BYTE 0 BYTE 1 BYTE 2 06752-026 CCLK BYTE 3 Figure 26. SPI Write to ADAU1401 Clocking (Single-Write Mode) CLATCH CCLK CDATA COUT BYTE 1 BYTE 0 HI-Z DATA DATA Figure 27. SPI Read from ADAU1401 Clocking (Single-Read Mode) Rev. 0 | Page 25 of 52 DATA HI-Z 06752-027 1 Byte 1 0000, subadr [11:8] Bit 7 R/W ADAU1401 SELF-BOOT EEPROM Format On power-up, the ADAU1401 can load a program and a set of parameters that have been saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this eliminates the need for a microcontroller in the system. The self-booting is accomplished by the ADAU1401 acting as a master on the I2C bus on startup, which occurs when the SELFBOOT pin is set high. The ADAU1401 cannot self-boot in SPI mode. The EEPROM data contains a sequence of messages. Each discrete message is one of the seven types defined in Table 20 and consists of a sequence of one or more bytes. The first byte identifies the message type. Bytes are written MSB first. Most messages are block write (0x01) types, which are used for writing to the ADAU1401 program RAM, parameter RAM, and control registers. The maximum necessary EEPROM size for program and parameters is 9248 bytes, or just over 8.5 kB. This does not include register settings or overhead bytes, but such factors do not add a significant number of bytes. This much memory is only needed if the program RAM (1024 × five bytes), parameter RAM (1024 × four bytes), and interface registers (8 × four bytes) are completely full. Most applications will not use the full program and parameter RAMs, so an 8 kB EEPROM should be sufficient. The body of the message following the message type should start with a 0x00 byte; this is the chip address. As with all other control port transactions, following the chip address is a 2-byte register/memory address field. A self-boot operation is triggered on the rising edge of RESET when the SELFBOOT and WP pins are set high. The ADAU1401 reads the program, parameters, and register settings from the EEPROM. After the ADAU1401 finishes self-booting, additional messages can be sent to the ADAU1401 on the I2C bus, although this typically is not necessary in a self-booting application. The I2C device address is 0x68 for a write and 0x69 for a read in this mode. The ADDRx pins have different functions when the chip is in this mode, so the settings on them can be ignored. The ADAU1401 does not self-boot if WP is set low. Holding this pin low allows the EEPROM to be programmed in-circuit. The WP pin is pulled low (it typically has a resistor pull-up) to enable writes to the EEPROM, but this in turn disables the selfboot function until the WP pin is returned high. The ADAU1401 is a master on the I2C bus during self-boot and writeback. Although it is uncommon for an application using self-boot to also have a microcontroller connected to the control lines, care should be taken that no other device tries to write to the I2C bus during self-boot or writeback. The ADAU1401 generates SCL at 8 × fS; therefore, for a fS of 48 kHz, SCL runs at 384 kHz. SCL has a duty cycle of 3/8 in accordance with the I2C specification. The ADAU1401 reads from EEPROM Chip Address 0xA1. The LSBs of the addresses of some EEPROMs are pin configurable; in most cases, these pins should be tied low to set this address. Table 21 shows an example of what should be stored in the EEPROM, starting with EEPROM Address 0. In this example, the interface registers are first set to control port write mode (Line 1), which is followed by 18 no-operation (no-op) bytes (Line 2 to Line 4) so that the interface register data appears on Page 2 of the EEPROM. Next follows the write header (Line 4) and then 32 bytes of interface register data (Line 5 to Line 8). Finally, the program RAM data, starting at ADAU1401 Address 0x04 0x00 is written (Line 9 to Line 11). In this example, the program length is 70 words, or 350 bytes, so 332 more bytes are included in the EEPROM but are not shown in Table 21. Writeback A writeback occurs when the WB pin is triggered and data is written to the EEPROM from the ADAU1401. This function is typically used to save the volume setting and other parameter settings to the EEPROM just before power is removed from the system. A rising edge on the WB pin triggers a writeback when the device is in self-boot mode, unless a message to set the WB to the falling edge sensitive (0x05) is contained in the self-boot message sequence. Only one writeback takes place unless a message to set multiple writebacks (0x04) is contained in the self-boot message sequence. The WP pin is pulled low when a writeback is triggered to allow writing to the EEPROM. The ADAU1401 is only capable of writing back the contents of the interface registers to the EEPROM. These registers are usually set by the DSP program, but can also be written to directly after setting Bit 6 of the core control register. The parameter settings that should be saved are configured in SigmaStudio. Rev. 0 | Page 26 of 52 ADAU1401 The writeback function writes data from the ADAU1401 interface registers to the second page of the self-boot EEPROM, Address 32 to Address 63. Starting at EEPROM Address 26 (so that the interface register data begins at Address 32), the EEPROM should be programmed with six bytes—the message byte (0x01), two length bytes, the chip address (0x00), and the 2-byte subaddress for the interface registers (0x08 0x00). There must be a message to the DSP core control register to enable writing to the interface registers prior to the interface register data in the EEPROM. This should be stored in EEPROM Address 0. No-op messages (0x03) can be used in between messages to ensure that these conditions are met. The ADAU1401 writes to EEPROM Chip Address 0xA0. The LSBs of the addresses of some EEPROMs are pin configurable; in most cases, these pins should be tied low to set the address to 0xA0. The maximum number of bytes that is written back from the ADAU1401 is 35 (eight 4-byte interface registers plus three bytes of EEPROM-addressing overhead). With SCL running at 384 kHz, the writeback operation takes approximately 73 μs to complete after being triggered. Ensure that sufficient power is available to the system to allow enough time for a writeback to complete, especially if the WB signal is triggered from a falling power supply voltage. Table 20. EEPROM Message Types Message ID 0x00 0x01 Message Type End Write 0x02 0x03 0x04 0x05 0x06 Delay No operation executed Set multiple writeback Set WB to falling edge sensitive End and wait for writeback Following Bytes None Two bytes indicating message length followed by appropriate number of data bytes Two bytes for delay None None None None Table 21. EEPROM Data Example 1 0x01 Write 0x00 0x05 0x00 Device addr. 2 0x03 0x03 0x03 0x03 0x03 No-op bytes 0x03 0x03 0x03 3 0x03 0x03 0x03 0x03 0x03 No-op bytes 0x03 0x03 0x03 4 0x03 0x03 No-op bytes 0x01 Write 0x00 Length 0x08 0x1C Core control register address 0x23 Length 0x00 Device addr. 0x00 0x40 Core control register data 0x08 0x00 Interface register address 5 0x00 0x00 0x00 0x00 0x00 Interface register data 0x00 0x00 0x00 6 0x00 0x00 0x00 0x00 0x00 Interface register data 0x00 0x00 0x00 7 0x00 0x00 0x00 0x00 0x00 Interface register data 0x00 0x00 0x00 8 0x00 0x00 0x00 0x00 0x00 Interface register data 0x00 0x00 0x00 9 0x01 Write 0x01 10 0x00 0x00 0x01 11 0x00 0x00 0x00 0x61 Length 0x00 Device addr. 0x04 0x00 Program RAM address 0x00 0x00 Program RAM data 0x00 0x00 Program RAM data 0x00 0xE8 0x01 0x00 0x01 0x00 Program RAM data (continues for 332 more bytes) 0x08 0x00 Rev. 0 | Page 27 of 52 ADAU1401 SIGNAL PROCESSING The ADAU1401 is designed to provide all audio signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical entry and realtime control of all signal processing functions. with a range of 1.0 (minus 1 LSB) to −1.0. Figure 28 shows the maximum signal levels at each point in the data flow in both binary and decibel levels. Many of the signal processing functions are coded using full, 56-bit, double-precision arithmetic data. The input and output word lengths of the DSP core are 24 bits. Four extra headroom bits are used in the processor to allow internal gains of up to 24 dB without clipping. Additional gains can be achieved by initially scaling down the input signal in the DSP signal flow. DATA IN NUMERIC FORMATS DSP systems commonly use a standard numeric format. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. The ADAU1401 uses the same numeric format for both the parameter and data values. The format is as follows. Numerical Format: 5.23 1.23 (0dB) SERIAL PORT 1.23 (0dB) SIGNAL PROCESSING (5.23 FORMAT) 5.23 (24dB) DIGITAL CLIPPER 5.23 (24dB) 1.23 (0dB) 06752-028 4-BIT SIGN EXTENSION Figure 28. Numeric Precision and Clipping Structure PROGRAMMING On power-up, the ADAU1401 default program passes the unprocessed input signals to the outputs (shown in Figure 13), but the outputs are muted by default (see the Power-Up Sequence section). There are 1024 instruction cycles per audio sample, resulting in about 50 MIPS available. The SigmaDSP runs in a stream-oriented manner, meaning that all 1024 instructions are executed each sample period. The ADAU1401 can also be set up to accept double- or quad-speed inputs by reducing the number of instructions per sample that are set in the core control register. The part can be easily programmed using SigmaStudio (Figure 29), a graphical tool provided by Analog Devices. No knowledge of writing line-level DSP code is required. More information about SigmaStudio can be found at www.analog.com. Linear range: −16.0 to (+16.0 − 1 LSB) Examples: 1000 0000 0000 0000 0000 0000 0000 = −16.0 1110 0000 0000 0000 0000 0000 0000 = −4.0 1111 1000 0000 0000 0000 0000 0000 = −1.0 1111 1110 0000 0000 0000 0000 0000 = −0.25 1111 1111 0011 0011 0011 0011 0011 = −0.1 1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0) 0000 0000 0000 0000 0000 0000 0000 = 0.0 0000 0000 1100 1100 1100 1100 1101 = 0.1 0000 0010 0000 0000 0000 0000 0000 = 0.25 0000 1000 0000 0000 0000 0000 0000 = 1.0 0010 0000 0000 0000 0000 0000 0000 = 4.0 0111 1111 1111 1111 1111 1111 1111 = (16.0 − 1 LSB). A digital clipper circuit is used between the output of the DSP core and the DACs or serial port outputs (see Figure 28). This clips the top four bits of the signal to produce a 24-bit output Rev. 0 | Page 28 of 52 06752-029 The serial port accepts up to 24 bits on the input and is signextended to the full 28 bits of the DSP core. This allows internal gains of up to 24 dB without internal clipping. Figure 29. SigmaStudio Screen Shot ADAU1401 RAMS AND REGISTERS Table 22. RAM Map and Read/Write Modes Memory Parameter RAM Program RAM 1 Size 1024 × 32 1024 × 40 Address Range 0 to 1023 (0x0000 to 0x03FF) 1024 to 2047 (0x0400 to 0x07FF) Read Yes Yes Write Yes Yes Write Modes Direct write 1 safeload write Direct write1 Internal registers should be cleared first to avoid clicks/pops. ADDRESS MAPS DATA RAM Table 22 shows the RAM map and Table 33 shows the ADAU1401 register map. The address space encompasses a set of registers and two RAMs: one holds signal processing parameters and one holds the program instructions. The program RAM and parameter RAM are initialized on power-up from on-board boot ROMs (see the Power-Up Sequence section). The ADAU1401 data RAM is used to store audio data words for processing. For the most part, this process is transparent to the user. The user cannot address this RAM space, which has a size of 2k words, directly from the control port. All RAMs and registers have a default value of all 0s, except for the program RAM, which is loaded with the default program (see the Initialization section). PARAMETER RAM The parameter RAM is 32 bits wide and occupies Address 0 to Address 1023. Each parameter is padded with four 0s before the MSB to extend the 28-bit word to a full 4-byte width. The parameter RAM is initialized to all 0s on power-up. The data format of the parameter RAM is twos complement, 5.23. This means that the coefficients can range from +16.0 (minus 1 LSB) to −16.0, with 1.0 represented by the binary word 0000 1000 0000 0000 0000 0000 0000 or by the hexadecimal word 0x00 0x80 0x00 0x00. The parameter RAM can be written using one of the two following methods: a direct read/write or a safeload write. Direct Read/Write The direct read/write method allows direct access to the program RAM and parameter RAM. This mode of operation is typically used when loading a new RAM using burst mode addressing. The clear registers bit in the core control register should be set to 0 using this mode to avoid any clicks or pops in the outputs. Note that this mode can be used during live program execution, but because there is no handshaking between the core and the control port, the parameter RAM is unavailable to the DSP core during control writes, resulting in clicks and pops in the audio stream. Safeload Write Up to five safeload registers can be loaded with the parameter RAM address/data. The data is then transferred to the requested address when the RAM is not busy. This method can be used for dynamic updates while live program material is playing through the ADAU1401. For example, a complete update of one biquad section can occur in one audio frame while the RAM is not busy. This method is not available for writing to the program RAM or control registers. Data RAM utilization should be considered when implementing blocks that require large amounts of data RAM space, such as delays. The SigmaDSP core processes delay times in one-sample increments; therefore, the total pool of delay available to the user equals 2048 multiplied by the sample period. For a fS of 48 kHz, the pool of available delay is a maximum of about 43 ms. In practice, this much data memory is not available to the user because every block in a design uses a few data memory locations for its processing. In most DSP programs, this does not significantly impact the total delay time. The SigmaStudio compiler manages the data RAM and indicates if the number of addresses needed in the design exceeds the maximum available. READ/WRITE DATA FORMATS The read/write formats of the control port are designed to be byte oriented. This allows easy programming of common microcontroller chips. To fit into a byte-oriented format, 0s are appended to the data fields before the MSB to extend the dataword to eight bits. For example, 28-bit words written to the parameter RAM are appended with four leading 0s to equal 32 bits (four bytes); 40-bit words written to the program RAM are not appended with 0s because they are already a full five bytes. These zero-padded data fields are appended to a 3-byte field consisting of a 7-bit chip address, a read/write bit, and an 11-bit RAM/register address. The control port knows how many data bytes to expect based on the address given in the first three bytes. The total number of bytes for a single-location write command can vary from four bytes (for a control register write) to eight bytes (for a program RAM write). Burst mode can be used to fill contiguous register or RAM locations. A burst mode write begins by writing the address and data of the first RAM or register location to be written. Rather than ending the control port transaction (by issuing a stop command in I2C mode or by bringing the CLATCH signal high in SPI mode after the data-word), as would be done in a single-address write, the next data-word can be immediately written without specifying its address. The ADAU1401 control port auto-increments the address of each write even across the boundaries of the different RAMs and registers. Table 24 and Table 26 show examples of burst mode writes. Rev. 0 | Page 29 of 52 ADAU1401 Table 23. Parameter RAM Read/Write Format (Single Address) Byte 0 chip_adr [6:0], W/R Byte 1 000000, param_adr [9:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes [4:6] param [23:0] Table 24. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 chip_adr [6:0], W/R Byte 1 000000, param_adr [9:8] Byte 2 param_adr [7:0] Byte 3 0000, param [27:24] Bytes [4:6] param [23:0] <—param_adr—> Bytes [7:10] Bytes [11:14] param_adr + 1 param_adr + 2 Bytes [8:12] Bytes [13:17] prog_adr + 1 prog_adr + 2 Table 25. Program RAM Read/Write Format (Single Address) Byte 0 chip_adr [6:0], W/R Byte 1 Byte 2 Bytes [3:7] 00000, prog_adr [10:8] prog_adr [7:0] prog [39:0] Table 26. Program RAM Block Read/Write Format (Burst Mode) Byte 0 chip_adr [6:0], W/R Byte 1 00000, prog_adr [10:8] Byte 2 prog_adr [7:0] Bytes [3:7] prog [39:0] <—prog_adr—> Table 27. Control Register Read/Write Format (Core, Serial Out 0, Serial Out 1) Byte 0 chip_adr [6:0], W/R Byte 1 0000, reg_adr [11:8] Byte 2 reg_adr [7:0] Byte 3 data [15:8] Byte 4 data [7:0] Table 28. Control Register Read/Write Format (RAM Configuration, Serial Input) Byte 0 chip_adr [6:0], W/R Byte 1 0000, reg_adr [11:8] Byte 2 reg_adr [7:0] Byte 3 data [7:0] Table 29. Data Capture Register Write Format Byte 0 chip_adr [6:0], W/R 1 2 Byte 1 0000, data_capture_adr [11:8] Byte 2 data_capture_adr [7:0] Byte 3 000, progCount [10:6] 1 Byte 4 progCount [5:0]1, regSel [1:0] 2 progCount [10:0] is the value of the program counter when the data capture occurs (the table of values is generated by the SigmaStudio compiler). regSel [1:0] selects one of four registers (see the 2074 to 2075 (0X081A to 0X081B)—Data Capture Registers section). Table 30. Data Capture (Control Port Readback) Register Read Format Byte 0 chip_adr [6:0], W/R Byte 1 0000, data_capture_adr [11:8] Byte 2 data_capture_adr [7:0] Bytes [3:5] data [23:0] Table 31. Safeload Address Register Write Format Byte 0 chip_adr [6:0], W/R Byte 1 0000, safeload_adr [11:8] Byte 2 safeload_adr [7:0] Byte 3 000000, param_adr [9:8] Byte 4 param_adr [7:0] Table 32. Safeload Data Register Write Format Byte 0 chip_adr [6:0], W/R Byte 1 0000, safeload_adr [11:8] Byte 2 safeload_adr [7:0] Byte 3 00000000 Rev. 0 | Page 30 of 52 Byte 4 0000, data [27:24] Bytes [5:7] data [23:0] ADAU1401 CONTROL REGISTER MAP Table 33. Register Map 1 MSB Reg (Dec) 0x0800 2048 0x0801 2049 4 0x0802 2050 4 0x0803 2051 4 0x0804 2052 4 0x0805 2053 4 0x0806 2054 4 0x0807 2055 4 0x0808 0x0809 0x080A 0x080B 2056 2057 2058 2059 2 2 2 2 0x080C 2060 0x080D 2061 2 5 0x080E 0x080F 0x0810 0x0811 0x0812 0x0813 0x0814 0x0815 0x0816 0x0817 0x0818 0x0819 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 D31 D15 0 IF15 D30 D14 0 IF14 D29 D13 0 IF13 D28 D12 0 IF12 D27 D11 IF27 IF11 D26 D10 IF26 IF10 D25 D9 IF25 IF09 D24 D8 IF24 IF08 Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] Interface 0 [31:16] Interface 0 [15:0] GPIO pin setting Auxiliary ADC Data 0 Auxiliary ADC Data 1 Auxiliary ADC Data 2 0 IF15 0 IF15 0 IF15 0 IF15 0 IF15 0 IF15 0 IF15 0 0 0 0 0 IF14 0 IF14 0 IF14 0 IF14 0 IF14 0 IF14 0 IF14 0 0 0 0 0 IF13 0 IF13 0 IF13 0 IF13 0 IF13 0 IF13 0 IF13 0 0 0 0 0 IF12 0 IF12 0 IF12 0 IF12 0 IF12 0 IF12 0 IF12 0 0 0 0 IF27 IF11 IF27 IF11 IF27 IF11 IF27 IF11 IF27 IF11 IF27 IF11 IF27 IF11 MP11 AA11 AA11 AA11 IF26 IF10 IF26 IF10 IF26 IF10 IF26 IF10 IF26 IF10 IF26 IF10 IF26 IF10 MP10 AA10 AA10 AA10 IF25 IF09 IF25 IF09 IF25 IF09 IF25 IF09 IF25 IF09 IF25 IF09 IF25 IF09 MP09 AA09 AA09 AA09 IF24 IF08 IF24 IF08 IF24 IF08 IF24 IF08 IF24 IF08 IF24 IF08 IF24 IF08 MP08 AA08 AA08 AA08 IF23 IF07 IF23 IF07 IF23 IF07 IF23 IF07 IF23 IF07 IF23 IF07 IF23 IF07 MP07 AA07 AA07 AA07 IF22 IF06 IF22 IF06 IF22 IF06 IF22 IF06 IF22 IF06 IF22 IF06 IF22 IF06 MP06 AA06 AA06 AA06 IF21 IF05 IF21 IF05 IF21 IF05 IF21 IF05 IF21 IF05 IF21 IF05 IF21 IF05 MP05 AA05 AA05 AA05 IF20 IF04 IF20 IF04 IF20 IF04 IF20 IF04 IF20 IF04 IF20 IF04 IF20 IF04 MP04 AA04 AA04 AA04 IF19 IF03 IF19 IF03 IF19 IF03 IF19 IF03 IF19 IF03 IF19 IF03 IF19 IF03 MP03 AA03 AA03 AA03 IF18 IF02 IF18 IF02 IF18 IF02 IF18 IF02 IF18 IF02 IF18 IF02 IF18 IF02 MP02 AA02 AA02 AA02 IF17 IF01 IF17 IF01 IF17 IF01 IF17 IF01 IF17 IF01 IF17 IF01 IF17 IF01 MP01 AA01 AA01 AA01 IF16 IF00 IF16 IF00 IF16 IF00 IF16 IF00 IF16 IF00 IF16 IF00 IF16 IF00 MP00 AA00 AA00 AA00 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Auxiliary ADC Data 3 Reserved [39:32] Reserved [31:16] Reserved [15:0] Reserved [39:32] Reserved [31:16] Reserved [15:0] Reserved [39:32] Reserved [31:16] Reserved [15:0] Safeload Data 0 [39:32] Safeload Data 0 [31:16] Safeload Data 0 [15:0] Safeload Data 1 [39:32] Safeload Data 1 [31:16] Safeload Data 1 [15:0] Safeload Data 2 [39:32] Safeload Data 2 [31:16] Safeload Data 2 [15:0] Safeload Data 3 [39:32] Safeload Data 3 [31:16] Safeload Data 3 [15:0] Safeload Data 4 [39:32] Safeload Data 4 [31:16] Safeload Data 4 [15:0] Safeload Address 0 Safeload Address 1 Safeload Address 2 Safeload Address 3 Safeload Address 4 0 0 0 0 AA11 AA10 AA09 AA08 AA07 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD39 SD27 SD26 SD25 SD24 SD23 SD11 SD10 SD09 SD08 SD07 SD39 SD27 SD26 SD25 SD24 SD23 SD11 SD10 SD09 SD08 SD07 SD39 SD27 SD26 SD25 SD24 SD23 SD11 SD10 SD09 SD08 SD07 SD39 SD27 SD26 SD25 SD24 SD23 SD11 SD10 SD09 SD08 SD07 SD39 SD27 SD26 SD25 SD24 SD23 SD11 SD10 SD09 SD08 SD07 SA11 SA10 SA09 SA08 SA07 SA11 SA10 SA09 SA08 SA07 SA11 SA10 SA09 SA08 SA07 SA11 SA10 SA09 SA08 SA07 SA11 SA10 SA09 SA08 SA07 AA06 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD38 SD22 SD06 SD38 SD22 SD06 SD38 SD22 SD06 SD38 SD22 SD06 SD38 SD22 SD06 SA06 SA06 SA06 SA06 SA06 AA05 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD37 SD21 SD05 SD37 SD21 SD05 SD37 SD21 SD05 SD37 SD21 SD05 SD37 SD21 SD05 SA05 SA05 SA05 SA05 SA05 AA04 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD36 SD20 SD04 SD36 SD20 SD04 SD36 SD20 SD04 SD36 SD20 SD04 SD36 SD20 SD04 SA04 SA04 SA04 SA04 SA04 AA03 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD35 SD19 SD03 SD35 SD19 SD03 SD35 SD19 SD03 SD35 SD19 SD03 SD35 SD19 SD03 SA03 SA03 SA03 SA03 SA03 AA02 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD34 SD18 SD02 SD34 SD18 SD02 SD34 SD18 SD02 SD34 SD18 SD02 SD34 SD18 SD02 SA02 SA02 SA02 SA02 SA02 AA01 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD33 SD17 SD01 SD33 SD17 SD01 SD33 SD17 SD01 SD33 SD17 SD01 SD33 SD17 SD01 SA01 SA01 SA01 SA01 SA01 AA00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD32 SD16 SD00 SD32 SD16 SD00 SD32 SD16 SD00 SD32 SD16 SD00 SD32 SD16 SD00 SA00 SA00 SA00 SA00 SA00 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x00 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 No. of Bytes Name 4 Interface 0 [31:16] Interface 0 [15:0] Reg (Hex) 5 5 5 5 5 5 5 2 2 2 2 2 LSB D39 D23 D7 IF23 IF07 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SD31 SD30 SD29 SD28 SD15 SD14 SD13 SD12 SD31 SD30 SD29 SD28 SD15 SD14 SD13 SD12 SD31 SD30 SD29 SD28 SD15 SD14 SD13 SD12 SD31 SD30 SD29 SD28 SD15 SD14 SD13 SD12 SD31 SD15 0 0 0 0 0 SD30 SD14 0 0 0 0 0 SD29 SD13 0 0 0 0 0 SD28 SD12 0 0 0 0 0 Rev. 0 | Page 31 of 52 D38 D22 D6 IF22 IF06 D37 D21 D5 IF21 IF05 D36 D20 D4 IF20 IF04 D35 D19 D3 IF19 IF03 D34 D18 D2 IF18 IF02 D33 D17 D1 IF17 IF01 D32 D16 D0 IF16 IF00 Default 0x0000 0x0000 ADAU1401 MSB Reg (Hex) Reg (Dec) 0x081A 0x081B 0x081C 0x081D 0x081E 0x081F 0x0820 2074 2075 2076 2077 2078 2079 2080 0x0821 2081 0x0822 2082 0x0823 0x0824 0x0825 0x0826 0x0827 2083 2084 2085 2086 2087 1 No. of Bytes Name 2 Data Capture 0 2 Data Capture 1 2 DSP core control 1 Reserved 2 Serial output control 1 Serial input control 3 MP Pin Config. 0 [23:16] MP Pin Config. 0 [15:0] 3 MP Pin Config. 1 [23:16] MP Pin Config. 1 [15:0] 2 Auxiliary ADC and Power Control 2 Reserved 2 Auxiliary ADC Enable 2 Reserved 2 Oscillator Power-Down 2 DAC Setup D31 D15 0 0 RSVD D30 D14 0 0 RSVD D29 D13 0 0 GD1 D28 D12 0 0 GD0 D27 D11 PC09 PC09 RSVD D26 D10 PC08 PC08 RSVD D25 D9 PC07 PC07 RSVD D24 D8 PC06 PC06 AACW RSVD AAEN RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD D39 D23 D7 PC05 PC05 GPCW RSVD OLF0 0 MP53 MP13 D38 D22 D6 PC04 PC04 IFCW RSVD FST 0 MP52 MP12 D37 D21 D5 PC03 PC03 IST RSVD TDM 0 MP51 MP11 D36 D20 D4 PC02 PC02 ADM RSVD MSB2 ILP MP50 MP10 D35 D19 D3 PC01 PC01 DAM RSVD MSB1 IBP MP43 MP03 D34 D18 D2 PC00 PC00 CR RSVD MSB0 M2 MP42 MP02 D33 D17 D1 RS01 RS01 SR1 RSVD OWL1 M1 MP41 MP01 LSB D32 D16 D0 RS00 RS00 SR0 RSVD OWL0 M0 MP40 MP00 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPD RSVD RSVD RSVD RSVD RSVD DS1 RSVD RSVD RSVD RSVD DS0 Default 0x0000 0x0000 0x0000 0x00 0 0 OLRP OBP M/S OBF1 OBF0 OLF1 0x0000 0x00 0x00 MP33 MP32 MP31 MP30 MP23 MP22 MP21 MP20 0x0000 MP113 MP112 MP111 MP110 MP103 MP102 MP101 MP100 0x00 MP93 MP92 MP91 MP90 MP83 MP82 MP81 MP80 MP73 MP72 MP71 MP70 MP63 MP62 MP61 MP60 0x0000 RSVD RSVD RSVD RSVD RSVD RSVD FIL1 FIL0 AAPD VBPD VRPD RSVD D0PD D1PD D2PD D3PD 0x0000 Shading indicates that registers do not fill these locations, so control bits do not exist in these locations. Rev. 0 | Page 32 of 52 0x0000 0x0000 0x0000 0x0000 0x0000 ADAU1401 CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS The interface registers are used in self-boot mode to save parameters that need to be written to the external EEPROM. The ADAU1401 then recalls these parameters from the EEPROM after the next reset or power-up. Therefore, system parameters such as volume and EQ settings can be saved during power-down and recalled the next time the system is turned on. There are eight 32-bit interface registers, which allow eight 28-bit (plus zero-padding) parameters to be saved. The parameters to be saved in these registers are selected in the graphical programming tools. These registers are updated with their corresponding parameter RAM data once per sample period. An edge, which can be set to be either rising or falling, triggers the ADAU1401 to write the current contents of the interface registers to the EEPROM. See the Self-Boot section for details. The user can write directly to the interface registers after the interface registers control port write mode (IFCW) in the DSP core control register has been set. In this mode, the data in the registers is written from the control port, not from the DSP core. Table 34. D31 D15 0 IF15 D30 D14 0 IF14 D29 D13 0 IF13 D28 D12 0 IF12 D27 D11 IF27 IF11 D26 D10 IF26 IF10 D25 D9 IF25 IF09 D24 D8 IF24 IF08 D23 D7 IF23 IF07 D22 D6 IF22 IF06 Table 35. Bit Name IF [27:0] Description Interface register 28-bit parameter Rev. 0 | Page 33 of 52 D21 D5 IF21 IF05 D20 D4 IF20 IF04 D19 D3 IF19 IF03 D18 D2 IF18 IF02 D17 D1 IF17 IF01 D16 D0 IF16 IF00 Default 0x0000 0x0000 ADAU1401 2056 (0x808)—GPIO PIN SETTING REGISTER This register allows the user to set the GPIO pins through the control port. High or low settings can be directly written to or read from this register after setting the GPIO pin setting register control port write mode (GPCW) in the core control register. This register is updated once every LRCLK frame (1/fS). Table 36. D15 0 D14 0 D13 0 D12 0 D11 MP11 D10 MP10 D9 MP09 D8 MP08 D7 MP07 D6 MP06 D5 MP05 D4 MP04 D3 MP03 Table 37. Bit Name MP [11:0] Description Setting of multipurpose pin when controlled through SPI or I2C Rev. 0 | Page 34 of 52 D2 MP02 D1 MP01 D0 MP00 Default 0x0000 ADAU1401 2057 TO 2060 (0x809 TO 0x80C)—AUXILIARY ADC DATA REGISTERS These registers hold the data generated by the 4-channel auxiliary ADC. The ADCs have eight bits of precision and can be extended to 12 bits if filtering is selected via Bits FIL [1:0] of the auxiliary ADC and power control register. The SigmaDSP program reads this data as a 1.11 format data-word with a range of 0 to 1.0. This data-word is mapped to the 5.23 format parameter word with the four MSBs and 12 LSBs set to 0. A full-scale code of 255 results in a value of 1.0. These registers can be written to directly if the auxiliary ADC data registers control port write mode (AACW) bit is set in the DSP core control register. Table 38. D15 0 D14 0 D13 0 D12 0 D11 AA11 D10 AA10 D9 AA09 D8 AA08 D7 AA07 D6 AA06 Table 39. Bit Name AA [11:0] Description Auxiliary ADC output data, MSB first Rev. 0 | Page 35 of 52 D5 AA05 D4 AA04 D3 AA03 D2 AA02 D1 AA01 D0 AA00 Default 0x0000 ADAU1401 2064 TO 2068 (0x0810 TO 0x814)—SAFELOAD DATA REGISTERS Many applications require real-time microcontroller control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. When controlling a biquad filter, for example, all of the parameters must be updated at the same time. Doing so prevents the filter from executing with a mix of old and new coefficients for one or two audio frames, thus avoiding temporary instability and transients that may take a long time to decay. To accomplish this, the ADAU1401 uses safeload data registers to simultaneously load a set of five 28-bit values to the desired parameter RAM address. Five registers are used because a biquad filter uses five coefficients and, as previously mentioned, it is desirable to do a complete update in one transaction. loading into RAM. Each of the five safeload registers takes one of the 1024 core instructions to load into the parameter RAM. The total program lengths should, therefore, be limited to 1019 cycles (1024 minus 5) to ensure that the SigmaDSP core always has at least five cycles available. The safeload is guaranteed to occur within one LRCLK period (21 μs for a fS of 48 kHz) of the initiate safeload transfer bit being set. The safeload logic automatically sends data to be loaded into RAM from only those safeload registers that have been written to since the last safeload operation. For example, if two parameters are to be updated in the RAM, only two of the five safeload registers must be written. When the initiate safeload transfer bit is asserted, only data from those two registers are sent to the RAM; the other three registers are not sent to the RAM and may hold old or invalid data. The first step in performing a safeload operation is writing the parameter address to one of the safeload address registers (2069 to 2073). The 10-bit data-word to be written is the address in parameter RAM to which the safeload is being performed. After this address is written, the 28-bit data-word can be written to the corresponding safeload data register (2064 to 2068). Table 40. Safeload Address and Data Register Mapping Safeload Register 0 1 2 3 4 The data formats for these writes are detailed in Table 31 and Table 32. Table 40 shows how each of the five address registers maps to its corresponding data register. Safeload Address Register 2069 2070 2071 2072 2073 Safeload Data Register 2064 2065 2066 2067 2068 After the address and data registers are loaded, set the initiate safeload transfer bit in the core control register to initiate the Table 41. D31 D15 D30 D14 D29 D13 D28 D12 D27 D11 D26 D10 D25 D9 D24 D8 SD31 SD15 SD30 SD14 SD29 SD13 SD28 SD12 SD27 SD11 SD26 SD10 SD25 SD09 SD24 SD08 D39 D23 D7 SD39 SD23 SD07 D38 D22 D6 SD38 SD22 SD06 D37 D21 D5 SD37 SD21 SD05 D36 D20 D4 SD36 SD20 SD04 D35 D19 D3 SD35 SD19 SD03 D34 D18 D2 SD34 SD18 SD02 D33 D17 D1 SD33 SD17 SD01 D32 D16 D0 SD32 SD16 SD00 Default 0x00 0x0000 0x0000 Table 42. Bit Name SD [39:0] Safeload Data Description Data (program, parameters, register contents) to be loaded into the RAMs or registers 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS Table 43. D15 0 D14 0 D13 0 D12 0 D11 SA11 D10 SA10 D9 SA09 D8 SA08 D7 SA07 D6 SA06 D5 SA05 D4 SA04 D3 SA03 Table 44. Bit Name SA [11:0] Safeload Address Description Address of data that is to be loaded into the RAMs or registers Rev. 0 | Page 36 of 52 D2 SA02 D1 SA01 D0 SA00 Default 0x0000 ADAU1401 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS The ADAU1401 data capture feature allows the data at any node in the signal processing flow to be sent to one of two readable registers. This feature is useful for monitoring and displaying information about internal signal levels or compressor/limiter activity. The captured data is in 5.19, twos complement data format, which comes from the internal 5.23 data-word with the four LSBs truncated. The data that must be written to set up the data capture is a concatenation of the 10-bit program count index with the 2-bit register select field. The capture count and register select values that correspond to the desired point to be monitored in the signal processing flow can be found in a file output from the program compiler. The capture registers can be accessed by reading from Location 2074 and Location 2075. The format for writing and reading to the data capture registers is shown in Table 29 and Table 30. For each of the data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 1023 that corresponds to the program step number where the capture is to occur. The register select field programs one of four registers in the DSP core that transfers this information to the data capture register when the program counter reaches this step. Table 45. D15 0 D14 0 D13 0 D12 0 D11 PC09 D10 PC08 D9 PC07 D8 PC06 D7 PC05 D6 PC04 D5 PC03 Table 46. Bit Name PC [9:0] RS [1:0] Description 10-bit program counter address Select the register to be transferred to the data capture output RS [1:0] Register 00 Multiplier X input (Mult_X_input) 01 Multiplier Y input (Mult_Y_input) 10 Multiplier-accumulator output (MAC_out) 11 Accumulator feedback (Accum_fback) Rev. 0 | Page 37 of 52 D4 PC02 D3 PC01 D2 PC00 D1 RS01 D0 RS00 Default 0x0000 ADAU1401 2076 (0x081C)—DSP CORE CONTROL REGISTER Table 47. D15 RSVD D14 RSVD D13 GD1 D12 GD0 D11 RSVD D10 RSVD D9 RSVD D8 AACW D7 GPCW D6 IFCW D5 IST D4 ADM D3 DAM D2 CR D1 SR1 D0 SR0 Default 0x0000 Table 48. DSP Core Control Register Bit Name GD [1:0] GPIO Debounce Control AACW Auxiliary ADC Data Registers Control Port Write Mode GPCW GPIO Pin Setting Register Control Port Write Mode IFCW Interface Registers Control Port Write Mode IST Initiate Safeload Transfer ADM Mute ADCs DAM Mute DACs CR Clear Internal Registers to 0 SR [1:0] Sample Rate Description Sets debounce time of multipurpose pins that are set as GPIO inputs. GD [1:0] Time (ms) 00 20 01 40 10 10 11 5 Setting this bit allows data to be written directly to the auxiliary ADC data registers (2057 to 2060) from the control port. When this bit is set, the auxiliary ADC data registers ignore the settings on the multipurpose pins. When this bit is set, the GPIO pin setting register (2056) can be written to directly from the control port and this register ignores the input settings on the multipurpose pins. When this bit is set, data can be written directly to the interface registers (2048 to 2055) from the control port. In that state, the interface registers are not written from the SigmaDSP program. Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is automatically cleared when the operation is complete. There are five safeload register pairs (address/data); only those registers that have been written since the last safeload event are transferred to the parameter RAM. This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to transmit audio signals from the ADCs. This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to transmit audio signals from the DACs. This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass through the SigmaDSP core. These bits set the number of DSP instructions for every sample and the sample rate at which the ADAU1401 operates. At the default setting of 1×, there are 1024 instructions per audio sample. This setting should be used with sample rates such as 48 kHz and 44.1 kHz. At the 2× setting, the number of instructions per frame is halved to 512 and the ADCs and DACs nominally run at a 96 kHz sample rate. At the 4× setting, there are 256 instructions per cycle and the converters run at a 192 kHz sample rate. SR [1:0] Setting 00 1× (1024 instructions) 01 2× (512 instructions) 10 4× (256 instructions) 11 Reserved Rev. 0 | Page 38 of 52 ADAU1401 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER Table 49. D15 0 D14 0 D13 OLRP D12 OBP D11 M/S D10 OBF1 D9 OBF0 D8 OLF1 D7 OLF0 D6 FST D5 TDM D4 MSB2 D3 MSB1 D2 MSB0 D1 OWL1 D0 OWL0 Default 0x0000 Table 50. Bit Name OLRP OUTPUT_LRCLK Polarity OBP OUTPUT_BCLK Polarity M/S Master/Slave OBF [1:0] OUTPUT_BCLK Frequency (Master Mode Only) OLF [1:0] OUTPUT_LRCLK Frequency (Master Mode Only) FST Frame Sync Type TDM TDM Enable MSB [2:0] MSB Position OWL [1:0] Output Word Length Description When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is low and the right-channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-channel data is clocked when OUTPUT_LRCLK is low and the left-channel data is clocked when OUTPUT_LRCLK is high. This bit controls on which edge of the bit clock the output data is clocked. Data changes on the falling edge of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is set to 1. This bit sets whether the output port is a clock master or slave. The default setting is slave; on power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time they become clock outputs. When the output port is being used as a clock master, these bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock (49.152 MHz for a fS of 48 kHz). OBF [1:0] Setting 00 Internal clock/16 01 Internal clock/8 10 Internal clock/4 11 Internal clock/2 When the output port is used as a clock master, these bits set the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal 1024 × fS clock (49.152 MHz for a fS of 48 kHz). OLF [1:0] Setting 00 Internal clock/1024 01 Internal clock/512 10 Internal clock/256 11 Reserved This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of one bit clock at the beginning of the data frame. Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-channel TDM output stream on the SDATA_OUT0 pin (MP6). These three bits set the position of the MSB of data with respect to the LRCLK edge. The data output of the ADAU1401 is always MSB first. MSB [2:0] Setting 000 Delay by 1 001 Delay by 0 010 Delay by 8 011 Delay by 12 100 Delay by 16 101 Reserved 111 Reserved These bits set the word length of the output data-word. All bits following the LSB are set to 0. OWL [1:0] Setting 00 24 bits 01 20 bits 10 16 bits 11 Reserved Rev. 0 | Page 39 of 52 ADAU1401 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER Table 51. D7 0 D6 0 D5 0 D4 ILP D3 IBP D2 M2 D1 M1 D0 M0 Default 0x00 Table 52. Bit Name ILP INPUT_LRCLK Polarity IBP INPUT_BCLK Polarity M [2:0] Serial Input Mode Description When this bit is set to 0, the left-channel data on the SDATA_INx pins is clocked when INPUT_LRCLK is low and the right-channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1, the clocking of these channels is reversed. In TDM mode when this bit is set to 0, data is clocked in, starting with the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock. In this case, the first edge of the pulse is used by the ADAU1401 to start the data frame. When this polarity bit is set to 0, a low pulse should be used; when the bit it set to 1, a high pulse should be used. This bit controls on which edge of the bit clock the input data changes and on which edge it is clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is set at 1. These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4 of this control register override the settings of Bits [2:0]; therefore, all four bits must be changed together for proper operation in some modes. The clock diagrams for these modes are shown in Figure 31, Figure 32, and Figure 33. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is the opposite of the default setting for ILP. When these bits are set to accept a TDM input, the ADAU1401 data starts after the edge defined by ILP. The ADAU1401 TDM data stream should be input on Pin SDATA_IN0. Figure 34 shows a TDM stream with a high-tolow triggered LRCLK and data changing on the falling edge of the BCLK. The ADAU1401 expects the MSB of each data slot to be delayed by one BCLK from the beginning of the slot, as it would in stereo I2S format. In TDM mode, Channel 0 to Channel 3 are in the first half of the frame, and Channel 4 to Channel 7 are in the second half. Figure 35 shows an example of a TDM stream running with a pulse word clock, which is used to interface to ADI codecs in auxiliary mode. To work in this mode with either the input or output serial ports, set the ADAU1401 to begin the frame on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to delay the MSB position from the start of the word clock by one BCLK. M [2:0] Setting 000 I2S 001 Left-justified 010 TDM 011 Right-justified, 24 bits 100 Right-justified, 20 bits 101 Right-justified, 18 bits 110 Right- justified, 16 bits 111 Reserved Rev. 0 | Page 40 of 52 ADAU1401 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS each pin’s 4-bit configuration inverts the input to or output from the pin. The internal pull-up resistor (approximately 10 kΩ) of each MP pin is enabled when it is set as a digital input (either a GPIO input or a serial data port input). Each multipurpose pin can be set to different functions from these registers (2080 to 2081). The two 3-byte registers are broken up into 12 4-bit (nibble) sections that each control a different MP pin. Table 55 lists the function of each nibble setting within the MP pin configuration registers. The MSB of Table 53. Register 2080 D15 D14 D13 D12 D11 D10 D9 D8 MP33 MP32 MP31 MP30 MP23 MP22 MP21 MP20 D23 D7 MP53 MP13 D22 D6 MP52 MP12 D21 D5 MP51 MP11 D20 D4 MP50 MP10 D19 D3 MP43 MP03 D18 D2 MP42 MP02 D17 D1 MP41 MP01 D16 D0 MP40 MP00 D19 D3 MP103 MP63 D18 D2 MP102 MP62 D17 D1 MP101 MP61 D16 D0 MP100 MP60 Default 0x00 0x0000 Table 54. Register 2081 D15 D14 D13 D12 D11 D10 D9 D8 MP93 MP92 MP91 MP90 MP83 MP82 MP81 MP80 D23 D7 MP113 MP73 D22 D6 MP112 MP72 D21 D5 MP111 MP71 Table 55. Bit Name MPx [3:0] Description Set the function of each multipurpose pin MPx [3:0] Setting 1111 Auxiliary ADC input (see Table 64) 1110 Reserved 1101 Reserved 1100 Serial data port—inverted (see Table 66) 1011 Open-collector output—inverted 1010 GPIO output—inverted 1001 GPIO input, no debounce—inverted 1000 GPIO input, debounced—inverted 0111 N/A 0110 Reserved 0101 Reserved 0100 Serial data port (see Table 66) 0011 Open-collector output 0010 GPIO output 0001 GPIO input, no debounce 0000 GPIO input, debounced Rev. 0 | Page 41 of 52 D20 D4 MP110 MP70 Default 0x00 0x0000 ADAU1401 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL Table 56. D15 RSVD D14 RSVD D13 RSVD D12 RSVD D11 RSVD D10 RSVD D9 FIL1 D8 FIL0 D7 AAPD D6 VBPD D5 VRPD D4 RSVD D3 D0PD D2 D1PD D1 D2PD D0 D3PD Default 0x0000 Table 57. Bit Name FIL [1:0] AAPD VBPD VRPD D0PD D1PD D2PD D3PD Description Auxiliary ADC filtering FIL [1:0] Setting 00 4-bit hysteresis (12-bit level) 01 5-bit hysteresis (12-bit level) 10 Filter and hysteresis bypassed 11 Low-pass filter bypassed ADC power-down (both ADCs) Voltage reference buffer power-down Voltage reference power-down DAC0 power-down DAC1 power-down DAC2 power-down DAC3 power-down 2084 (0x0824)—AUXILIARY ADC ENABLE Table 58. D15 AAEN D14 RSVD D13 RSVD D12 RSVD D11 RSVD D10 RSVD D9 RSVD D8 RSVD D7 RSVD D6 RSVD D5 RSVD D4 RSVD D3 RSVD D2 RSVD D8 RSVD D7 RSVD D6 RSVD D5 RSVD D4 RSVD D3 RSVD D2 OPD D1 RSVD D0 RSVD Default 0x0000 Table 59. Bit Name AAEN Description Enable the auxiliary ADC 2086 (0x0826)—OSCILLATOR POWER-DOWN Table 60. D15 RSVD D14 RSVD D13 RSVD D12 RSVD D11 RSVD D10 RSVD D9 RSVD Table 61. Bit Name OPD Description Power down the oscillator Rev. 0 | Page 42 of 52 D1 RSVD D0 RSVD Default 0x0000 ADAU1401 2087 (0x0827)—DAC SETUP To properly initialize the DACs, Bits DS [1:0] in this register should be set to 01. Table 62. D15 RSVD D14 RSVD D13 RSVD D12 RSVD D11 RSVD D10 RSVD D9 RSVD D8 RSVD D7 RSVD D6 RSVD Table 63. Bit Name DS [1:0] Description DAC setup DS [1:0] 00 01 10 11 Setting Reserved Initialize DACs Reserved Reserved Rev. 0 | Page 43 of 52 D5 RSVD D4 RSVD D3 RSVD D2 RSVD D1 DS1 D0 DS0 Default 0x0000 ADAU1401 MULTIPURPOSE PINS The ADAU1401 has 12 multipurpose (MP) pins that can be individually programmed to be used as serial data inputs, serial data outputs, digital control inputs/outputs to and from the SigmaDSP core, or inputs to the 4-channel auxiliary ADC. These pins allow the ADAU1401 to be used with external ADCs and DACs. They also use analog or digital inputs to control settings such as volume control, or use output digital signals to drive LED indicators. AUXILIARY ADC The ADAU1401 has a 4-channel, auxiliary, 8-bit ADC that can be used in conjunction with a potentiometer to control volume, tone, or other parameter settings in the DSP program. Each of the four channels is sampled at the audio sampling frequency (fS). Full-scale input on this ADC is 3.0 V, so the step size is approximately 11 mV (3.0 V/256 steps). The input resistance of the ADC is approximately 30 kΩ. Table 64 indicates which four MP pins are mapped to the four channels of the auxiliary ADC. The auxiliary ADC is enabled for those pins by writing 1111 to the appropriate portion of the multipurpose pin configuration registers. The auxiliary ADC is turned on by setting the AAEN bit of the auxiliary ADC enable register (see Table 59). Noise on the ADC input can cause the digital output to constantly change by a few LSBs. If the auxiliary ADC is used to control volume, this constant change causes small gain fluctuations. To avoid this, add a low-pass filter or hysteresis to the auxiliary ADC signal path by enabling either function in the auxiliary ADC and power control register (2082), as described in Table 57. The filter is enabled by default when the auxiliary ADC is enabled. When data is read from the auxiliary ADC registers, two bytes (12 bits of data, plus zero-padded LSBs) are available because of this filtering. AUX ADC INPUT PIN 20kΩ S2 1.8pF Multipurpose Pin MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9 MP10 MP11 Function N/A N/A ADC1 ADC2 N/A N/A N/A N/A ADC3 ADC0 N/A N/A GENERAL-PURPOSE INPUT/OUTPUT PINS The general-purpose input/output (GPIO) pins can be used as either inputs or outputs. These pins are readable and can be set either through the control interface or directly by the SigmaDSP core. When set as inputs, these pins can be used with push-button switches or rotary encoders to control DSP program settings. Digital outputs can be used to drive LEDs or external logic to indicate the status of internal signals and control other devices. Examples of this use include indicating signal overload, signal present, and button press confirmation. When set as an output, each pin can typically drive 2 mA. This is enough current to directly drive some high efficiency LEDs. Standard LEDs require about 20 mA of current and can be driven from a GPIO output with an external transistor or buffer. Because of issues that could arise from simultaneously driving or sinking a large current on many pins, care should be taken in the application design to avoid connecting high efficiency LEDs directly to many or all of the MPx pins. If many LEDs are required, use an external driver. When the GPIO pins are set as open-collector outputs, they should be pulled up to a maximum voltage of 3.3 V (the voltage on IOVDD). 06752-030 S1 10kΩ Table 64. Multipurpose Pin Auxiliary ADC Mapping SERIAL DATA INPUT/OUTPUT PORTS Figure 30. Auxiliary ADC Input Circuit Figure 30 shows the input circuit for the auxiliary ADC. Switch S1 enables the auxiliary ADC and is set by Bit 15 of the auxiliary ADC enable register. The sampling switch, S2, operates at the audio sampling frequency. The auxiliary ADC data registers can be written to directly after AACW in the DSP core control register has been set. In this mode, the voltages on the analog inputs are not written into the registers, but rather the data in the registers is written from the control port. PVDD supplies the 3.3 V power for the auxiliary ADC analog input. The digital core of the auxiliary ADC is powered with the 1.8 V DVDD signal. The flexible serial data input and output ports of the ADAU1401 can be set to accept or transmit data in 2-channel format or in an 8-channel TDM stream. Data is processed in twos complement, MSB-first format. The left-channel data field always precedes the right-channel data field in the 2-channel streams. In TDM mode, Slot 0 to Slot 3 are in the first half of the audio frame, and Slot 4 to Slot 7 are in the second half of the frame. TDM mode allows fewer multipurpose pins to be used, freeing more pins for other functions. The serial modes are set in the serial output and serial input control registers. The serial data clocks need to be synchronous with the ADAU1401 master clock input. Rev. 0 | Page 44 of 52 ADAU1401 The input control register allows control of clock polarity and data input modes. The valid data formats are I2S, left-justified, right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all modes except for the right-justified modes, the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but they are truncated internally. Proper operation of the right-justified modes requires that there be exactly 64 BCLKs per audio frame. The TDM data is input on SDATA_IN0. The LRCLK in TDM mode can be input to the ADAU1401 either as a 50/50 duty cycle clock or as a bit-wide pulse. In TDM mode, the ADAU1401 can be a master for 48 kHz and 96 kHz data, but not for 192 kHz data. Table 65 lists the modes in which the serial output port can function. Table 65. Serial Output Port Master/Slave Mode Capabilities fS 48 kHz 96 kHz 192 kHz 2-Channel Modes (I2S, Left-Justified, Right-Justified) Master and slave Master and slave Master and slave the configuration of the corresponding output port is controlled with the serial output control register (Table 50). The clocks of the input port function only as slaves, whereas the output port clocks can be set to function as either masters or slaves. The INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are used to clock the SDATA_INx (MP0 to MP3) signals, and the OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins are used to clock the SDATA_OUTx (MP6 to MP9) signals. If an external ADC is connected as a slave to the ADAU1401, use both the input and output port clocks. The OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins must be set to master mode and connected externally to the INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins as well as to the external ADC clock input pins. The data is output from the external ADC into the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3). Connections to an external DAC are handled exclusively with the output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK pins can be set to function as either masters or slaves, and the SDATA_OUTx pins are used to output data from the SigmaDSP to the external DAC. 8-Channel TDM Master and slave Master and slave Slave only The output control registers allow the user to control clock polarities, clock frequencies, clock types, and data format. In all modes except for the right-justified modes (MSB delayed by 8, 12, or 16 bits), the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but are truncated internally. Proper operation of the right-justified modes requires the LSB to align with the edge of the LRCLK. The default settings of all serial port control registers correspond to 2-channel I2S mode. All register settings apply to both master and slave modes unless otherwise noted. The function of each multipurpose pin in serial data port mode is shown in Table 66. Pin MP0 to Pin MP5 support digital data input to the ADAU1401, and Pin MP6 to Pin MP11 handle digital data output from the DSP. The configuration of the serial data input port is set in the serial input control register (Table 52), and Table 67 describes the proper configurations for standard audio data formats. Table 66. Multipurpose Pin Serial Data Port Functions Multipurpose Pin MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9 MP10 MP11 Function SDATA_IN0/TDM_IN SDATA_IN1 SDATA_IN2 SDATA_IN3 INPUT_LRCLK (slave only) INPUT_BCLK (slave only) SDATA_OUT0/TDM_OUT SDATA_OUT1 SDATA_OUT2 SDATA_OUT3 OUTPUT_LRCLK (master or slave) OUTPUT_BCLK (master or slave) Table 67. Data Format Configurations Format I2S (Figure 31) LRCLK Polarity Frame begins on falling edge LRCLK Type Clock BCLK Polarity Data changes on falling edge Left-Justified (Figure 32) Right-Justified (Figure 33) Frame begins on rising edge Frame begins on rising edge Clock Clock Data changes on falling edge Data changes on falling edge TDM with Clock (Figure 34) Frame begins on falling edge Clock Data changes on falling edge TDM with Pulse (Figure 35) Frame begins on rising edge Pulse Data changes on falling edge Rev. 0 | Page 45 of 52 MSB Position Delayed from LRCLK edge by 1 BCLK Aligned with LRCLK edge Delayed from LRCLK edge by 8, 12, or 16 BCLKs Delayed from start of word clock by 1 BCLK Delayed from start of word clock by 1 BCLK ADAU1401 LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB LSB MSB 06752-031 SDATA 1/FS 2 Figure 31. I S Mode—16 Bits to 24 Bits per Channel MSB LSB MSB LSB 06752-032 SDATA RIGHT CHANNEL LEFT CHANNEL LRCLK BCLK 1/FS Figure 32. Left-Justified Mode—16 Bits to 24 Bits per Channel RIGHT CHANNEL SDATA MSB LSB MSB LSB 06752-033 LEFT CHANNEL LRCLK BCLK 1/FS Figure 33. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK 256 BCLKs BCLK DATA 32 BCLKs SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LRCLK MSB–1 MSB–2 06752-034 BCLK MSB DATA Figure 34. TDM Mode LRCLK BCLK MSB TDM MSB TDM CH 0 8TH CH SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 06752-035 SDATA 32 BCLKs Figure 35. TDM Mode with Pulse Word Clock Rev. 0 | Page 46 of 52 ADAU1401 LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage-to-current resistors and the ADC current set resistor should be placed as close as possible to the 2, 3, and 4 input pins. All 100 nF bypass capacitors, which are recommended for every analog, digital, and PLL power/ground pair, should be placed as close as possible to the ADAU1401. The 3.3 V and 1.8 V signals on the board should also each be bypassed with a single bulk capacitor (10 μF to 47 μF). All traces in the crystal oscillator circuit (Figure 14) should be kept as short as possible to minimize stray capacitance. In addition, avoid long board traces connected to any of these components because such traces may affect crystal startup and operation. GROUNDING A single ground plane should be used in the application layout. Components in an analog signal path should be placed away from digital signals. Rev. 0 | Page 47 of 52 ADAU1401 TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE 06752-036 U1 ADAU1401 Figure 36. Self-Boot Mode Schematic Rev. 0 | Page 48 of 52 ADAU1401 I2C CONTROL 06752-037 U1 ADAU1401 Figure 37. I2C Control Schematic Rev. 0 | Page 49 of 52 ADAU1401 SPI CONTROL 06752-038 U1 ADAU1401 Figure 38. SPI Control Schematic Rev. 0 | Page 50 of 52 ADAU1401 OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE VIEW A (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 24 0.27 0.22 0.17 051706-A 0.75 0.60 0.45 Figure 39. 48-Lead Low-Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model ADAU1401YSTZ 1 ADAU1401YSTZ-RL1 EVAL-ADAU1401EB 1 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 48-Lead LQFP 48-Lead LQFP in 13” Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 51 of 52 Package Option ST-48 ST-48 ADAU1401 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06752-0-7/07(0) Rev. 0 | Page 52 of 52