ETC PI6C184-02S

PI6C184-02
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Precision 1-13 Clock Buffer
Features
Description
• High speed, low noise non-inverting 1-13 buffer
The PI6C184-02 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
• Supports up to four SDRAM DIMMs
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
• Low skew (<250ps) between any two output clocks
2
• I C Serial Configuration interface
• 3.3V power supply voltage
At power up all SDRAM output are enabled and active. The
I2C Serial control may be used to individually activate/deactivate
any of the 13 output drivers.
• 28-pin SSOP and SOIC packages (H, S)
Note:
• Multiple VDD, VSS pins for noise reduction
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
Block Diagram
Pin Configuration
SDRAM0
VDD
SDRAM0
SDRAM1
VSS
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD
SDATA
SDRAM1
BUF_IN
SDRAM2
SDRAM3
SDRAM12
SDATA
I2C
SCLOCK
I/O
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1
1
2
3
4
5
6 28-Pin
H, S
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SDRAM11
SDRAM10
VSS
VDD
SDRAM9
SDRAM8
VSS
VDD
SDRAM7
SDRAM6
VSS
VSS
SCLK
PS8319
05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
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Pin Description
Pin
Symbol
Type
Quantity
2,3,6,7,10,11,
SDRAM [0.5]
0
6
SDRAM Byte 0 clock output
18,19,22,23,26,27
SDRAM [6.11]
0
6
SDRAM Byte 1 clock output
12
SDRAM [12]
0
1
SDRAM Byte 2 clock output
9
BUF_IN
1
1
Input for 1- 13- buffer
14
SDATA
I/O
1
Data pin for I2C circuitry. Has a 100k
Internal pull- up resistor
154
SCLOCK
I/O
1
Clock pin for I2C circuitry. Has a
100k Internal pull- up resistor
1,5,13,20,24,28
VDD
Power
6
3.3V power supply for SDRAM buffer
4,8,16,17,21,25
VSS
Ground
6
Ground for SDRAM Buffers
PI6C184-02 I2C Address Assignment
De s cription
PI6C184 Serial Configuration Map
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
De s cription
Bit 7
11
SDRAM5 (Active/Inactive)
Bit 6
10
SDRAM4(Active/Inactive)
Bit 5
~
Reserved
Bit 4
~
Reserved
Bit 3
7
SDRAM3 (Active/Inactive)
Bit 2
6
SDRAM2 (Active/Inactive)
Bit 1
3
SDRAM1 (Active/Inactive)
Bit 0
2
SDRAM0 (Active/Inactive)
Note:
Inactive means outputs are held LOW and
are disabled from switching
2
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PS8319
05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
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2-Wire I2C Control
The I2C interface permits individual enable/disable of each
clock output and test mode enable.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is
always a 7-bit address byte followed by a read/write bit. (HIGH
= read from addressed device, LOW = write to addressed
device). If the device’s own address is detected, PI6C184-02
generates an acknowledge by pulling SDATA line LOW during
ninth clock pulse, then accepts the following data bytes until
another start or stop condition is detected.
The PI6C184-02 is a slave receiver device. It can not be read
back. Sub addressing is not supported. All preceding bytes
must be sent in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB
first), followed by an acknowledge bit generated by the
receiving device.
During normal data transfers Sdata changes only when SCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA
while SCLK is HIGH indicates a “start” condition. A LOW to
HIGH transition on SDATA while SCLK is HIGH is a “stop”
condition and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
Byte2: Optional Register for Possible Future
(1 = enable, 0 = disable)
Requirements (1 = enable, 0 = disable)
Bit
Pin #
Bit 7
27
Bit 6
De s cription
Bit
Pin #
SDRAM11 (Active/Inactive)
Bit 7
N/A
26
SDRAM10 (Active/Inactive)
Bit 6
12
Bit 5
23
SDRAM9 (Active/Inactive)
Bit 5
N/A
(Reserved)
Bit 4
22
SDRAM8 (Active/Inactive)
Bit 4
N/A
(Reserved)
Bit 3
N/A
(Reserved)
Bit 3
N/A
(Reserved)
Bit 2
N/A
(Reserved)
Bit 2
N/A
(Reserved)
Bit 1
19
SDRAM7 (Active/Inactive)
Bit 1
N/A
(Reserved)
Bit 0
18
SDRAM6 (Active/Inactive)
Bit 0
N/A
(Reserved)
Storage Temperature ................................................ –65°C to +150°C
DC Input Voltage ..................................................... –0.5V to +4.6V
Parame te r
Te s t Condition
SDRAM12 (Active/Inactive)
5
7
8
9
10
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
12
13
14
M in.
Typ.
M ax
IDD
Supply Current
BUF_IN = 0 MHz
IDD
Supply Current
BUF_IN = 66.66 MHz
230
IDD
Supply Current
BUF_IN = 100.0 MHz
360
Units
15
3
3
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4
(Reserved)
Supply Current (VDD = +3.465V, Cload = max)
Symbol
3
11
(Above which the useful life may be impaired. For user guidelines, not tested.)
3.3V Supply Voltage to Ground Potential ............... –0.5V to +4.6V
2
6
De s cription
Maximum Ratings
Ambient Temperature with Power Applied ............. –0°C to +70°C
1
mA
PS8319
05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
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DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C)
Symbol
Parame te r
Te s t Condition
M in.
M ax.
Units
2.0
VDDCORE +0.3
VSS –0.3
0.8
0 < VIN < VDD
-5
+5
2.4
Input Voltage , VDDCORE [0-1] = 3.3V± 5%
VIH
Input High Voltage
VIL
Input Low Voltage
IIL
Input Leakage Current
VDD
V
VDD = 3.3V ± 5%
VOH
Output High Voltage
IOH = –1mA
VOL
Output Low Voltage
IOL = –1mA
CIN
Input Pin Capacitance
5
COUT
Output pins Capacitance
6
LPIN
Pin Inductance
7
nH
70
ºC
TA
Ambient Temperature
V
0.4
No Airflow
0
pF
SDRAM Clock Buffer Operating Specification
Symbol
Parame te r
Condition
M in. Typ.
M ax.
Units
IOHMIN
Pull- up current
VOUT = 2.0V
IOHMAX
Pull- up current
VOUT = 3.135V
–46
mA
IOLMIN
Pull- down current
VOUT = 1.0V
IOLMAX
Pull- down current
VOUT = 0.4V
tRHSDRAM
O utput rise edge rate
SDRAM only
3.3V ±5%
@04V- 2.4V
1.5
4
tFHSDRAM
O utput fall edge rate
SDRAM only
3.3V ±5%
@2.4V- 0.4V
1.5
4
–54
54
53
V/ns
AC Timing
Symbol
Parame te r
66 M Hz
100 M Hz
M in.
M ax.
M in.
M ax.
15.5
10.0
10.5
Units
tSDKP
SDRAM CLK period
15.0
tSDKH
SDRAM CLK high time
5.6
3.3
tSDKL
SDRAM CLK low time
5.3
3.1
tSDRISE
SDRAM CLK rise time
1.5
4.0
1.5
4.0
tSDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
tpLH
SDRAM Buffer LH prop delay
1.0
5.0
1.0
5.0
tpHL
SDRAM Buffer HL prop delay
1.0
5.0
1.0
5.0
tpZL,tpZH
SDRAM Buffer Enable delay
1.0
8.0
1.0
8.0
tpLZ,tpHZ
SDRAM Buffer Disable delay
1.0
8.0
1.0
8.0
Duty Cycle
Measured at 1.5V
45
55
45
55
%
tSDSKW
SDRAM Output to
Output Skew
250
ps
ns
250
4
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V/ns
ns
PS8319
05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
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1
Test
Output
Point
Buffer
2
Test Load
3
tSDKP
tSDKH
3.3V
2.4
Clocking
4
1.5
Interface
0.4
(TTL)
5
tSDKL
tSDRISE
tSDFALL
6
Input
1.5V
1.5V
Waveform
tplh
7
tphl
Output
1.5V
Waveform
8
1.5V
9
Figure 1. Clock Waveforms
10
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
M in Load M ax Load
20
30
Units
pF
Note s
SDRAM DIMM
Specification
11
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
12
13
Design Guidelines to Reduce EMI
14
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10 pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
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15
PS8319
05/03/00
PI6C184-02
Precision 1-13 Clock Buffer
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PI6C184
Ω
100/66 MHz
22
13
SDRAM
Clock from
SDRAM
DIMM
CI
Chipset
Spec.
Figure 2. Design Guidelines
28-pin SSOP (H)
28
.197
5.00
.220
5.60
1
.390
.004
0.09
.413
.009
0.25
9.90
10.50
.078
0.55
.022
0.95
.037
Max
2.0
.291
.322
SEATING
PLANE
7.40
8.20
.0256
.0098
BSC
Max.
0.65
0.25
X.XX
DENOTES DIMENSIONS
X.XX
IN MILLIMETERS
.002
Min
0.050
28-pin SOIC (S)
28
.2914
.2992
7.40
7.60
.010
.029
1
.6969 17.70
.7125 18.10
0.254
x 45˚
0.737
.0091
.0125
0-8˚
.021 0.533
.031 0.787
.0926
.1043
REF
2.35
2.65
0.41 .016
1.27 .050
SEATING
PLANE
.050
BSC
1.27
.0040
.0118
.013
.020
0.33
0.51
0.23
0.32
.394
.419
10.00
10.65
0.10
0.30
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
P/N
De s cription
PI6C184- 02H
28- pin SSOP Package
PI6C184- 02S
28- pin SOIC Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6
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PS8319
05/03/00