PI6C180 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Precision 1-18 Clock Buffer Product Features Description • High-speed, to 100 MHz The PI6C180, a high-speed low-noise 1-18 non-inverting buffer designed for SDRAM clock buffer applications operates up to 100 MHz. • Low-noise non-inverting 1-18 buffer • Supports up to four SDRAM DIMMs At power up all SDRAM output are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 18 output drivers. • Low skew (< 250ps) between any two output clocks • I2C Serial Configuration interface The output enable (OE) pin may be pulled low to put all outputs in a Hi-Z state. • Multiple VDD, VSS pins for noise reduction • 3.3V power supply voltage Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips. • Separate Hi-Z pin for testing • 48-pin SSOP package (V) Logic Block Diagram Product Pin Configuration SDRAM0 SDRAM1 BUF_IN SDRAM2 NC 1 48 NC NC 2 47 NC VDD0 3 46 VDD9 SDRAM0 4 45 SDRAM15 SDRAM1 5 44 SDRAM14 VSS0 6 43 VSS9 VDD1 7 42 VDD8 SDRAM2 8 41 SDRAM13 9 40 SDRAM12 10 48-Pin 39 VSS8 38 OE SDRAM3 VSS1 SDRAM3 SDRAM17 OE SDATA SCLOCK I2C I/O 1 V BUF_IN 11 VDD2 12 37 VDD7 SDRAM4 13 36 SDRAM11 SDRAM5 14 35 SDRAM10 VSS2 15 34 VSS7 VDD3 16 33 VDD6 SDRAM6 17 32 SDRAM9 SDRAM7 18 31 SDRAM8 VSS3 19 30 VSS6 VDD4 20 29 VDD5 SDRAM16 21 28 SDRAM17 VSS4 22 27 VSS5 VDDIIC SDATA 23 26 25 VSSIIC SCLOCK 24 PS8141D 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Description Pin Symbol 4,5,8,9 Type Qty De s cription SDRAM[0- 3] O 4 SDRAM Byte 0 clock output 13,14,17,18 SDRAM[4- 7] O 4 SDRAM Byte 1 clock output 31,32,35,36 SDRAM[8- 11] O 4 SDRAM Byte 2 clock output 4 0 , 4 1, 4 4 , 4 5 SDRAM[12- 15] O 4 SDRAM Byte 3 clock output 2 1, 2 8 SDRAM[16- 17] O 4 SDRAM clock outputs usable for feedback 11 BUF_IN I 1 Input for 1- 18 buffer 38 OE I 1 Hi- Z all outputs when held LOW. Has a >100kohm internal pull- up resistor 24 SDATA I/O 1 Data pin for I2C circuitry. Has a >100kohm internal pull- up resistor 25 SCLOCK I/O 1 Clock pin I2C circuitry. Has a >100kohm internal pull- up resistor 3,7,12,16,20, 29,33,37, 42,46 VDD[0-9] Power 10 3.3V power supply for SDRAM buffers 6,10,15,19,22,27,30,34, 39,43 VSS[0-9] Ground 10 Ground for SDRAM buffers 23 VDDIIC Power 1 3.3V power supply for I2C circuitry 26 VSSIIC Ground 1 Ground for I2C circuitry Reserved 4 Reserved for future modification. No connects 1,2,47,48 NC OE Functionality PI6C180 Serial Configuration Map OE SDRAM [0-17] Note 0 Hi- Z 1 1 BUF_IN 2 Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Notes: 1. Used for test purposes only 2. Buffers are non-inverting PI6C180 I2C Address Assignment Bit Pin Numbe r De s cription Bit 7 18 SDRAM7 (Active/Inactive) Bit 6 17 SDRAM6 (Active/Inactive) Bit 5 14 SDRAM5 (Active/Inactive) Bit 4 13 SDRAM4 (Active/Inactive) Bit 3 9 SDRAM3 (Active/Inactive) Bit 2 8 SDRAM2 (Active/Inactive) A6 A5 A4 A3 A2 A1 A0 R/W Bit 1 5 SDRAM1 (Active/Inactive) 1 1 0 1 0 0 1 0 Bit 0 4 SDRAM0 (Active/Inactive) Note: Inactive means outputs are held LOW and are disabled from switching. 2 PS8141D 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2-Wire I2C Control The I2C interface permits individual enable/disable of each clock output and test mode enable. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW= write to addressed device). If the device’s own address is detected, PI6C180 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. The PI6C180 is a slave receiver device. It can not be read back. Sub addressing is not supported. All preceding bytes must be sent in order to change one of the control bytes. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLOCK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLOCK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATAwhile SCLOCK is HIGH is a “stop” condition and indicates the end of a data transfer cycle. Following acknowledgement of the address byte (D2), two more bytes must be sent: 1. “Command Code” byte, and 2. “Byte Count” byte. Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged. Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Pin # Bit 7 45 Bit 6 Byte2: Optional Register for Possible Future Requirements (1 = enable, 0 = disable) De s cription Bit Pin # De s cription SDRAM15 (Active/Inactive) Bit 7 28 SDRAM17 (Active/Inactive) 44 SDRAM14 (Active/Inactive) Bit 6 21 SDRAM16 (Active/Inactive) Bit 5 41 SDRAM13 (Active/Inactive) Bit 5 (Reserved) Bit 4 40 SDRAM12 (Active/Inactive) Bit 4 (Reserved) Bit 3 36 SDRAM11 (Active/Inactive) Bit 3 (Reserved) Bit 2 35 SDRAM10 (Active/Inactive) Bit 2 (Reserved) Bit 1 32 SDRAM9 (Active/Inactive) Bit 1 (Reserved) Bit 0 31 SDRAM8 (Active/Inactive) Bit 0 (Reserved) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS Storage Temperature ........................................ –65°C to +150°C may cause permanent damage to the device. This is a stress Ambient Temperature with Power Applied .......... –0°C to +70°C rating only and functional operation of the device at these or any 3.3V Supply Voltage to Ground Potential ........... –0.5V to +4.6V other conditions above those indicated in the operational sections of this specification is not implied. Exposure to DC Input Voltage ................................................ –0.5V to +4.6V absolute maximum rating conditions for extended periods may affect reliability. Supply Current (VDD = +3.465V, CLOAD = Max.) Symbol Parame te r Te s t Condition IDD Supply Current BUF_IN = 0 MHz IDD Supply Current BUF_IN = 66.66 MHz 230 IDD Supply Current BUF_IN = 100.0 MHz 360 3 M in. Typ. M ax. Units 3 PS8141D mA 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C) Symbol Parame te r Te s t Condition M in. M a x. Units VDD 2.0 VDD +0.3 VSS - 0.3 0.8 0 < VIN < VDD -5 +5 2.4 Input Voltage VIH Input high voltage VIL Input low voltage IIL Input leakage current V mA VDD[0-9] = 3.3V ±5% VOH Output high voltage IOH = - 1mA VOL Output low voltage IOL = 1mA COUT Output pin capacitance 6 CIN Input pin capacitance 5 LPIN Pin Inductance 7 nH 70 °C TA Ambient Temperature V 0.4 No Airflow 0 pF SDRAM Clock Buffer Operating Specification Symbol Parame te r Te s t Conditions M in. Typ. M a x. IOHMIN Pull- up current VOUT = 2.0V IOHMAX Pull- up current VOUT = 3.135V IOLMIN Pull- down current VOUT = 1.0V IOLMAX Pull- down current VOUT = 0.4V tRHSDRAM Output rise edge rate SDRAM only 3.3V ±5% @04V- 2.4V 1.5 4 tTHSDRAM Output fall edge rate SDRAM only 3.3V ±5% @2.4V- 0.4V 1.5 4 Units –54 –46 54 mA 53 V/ns AC Timing Symbol Parame te r 66 M Hz Units 100 M Hz M in. M a x. M in. M a x. 15.5 10.0 10.5 tS DK P SDRAM CLK period 15.0 tS DK H SDRAM CLK high time 5.6 3.3 tS DK L SDRAM CLK low time 5.3 3.1 tS DRIS E SDRAM CLK rise time 1.5 4.0 1. 5 4.0 tS DFALL SDRAM CLK fall time 1.5 4.0 1.5 4.0 tP LH SDRAM Buffer LH prop delay 1.0 5.0 1.0 5.0 tP HL SDRAM Buffer HL prop delay 1.0 5.0 1.0 5.0 tP ZL,tP ZH SDRAM Buffer Enable delay 1.0 8.0 1. 0 8.0 tP LZ,tP HZ SDRAM Buffer Disable delay 1.0 8.0 1.0 8.0 Duty Cycle Measured at 1.5V 45 55 45 55 % tS DS K W SDRAM Output to Output Skew 250 ps 250 4 ns V/ns ns PS8141D 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Point Output Buffer Test Load tSDKP tSDKH 3.3V Clocking Interface (TTL) 2.4 1.5 0.4 tSDKL tSDRISE Input Waveform tSDFALL 1.5V 1.5V tplh tphl Output Waveform 1.5V 1.5V Figure 1. Clock Waveforms Minimum & Maximum Expected Capacitive Loads Clock M in. Load SDRAM 20 M ax. Load Units 30 pF Design Guidelines to Reduce EMI 1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of “vias” of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors. Note s SDRAM DIMM Specification Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500-ohm resistor in parallel. 5 PS8141D 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PCB Layout Suggestion C1 VDD C2 46 4 45 C11 VDD Ferrite Bead 44 6 43 VSS VDD 7 42 VDD 8 41 9 40 10 39 11 38 12 37 13 36 14 35 VSS 15 34 VSS VDD 16 33 VDD 17 32 18 31 VSS 19 30 VSS VDD 20 29 VDD VDD C6 47 3 5 C3 C5 48 2 VSS VSS C4 1 VCC C12 C10 22uF VSS C9 VDD 21 28 VSS 22 27 VSS VDD 23 26 VSS 24 25 C8 C7 Via to GND Plane Via to VDD Plane Void in Power Plane Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C1-C11 should be placed as close as possible to their respective VDD. Recommended capacitor values: C1-C11 .............. 0.1µF, ceramic C12 ................. 22µF PI6C180 100/66 MHz Clock from Chipset SDRAM 18 22Ω CI SDRAM DIMM Spec. Figure 2. Design Guidelines 6 PS8141D 09/18/03 PI6C180 Precision 1-18 Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-Pin SSOP (V) Package 48 .291 .299 7.39 7.59 .395 .420 10.03 10.67 Gauge Plane .010 0.25 .02 0.51 .04 1.01 1 .620 .630 15.75 16.00 .015 0.381 x 45˚ .025 0.635 .008 0.20 Nom. .110 2.79 Max .025 BSC 0.635 .008 0.20 .0135 0.34 .008 0.20 .016 0.40 0-8˚ X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Table of Dimensions Body E (Width) D (Le ngth) A (He ight) e (Pin-to-Pin pitch) 48 pins Min. 0.291 0.620 0.095 0.025 (300 mil) Max. 0.299 0.630 0.110 — Ordering Information P/N De s cription PI6C180V 48- pin SSOP Package Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS8141D 09/18/03