ETC PI6C184H

PI6C184
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Precision 1-13 Clock Buffer
Description
Product Features
The PI6C184 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
• High speed, low noise non-inverting 1-13 buffer
• Supports up to four SDRAM DIMMs
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
• Low skew (< 250ps) between any two output clocks
• I2C Serial Configuration interface
At power up all SDRAM output are enabled and active. The I 2C
Serial control may be used to individually activate/deactivate any
of the 13 output drivers.
• Multiple VDD, VSS pins for noise reduction
• 3.3V power supply voltage
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
• Separate Hi-Z pin for testing
• 28-pin SSOP and SOIC packages (H, S)
Block Diagram
Pin Configuration
SDRAM0
SDRAM1
BUF_IN
SDRAM2
SDRAM3
SDRAM12
SDATA
SCLOCK
I2C
I/O
1
VDD
1
28
VDD
SDRAM0
2
27
SDRAM11
SDRAM1
3
26
SDRAM10
VSS
4
25
VSS
VDD
5
24
VDD
SDRAM2
6
23
SDRAM9
SDRAM3
7
22
SDRAM8
VSS
8
21
VSS
BUF_IN
9
20
VDD
SDRAM4
10
19
SDRAM7
SDRAM5
11
18
SDRAM6
SDRAM12
12
17
VSS
VDD
13
16
VSS
SDATA
14
15
SCLK
28-Pin
H, S
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Pin Description
Pin
Symbol
Type
Quantity
2,3,6,7,10,11,18,19
SDRAM [0.7]
0
8
SDRAM Byte 0 clock output
26,27,12
SDRAM [10.12]
0
3
SDRAM Byte 1 clock output
22,23
SDRAM [8.9]
0
2
SDRAM Byte 2 clock output
9
BUF_IN
1
1
Input for 1- 13- buffer
14
SDATA
I/O
1
Data pin for I2C circuitry. Has a
100k Internal pull- up resistor
154
SCLOCK
I/O
1
Clock pin for I2C circuitry. Has a 100k Intrnal pull- up resistor
1,5,13,20,24,28
VDD
Power
6
3.3V power supply for SDRAM buffer
4,8,16,17,21,25
VSS
Ground
6
Ground for SDRAM Buffers
PI6C184 I2C Address Assignment
PI6C184 Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
Bit 7
19
SDRAM7 (Active/Inactive)
Bit 6
18
SDRAM6 (Active/Inactive)
Bit 5
11
SDRAM5 (Active/Inactive)
Bit 4
10
SDRAM4 (Active/Inactive)
Bit 3
7
SDRAM3 (Active/Inactive)
Bit 2
6
SDRAM2 (Active/Inactive)
Bit 1
3
SDRAM1 (Active/Inactive)
Bit 0
2
SDRAM0 (Active/Inactive)
De s cription
De s cription
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
Note:
Inactive means outputs are held LOW and
are disabled from switching
2
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C184 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
The PI6C184 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Each data transfer is initiated with a start condition and ended with
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit
Pin #
De s cription
Bit
Pin #
De s cription
Bit 7
NC (Initialize to 0)
Bit 7
23
SDRAM9 (Active/Inactive)
Bit 6
NC (Initialize to 0)
Bit 6
22
SDRAM8 (Active/Inactive)
Bit 5
NC (Initialize to 0)
Bit 5
-
(Reserved)
Bit 4
NC (Initialize to 0)
Bit 4
-
(Reserved)
Bit 3
NC (Initialize to 0)
Bit 3
-
(Reserved)
Bit 2
12
SDRAM12 (Active/Inactive)
Bit 2
-
(Reserved)
Bit 1
27
SDRAM11(Active/Inactive)
Bit 1
-
(Reserved)
Bit 0
26
SDRAM10 (Active/Inactive)
Bit 0
-
(Reserved)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................... –65°C to +150°C
Ambient Temperature with Power Applied ................. –0°C to +70°C
3.3V Supply Voltage to Ground Potential .................. –0.5V to +4.6V
DC Input Voltage ....................................................... –0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol
Parame te r
Te s t Condition
M in.
Typ.
M ax.
IDD
Supply Current
BUF_IN = 0 MHz
IDD
Supply Current
BUF_IN = 66.66 MHz
230
IDD
Supply Current
BUF_IN = 100.0 MHz
360
3
Units
3
mA
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C)
Symbol
Parame te r
Te s t Condition
M in.
M ax.
Units
VDD
2.0
VDD +0.3
VSS –0.3
0.8
0 < VIN < VDD
–5
+5
2.4
Input Voltage
VIH
Input high voltage
VIL
Input low voltage
IIL
Input leakage current
V
mA
VDD[0- 9] = 3.3V ±5%
VOH
Output high voltage
IOH = - 1mA
VOL
Output low voltage
IOL = 1mA
COUT
Output pin capacitance
6
CIN
Input pin capacitance
5
LPIN
Pin Inductance
7
nH
70
°C
TA
Ambient Temperature
V
0.4
No Airflow
0
pF
SDRAM Clock Buffer Operating Specification
Symbol
Parame te r
Te s t Conditions
M in.
Typ.
M ax.
IOHMIN
Pull- up current
VOUT = 2.0V
IOHMAX
Pull- up current
VOUT = 3.135V
IOLMIN
Pull- down current
VOUT = 1.0V
IOLMAX
Pull- down current
VOUT = 0.4V
tRHSDRAM
Output rise edge rate SDRAM only
3.3V ±5% @ 04V- 2.4V
1.5
4
tTHSDRAM
Output fall edge rate SDRAM only
3.3V ±5% @ 2.4V- 0.4V
1.5
4
Units
–54
–46
54
mA
53
V/ns
AC Timing
Symbol
66 M Hz
Parame te r
100 M Hz
M in.
M ax.
M in.
M ax.
15.5
10.0
10.5
Units
tSDKP
SDRAM CLK period
15.0
tSDKH
SDRAM CLK high time
5.6
3.3
tSDKL
SDRAM CLK low time
5.3
3.1
tSDRISE
SDRAM CLK rise time
1.5
4.0
1.5
4.0
tSDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
tPLH
SDRAM Buffer LH propagation delay
1.0
5.0
1.0
5.0
tPHL
SDRAM Buffer HL propagation delay
1.0
5.0
1.0
5.0
tPZL,tPZH
SDRAM Buffer Enable delay
1.0
8.0
1.0
8.0
tPLZ,tPHZ
SDRAM Buffer Disable delay
1.0
8.0
1.0
8.0
Duty Cycle
Measured at 1.5V
45
55
45
55
%
250
ps
tSDSKW
SDRAM O utput to O utput Skew
250
4
ns
V/ns
ns
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
Test
Point
Output
Buffer
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
tSDRISE
Input
tSDFALL
1.5V
1.5V
Waveform
tphl
tplh
Output
1.5V
Waveform
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock
M in. Load
M ax. Load
Units
SDRAM
20
30
pF
Note s
SDRAM DIMM Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PCB Layout Suggestion
C1
C4
1
28
2
27
3
26
VSS
4
25
VSS
VDD
5
24
VDD
6
23
7
22
8
21
9
20
10
19
11
18
12
17
VSS
13
16
VSS
14
15
VDD
C2
VSS
C3
VDD
Ferrite Bead
VCC
C7
VSS
C5
22µF
C6
VDD
Via to GND Plane
Via to VDD Plane
VDD
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C7 should be placed as close as possible to
their respective VDD.
Recommended capacitor values:
C1-C7 .............. 0.1µF, ceramic
C8 .................. 22µF
PI6C184
100/66 MHz
Clock from
Chipset
22Ω
13
SDRAM
CL
SDRAM
DIMM
Spec.
Figure 2. Design Guidelines
6
PS8320A
02/05/01
PI6C184
Precision 1-13 Clock Buffer
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123
28-pin SSOP Package Mechanical (H)
28-pin SOIC Package Mechanical (S)
28
.2914
.2992
7.40
7.60
.010
.029
1
.6969 17.70
.7125 18.10
0.254
x 45˚
0.737
.0091
.0125
0-8˚
.021 0.533
.031 0.787
.0926
.1043
REF
2.35
2.65
0.41 .016
1.27 .050
SEATING
PLANE
.050
BSC
1.27
.013
.020
0.33
0.51
.0040
.0118
0.23
0.32
.394
.419
10.00
10.65
0.10
0.30
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
P/N
De s cription
PI6C184H
28- pin SSOP Package
PI6C184S
28- pin SOIC Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
7
PS8320A
02/05/01