PMWD26UN Dual µTrenchMOS™ ultra low level FET Rev. 01 — 22 January 2003 M3D647 Product data 1. Product profile 1.1 Description Dual N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PMWD26UN in SOT530-1 (TSSOP8). 1.2 Features ■ Surface mounting package ■ Very low threshold ■ Low profile ■ Fast switching. 1.3 Applications ■ Portable appliances ■ Battery management ■ PCMCIA cards ■ Load switching. 1.4 Quick reference data ■ VDS ≤ 20 V ■ Ptot ≤ 2.3 W ■ ID ≤ 5.2 A ■ RDSon ≤ 30 mΩ 2. Pinning information Table 1: Pinning - SOT530-1, simplified outline and symbol Pin Description 1 drain1 (d1) 2,3 source1 (s1) 4 gate1 (g1) 5 gate2 (g2) 6,7 source2 (s2) 8 drain2 (d2) Simplified outline 8 5 1 4 Symbol d1 s1 Top view MBK885 SOT530-1 d2 g1 s2 g2 MSD901 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 20 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 20 V VGS gate-source voltage - ±10 V ID drain current (DC) Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 - 5.2 A Tsp = 100 °C; VGS = 4.5 V; Figure 2 - 3.1 A IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 18 A Tsp = 25 °C; Figure 1 Ptot total power dissipation - 2.3 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp = 25 °C - 2 A ISM peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 7 A © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 2 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 03aa17 120 03aa25 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 0 200 50 100 Tsp (°C) 150 200 Tsp (°C) VGS ≥ 4.5 V P tot P der = ----------------------- × 100% P ° ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. Fig 2. Normalized continuous drain current as a function of solder point temperature. 003aaa266 102 ID (A) Limit RDSon = VDS / ID tp = 10 µs 10 1 ms 10 ms 1 DC 100 ms 1s 10-1 10-2 10-1 10 1 VDS (V) 102 Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 3 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 4. Thermal characteristics Table 3: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit K/W Rth(j-sp) thermal resistance from junction to solder point Figure 4 - 55 70 Rth(j-a) thermal resistance from junction to ambient minimum footprint; mounted on printed-circuit board - 100 - K/W 4.1 Transient thermal impedance 003aaa267 102 Zth(j-sp) (K/W) δ = 0.5 0.2 10 0.1 0.05 0.02 single pulse 1 δ= P tp T t tp T 10-1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 4 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 5. Characteristics Table 4: Characteristics Tj = 25 °C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 20 - - V Tj = −55 °C 18 - - V 0.45 0.7 - V Tj = 25 °C - - 1 µA Tj = 150 °C - - 100 µA - - 100 nA Tj = 25 °C - 26 30 mΩ Tj = 150 °C - 44 51 mΩ VGS = 1.8 V; ID = 3.5 A; Figure 7 - 34 40 mΩ VGS = 2.5 V; ID = 3.5 A; Figure 7 - 29 35 mΩ ID = 4 A; VDD = 16 V; VGS = 4.5 V; Figure 13 - 23.6 - nC Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 IDSS drain-source leakage current VDS = 20 V; VGS = 0 V IGSS gate-source leakage current VGS = ±10 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 4.5 V; ID = 3.5 A; Figure 7 and 8 Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge - 2.1 - nC Qgd gate-drain (Miller) charge - 6.7 - nC Ciss input capacitance - 1366 - pF Coss output capacitance - 339 - pF Crss reverse transfer capacitance - 239 - pF td(on) turn-on delay time - 14 - ns VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11 VDD = 10 V; ID = A; VGS = 4.5 V; RG = 6 Ω tr rise time - 22 - ns td(off) turn-off delay time - 56 - ns tf fall time - 33 - ns Source-drain diode VSD source-drain (diode forward) voltage IS = 4 A; VGS = 0 V; Figure 12 trr reverse recovery time Qr recovered charge IS = 4 A; dIS/dt = −100 A/µs; VR = 20 V; VGS = 0 V 0.67 1.2 V 45 - ns - 13 - nC © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data - Rev. 01 — 22 January 2003 5 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 003aaa268 5 ID (A) 4 003aaa269 10 4.5 V ID (A) 8 1.8 V VGS = 1.3 V 1.2 V 3 Tj = 150 °C 6 2 4 1.1 V 25 °C 1 2 1.0 V 0 0 0.2 0.4 0.6 0 0.8 1 VDS (V) Tj = 25 °C 0 0.5 1 1.5 V 2 GS (V) Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 003aaa270 80 RDSon 03aa27 2 a (mΩ) 1.1 V 1.5 60 1.2 V 1 40 1.3 V 0.5 1.8 V 20 VGS = 2.5 V 4.5 V 0 0 0 1 2 3 ID (A) 4 -60 Tj = 25 °C 60 120 Tj (°C) 180 R DSon a = ----------------------------R DSon ( 25°C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data 0 Rev. 01 — 22 January 2003 6 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 03aj65 1 03aj64 10-3 VGS(th) (V) 0.8 ID (A) typ 10-4 0.6 min typ min 0.4 10-5 0.2 10-6 0 -60 0 60 120 Tj (°C) 0 180 0.2 0.4 0.6 0.8 1 VGS (V) Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. 104 003aaa271 Fig 10. Sub-threshold drain current as a function of gate-source voltage. 003aaa272 4 IS (A) C (pF) 3 150 °C Ciss 103 2 Tj = 25 °C 1 Coss Crss 102 10-1 0 1 102 10 0 0.2 0.4 0.6 VDS (V) Tj = 25 °C and 150 °C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data 0.8 1 VSD (V) Rev. 01 — 22 January 2003 7 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 003aaa273 5 VGS (V) 4 3 2 1 0 0 5 10 15 20 25 QG (nC) ID = 4 A; VDD = 16 V Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 8 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 6. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 E A D X c y HE v M A Z 8 5 A2 A (A3) A1 pin 1 index θ Lp L detail X 1 4 e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.10 0.15 0.05 0.95 0.85 0.25 0.30 0.19 0.20 0.13 3.10 2.90 4.50 4.30 0.65 6.50 6.30 0.94 0.70 0.50 0.10 0.10 0.10 0.70 0.35 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT530-1 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-02-24 MO-153 Fig 14. SOT530-1 (TSSOP8). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 9 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 7. Revision history Table 5: Revision history Rev Date 01 20030122 CPCN Description - Product data (9397 750 10834) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Product data Rev. 01 — 22 January 2003 10 of 12 PMWD26UN Philips Semiconductors Dual µTrenchMOS™ ultra low level FET 8. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 9. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V 10. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 9397 750 10834 Rev. 01 — 22 January 2003 11 of 12 Philips Semiconductors PMWD26UN Dual µTrenchMOS™ ultra low level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 22 January 2003 Document order number: 9397 750 10834