PMV117EN µTrenchMOS™ enhanced logic level FET Rev. 02 — 7 April 2005 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology. 1.2 Features ■ Logic level threshold ■ Subminiature surface-mounted package ■ Very fast switching 1.3 Applications ■ Battery management ■ High-speed switch ■ Low power DC-to-DC converter 1.4 Quick reference data ■ VDS ≤ 30 V ■ RDSon ≤ 117 mΩ (VGS = 10 V) ■ ID ≤ 2.5 A ■ Ptot ≤ 0.83 W 2. Pinning information Table 1: Pinning Pin Description 1 gate (G) 2 source (S) 3 drain (D) Simplified outline Symbol D 3 G 1 2 SOT23 mbb076 S PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 3. Ordering information Table 2: Ordering information Type number PMV117EN Package Name Description Version TO-236AB plastic surface mounted package; 3 leads SOT23 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage (DC) - ±20 V ID drain current (DC) Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 - 2.5 A Tsp = 100 °C; VGS = 10 V; Figure 2 - 1.6 A IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 10 A Ptot total power dissipation Tsp = 25 °C; Figure 1 - 0.83 W Tstg storage temperature −65 +150 °C Tj junction temperature −65 +150 °C Source-drain diode IS source (diode forward) current (DC) Tsp = 25 °C - 0.8 A ISM peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 3.3 A 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 2 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 03aa17 120 03aa25 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 Tsp (°C) 200 0 50 100 150 Tsp (°C) 200 VGS ≥ 10 V P tot P der = ------------------------ × 100 % P ° ID I der = --------------------- × 100 % I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature Fig 2. Normalized continuous drain current as a function of solder point temperature 03ak56 102 ID (A) 10 Limit RDSon = VDS / ID tp = 10 µs 100 µs 1 1 ms 10 ms DC 100 ms 10−1 10−2 10−1 1 102 10 VDS (V) Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 3 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter thermal resistance from junction to solder point Rth(j-sp) Conditions Min Typ Max Unit Figure 4 - - 100 K/W 03ak55 103 Zth(j-sp) (K/W) 102 δ = 0.5 0.2 10 0.1 0.05 0.02 δ= P single pulse tp T t tp T 1 10−4 10−3 10−2 10−1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 4 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tj = 25 °C 30 37 - V Tj = −55 °C 27 - - V Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 10 µA; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 and 10 Tj = 25 °C 1.5 2 - V Tj = 150 °C 1.1 - - V Tj = −55 °C - - 2.7 V Tj = 25 °C - 0.01 0.5 µA Tj = 150 °C - - 10 µA - 10 100 nA - 74 117 mΩ 117 190 mΩ 188 300 mΩ - 4.6 - nC - 0.6 - nC - 1.35 - nC - 147 - pF - 65 - pF - 41 - pF - 4 - ns VDS = 24 V; VGS = 0 V IGSS gate-source leakage current VGS = ±20 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 10 V; ID = 500 mA; Figure 6 and 8 Tj = 25 °C VGS = 4.5 V; ID = 500 mA; Figure 6 and 8 Tj = 25 °C - Tj = 150 °C Dynamic characteristics Qg(tot) total gate charge Qgs gate-source charge Qgd gate-drain (Miller) charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time ID = 0.5 A; VDD = 15 V; VGS = 10 V; Figure 11 VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 13 VDD = 15 V; RL = 15 Ω; VGS = 10 V tr rise time - 7.5 - ns td(off) turn-off delay time - 18 - ns tf fall time - 13 - ns Source-drain diode VSD source-drain (diode forward) voltage IS = 0.83 A; VGS = 0 V; Figure 12 - 0.7 1.2 V trr reverse recovery time IS = 1 A; dIS/dt = −100 A/µs; VGS = 0 V; VDS = 25 V - 69 - ns 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 5 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 03ak57 3 10 6 4.5 03ak58 400 3.4 3.8 3.6 RDSon (mΩ) ID (A) 3.2 VGS (V) = 3 Tj = 25 ˚C 3.2 3.4 300 2 3 3.6 200 3.8 2.8 1 4.5 6 100 2.6 10 VGS (V) = 2.4 0 0 0.2 0.4 0.6 0.8 0 1 0 VDS (V) Tj = 25 °C 1 2 ID (A) 3 Tj = 25 °C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values 03ak59 3 03ad57 2 VDS > ID × RDSon a ID (A) 1.5 2 1 1 Tj = 150 ˚C 0.5 25 ˚C 0 0 1 2 3 VGS (V) 4 0 −60 Tj = 25 °C and 150 °C; VDS > ID × RDSon 60 120 Tj (°C) 180 R DSon a = ----------------------------R DSon ( 25 °C ) Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 9397 750 14709 Product data sheet 0 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 6 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 03ak63 2.5 VGS(th) (V) typ 10−2 2 min 1.5 10−3 1 10−4 0.5 10−5 0 −60 03ak64 10−1 ID (A) min typ 10−6 0 60 120 Tj (°C) 180 0 0.8 1.6 2.4 VGS (V) 3.2 Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage 03ak62 10 VGS (V) ID = 0.5 A Tj = 25 °C VDD = 15 V 8 6 4 2 0 0 2 4 QG (nC) 6 ID = 0.5 A; VDD = 15 V Fig 11. Gate-source voltage as a function of gate charge; typical values 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 7 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 03ak60 3 03ak61 103 VGS = 0 V IS (A) C (pF) 2 Ciss 102 Coss 1 Tj = 150 ˚C 0 0 0.3 Crss 25 ˚C 0.6 0.9 VSD (V) 1.2 Tj = 25 °C and 150 °C; VGS = 0 V 10 10−1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 9397 750 14709 Product data sheet 1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 8 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 7. Package outline Plastic surface mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max. bp c D E e e1 HE Lp Q v w mm 1.1 0.9 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 1.9 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT23 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-09-13 04-11-04 TO-236AB Fig 14. Package outline SOT23 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 9 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 8. Revision history Table 6: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PMV117EN_2 20050407 Product data sheet - 9397 750 14709 PMV117EN-01 Modifications: PMV117EN-01 • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Table 5 “Characteristics”; correction to VGS(th) data Table 2 “Ordering information”: added 20030226 Product data - 9397 750 14709 Product data sheet 9397 750 11095 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 10 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 9. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14709 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 7 April 2005 11 of 12 PMV117EN Philips Semiconductors µTrenchMOS™ enhanced logic level FET 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 7 April 2005 Document number: 9397 750 14709 Published in The Netherlands