IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES QS59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK™ JR. FEATURES: • • • • • • DESCRIPTION: Eight zero delay outputs Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 25MHz to 85MHz CMOS outputs 3 skew grades: QS59920 -2: tSKEW0 <250ps QS59920 -5: tSKEW0 <500ps QS59920 -7: tSKEW0 <750ps 3-level input for PLL range control PLL bypass for DC testing External feedback, internal loop filter 46mA IOL high drive outputs Low Jitter: <200ps peak-to-peak Outputs drive 50Ω terminated lines Pin compatible with Cypress CY7B9920 Available in SOIC Package • • • • • • • • The QS59920 is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The QS59920 has CMOS outputs. The QS59920 maintains Cypress CY7B9920 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/ sOE pin is held low, all outputs are synchronously enabled (CY7B9920 compatibility). However, if GND/sOE is held high, all outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all outputs are synchronized with the positive edge of the REF clock input (CY7B9920 compatibility). When VDDQ/PE is held low, all outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FUNCTIONAL BLOCK DIAGRAM V DDQ /PE GND/sOE Q0 Q1 Q2 Q3 FB PLL REF Q4 Q5 FS Q6 Q7 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES MARCH 2000 1 c 1999 Integrated Device Technology, Inc. DSC-5813/- IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS REF 1 24 G ND V DD Q 2 23 TEST FS 3 22 NC NC 4 21 G ND/sO E V DDQ /PE 5 20 V DDN V D DN 6 19 Q7 Q0 7 18 Q6 Q1 8 17 G ND G ND 9 16 Q5 Q2 10 15 Q4 Q3 11 14 V DDN V D DN 12 13 FB SO24-2 (1) Symbol Rating Supply Voltage to Ground Max. –0.5 to +7 Unit V VI DC Input Voltage –0.5 to +7 V 530 mW Maximum Power Dissipation (T A = 85°C) TSTG Storage Temperature Range –65°C to +150°C °C NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = 25° C, f = 1MHz, VIN = 0V) Parameter CIN Description Input Capacitance Typ. Max. 5 7 Unit pF NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested. SOIC TOP VIEW PIN DESCRIPTION Pin Name Type Description REF IN Reference Clock Input FB IN Feedback Input TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. GND/ sOE (1) IN VDDQ/PE IN FS (2) IN Q 0 - Q7 OUT Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Frequency range select. 3 level input. FS = GND: 25 to 35MHz. FS = MID (or open): 35 to 60MHz FS = VDD: 60 to 85MHz 8 clock output VDDN PWR Power supply for output buffers VDDQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. 2 IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED OPERATING RANGE QS59920-5, -7 QS59920-2 (Industrial) (Commercial) Symbol VDD Description Power Supply Voltage Min. 4.5 Max. 5.5 Min. 4.75 Max. 5.25 Unit V TA Ambient Operating Temperature -40 +85 0 +70 °C DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIH VIL Parameter Input HIGH Voltage Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Min. VDD−1.35 Max. — Unit V Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 1.35 V (1) VIHH Input HIGH Voltage VIMM Input MID Voltage (1) (1) VILL Input LOW Voltage IIN Input Leakage Current (REF, FB Inputs Only) I3 3-Level Input DC Current (TEST, FS) 3-Level Inputs Only VDD−1 — V 3-Level Inputs Only VDD/2−0.5 VDD/2+0.5 V 3-Level Inputs Only — 1 V VIN = VDD or GND VDD = Max. VIN = VDD — ±5 µA — ±200 HIGH Level VIN = VDD/2 MID Level — ±50 VIN = GND LOW Level — ±200 µA VDD = Max., VIN = GND — ±100 µA IPU Input Pull-Up Current (VDDQ/PE) IPD Input Pull-Down Current (GND/sOE) VDD = Max., VIN = VDD — ±100 µA VOH Output HIGH Voltage VDD = Min., IOH = −16mA — — V VDD = Min., IOH = −40mA VDD−0.75 — V VOL Output LOW Voltage VDD = Min., IOL = 46mA — 0.45 V IOS Output Short Circuit Current (2) VDD = Max., VO = GND — N/A mA NOTES: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. QS59920 outputs are not to be shorted. POWER SUPPLY CHARACTERISTICS Symbol IDDQ Parameter Quiescent Power Supply Current ∆IDD IDDD ITOT Typ. 10 Max. 40 Unit mA Power Supply Current per Input HIGH Test Conditions VDD = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VDD = Max., VIN = 3.4V 0.4 1.5 mA Dynamic Power Supply Current per Output VDD = Max., CL = 0pF Total Power Supply Current 100 160 µA/MHz (1) 53 — mA VDD = 5V, FREF = 33MHz, CL = 240pF (1) 63 — mA (1) 117 — mA VDD = 5V, FREF = 25MHz, CL = 240pF VDD = 5V, FREF = 66MHz, CL = 240pF NOTE: 1. For eight outputs, each loaded with 30pF. 3 IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES INPUT TIMING REQUIREMENTS Symbol tR, tF Description (1) Maximum input rise and fall times, 0.8V to 2V Min. — Max. 10 Unit ns/V Input clock pulse, HIGH or LOW 3 — ns DH Input duty cycle 10 90 % REF Reference Clock Input 25 85 MHz tPWC NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. SWITCHING CHARACTERISTICS OVER OPERATING RANGE QS59920-2 Symbol FREF Parameter REF Frequency Range QS59920-5 QS59920-7 FS = LOW Min. 25 Typ. — Max. 35 Min. 25 Typ. — Max. 35 Min. 25 Typ. — Max. 35 FS = MID 35 — 60 35 — 60 35 — 60 FS = HIGH Unit MHz 60 — 85 60 — 85 60 — 85 tRPWH REF Pulse Width HIGH (1,7) 3 — — 3 — — 3 — — ns tRPWL REF Pulse Width LOW (1 7) 3 — — 3 — — 3 — — ns — 0.1 0.25 — 0.25 0.5 — 0.3 0.75 ns tSKEW Zero Output Skew (All Outputs) (1,3) (1,2,4) tDEV Device-to-Device Skew tPD REF Input to FB Propagation Delay (1,6) — — 0.75 — — 1.25 — — 1.65 ns −0.25 0 0.25 −0.5 0 0.5 −0.7 0 0.7 ns −1.2 0 1.2 −1.2 0 1.2 −1.5 0 1.5 ns 0.5 2 2.5 0.5 2 3.5 0.5 3 5 ns 0.5 2 2.5 0.5 2 3.5 0.5 3 5 ns — — 0.5 — — 0.5 — — 0.5 ms RMS — — 25 — — 25 — — 25 ps Peak-to-Peak — — 200 — — 200 — — 200 tODCV Output Duty Cycle Variation from 50% tORISE Output Rise Time (1) tOFALL Output Fall Time (1) (1) (1) tLOCK PLL Lock Time tJR Cycle-to-Cycle Output Jitter NOTES: 1. All timing tolerances apply for FNOM ≥25MHz. Guaranteed by design and characterization, not subject to production testing. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outputs. See AC Test Loads. 4. tDEV is the output-to-output skew between any two devices operating under the same conditions (V DD, ambient temperature, air flow, etc.) 5. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 6. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns. 7. Refer to Input Timing Requirements for more detail. 4 IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS AND WAVEFORMS ≤ 3 ns VDD ≤ 3ns VD D 80% Vth = 0.5V DD 100 Ω 20% 0V O utpu t 100 Ω CMOS INPUT TEST WAVEFORM CL C L = 50pF (C L = 30p F for -2 and -5 devices) TEST LOAD t OF AL L t O R ISE 0.8 V DD 0.2 V DD CMOS OUTPUT WAVEFORM AC TIMING DIAGRAM t R EF t RP W L t R PW H REF tP D t O D CV t O D CV FB t JR Q t SK E W t S K EW OTHER Q NOTES: Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with VDD/2. tSKEW: The skew between all outputs. tDEV: The output-to-output skew between any two devices operating under the same conditions (V DD, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. tORISE and tOFALL are measured between 0.2VDD and 0.8VDD. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 5 IDTCSP59920 LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION QS XXXXX XX Device Type Package X Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 C I Com mercial (0°C to +70°C) Industrial (-40°C to +85°C) SO Sm all Outline IC (300-m il) (SO24-2) 59920-2 59920-5 59920-7 Low Skew PLL Clock Driver TurboClock Jr. for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. Turboclock is a registered trademark of Integrated Device Technology, Inc. 6