ETC UC2572DTR

UC1572
UC2572
UC3572
Negative Output Flyback Pulse Width Modulator
FEATURES
DESCRIPTION
• Simple Single Inductor Flyback PWM
for Negative Voltage Generation
The UC3572 is a negative output flyback pulse width modulator which converts a positive input voltage to a regulated negative output voltage. The
chip is optimized for use in a single inductor negative flyback switching
converter employing an external PMOS switch. The block diagram consists
of a precision reference, an error amplifier configured for voltage mode operation, an oscillator, a PWM comparator with latching logic, and a 0.5A
peak gate driver. The UC3572 includes an undervoltage lockout circuit to
insure sufficient input supply voltage is present before any switching activity can occur, and a pulse-by-pulse current limit. Output current can be
sensed and limited to a user determined maximum value. The UVLO circuit
turns the chip off when the input voltage is below the UVLO threshold. In
addition, a sleep comparator interfaces to the UVLO circuit to turn the chip
off. This reduces the supply current to only 50µA, making the UC3572 ideal
for battery powered applications.
• Drives External PMOS Switch
• Contains UVLO Circuit
• Includes Pulse-by-Pulse Current Limit
• Low 50µA Sleep Mode Current
BLOCK DIAGRAM
UDG-94094-2
03/99
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UC1572
UC2572
UC3572
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC
IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
RAMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
CS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7A to 0.7A
I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (TOP VIEW)
D, N or J Packages
Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
ORDERING INFORMATION
UC1572
UC2572
UC3572
TEMPERATURE RANGE
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
PACKAGE
J
D, N or J
D or N
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
2.94
3
MAX UNITS
Reference Section
3VREF
3.06
V
Line Regulation
VCC = 4.75 to 30V
1
10
mV
Load Regulation
I3VREF = 0V to –5mA
1
10
mV
Oscillator Section
Frequency
VCC = 5V to 30V
85
100
115
kHz
EAOUT = 2V
–10
0
10
mV
Error Amp Section
EAINV
IEANV = –1mA
–0.2
–0.9
V
IEAINV
EAOUT = 2V
–0.2
–1.0
µA
AVOL
EAOUT = 0.5V to 3V
65
90
EAOUT High
EAINV = –100mV
3.6
4
4.4
EAOUT Low
EAINV = 100mV
0.1
0.2
IEAOUT
EAINV = –100mV, EAOUT = 2V
–350
–500
Unity Gain Bandwidth
TJ = 25°C, F = 10kHz
EAINV = 100mV, EAOUT = 2V
dB
V
V
µA
7
20
mA
0.6
1
MHz
0.195
0.215
0.235
V
–0.4
–1
µA
Current Sense Comparator Section
Threshold
Input Bias Current
CS = 0
CS Propogation Delay
300
nS
Gate Drive Output Section
OUT High Saturation
OUT Low Saturation
Rise Time
IOUT = 0
0
0.3
V
IOUT = –10mA
0.7
1.5
V
IOUT = –100mA
1.5
2.5
V
IOUT = 10mA
0.1
0.4
V
IOUT = 100mA
1.5
2.2
V
TJ = 25°C, CLOAD = 1nF + 3.3 Ohms
30
80
nS
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UC1572
UC2572
UC3572
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VCC = 5V, CT = 680pF, TA = TJ.
PARAMETER
Fall Time
TEST CONDITIONS
MIN
TYP
MAX UNITS
TJ = 25°C, CLOAD = 1nF + 3.3 Ohms
30
80
nS
Maximum Duty Cycle
EAINV = +100mV, VCC = 5V to 30V
92
96
%
Minimum Duty Cycle
EAINV = –100mV, VCC = 5V to 30V
0
%
Modulator Gain
EAOUT = 1.5V to 2.5V
65
%/V
Pulse Width Modulator Section
45
55
Undervoltage Lockout Section
Start Threshold
3.5
4.2
4.5
V
Hysteresis
100
200
300
mV
1.8
2.2
2.6
V
VCC = 5V, 30V
9
12
mA
VCC = 30, CS = 3V
50
150
µA
Sleep Mode Section
Threshold
Supply Current Section
IVCC
UDG-94095
Figure 1. Typical waveforms.
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UC1572
UC2572
UC3572
PIN DESCRIPTIONS
3VREF: Precision 3V reference. Bypass with 100nF capacitor to GND.
GND: Circuit Ground.
OUT: Gate drive for external PMOS switch connected
between VCC and the flyback inductor. OUT drives the
gate of the PMOS switch between VCC and GND.
CS: Current limit sense pin. Connect to a ground referenced current sense resistor in series with the flyback inductor. OUT will be held high (PMOS switch off) if CS
exceeds 0.2V.
RAMP: Oscillator and ramp for pulse width modulator.
Frequency is set by a capacitor to GND by the equation
EAINV: Inverting input to error amplifier. Summing junction for 3VREF and VOUT sense. The non-inverting input
of the error amplifier is internally connected to GND. This
pin will source a maximum of 1mA.
F=
1
15k • CRAMP
Recommended operating frequency range is 10kHz to
200kHz.
EAOUT: Output of error amplifier. Use EAOUT and
EAINV for loop compensation components.
VCC: Input voltage supply to chip. Range is 4.75 to 30V.
Bypass with a 1µF capacitor.
VIN
RSLEEP3
1MEG
SLEEP
MSLEEP
CVCC
10µF
C3V REF
100nF
CIN
10µF
UC1572
4
VCC
8
3VREF
7
RAMP
1
EAINV
2
EAOUT
6
GND
OUT
5
MSWITCH
CRAMP
680pF
RREF
RSLEEP1
56k
LFLYBACK
RCOMP
CCOMP
RSLEEP2
33k
CS
DFLYBACK
3
RCS
GND
GND
COUT
100µF
RV SENSE
40k
–12V OUT
VOUT
UDG-99057
Figure 2. Typical application: +5V to –12V flyback converter.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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