ETC UC3725N

UC1725
UC2725
UC3725
Isolated High Side FET Driver
FEATURES
DESCRIPTION
•
Receives Both Power and Signal Across
the Isolation Boundary
•
9 to 15 Volt High Level Gate Drive
•
Under-voltage Lockout
The UC1725 and its companion chip, the UC1724, provide all the necessary features to drive an isolated MOSFET transistor from a TTL input signal. A unique modulation scheme is used to transmit both power
and signals across an isolation boundary with a minimum of external
components.
•
Programmable Over-current Shutdown
and Restart
•
Output Enable Function
Protection circuitry, including under-voltage lockout, over-current shutdown, and gate voltage clamping provide fault protection for the MOSFET. High level gate drive is guaranteed to be greater than 9 volts and
less than 15 volts under all conditions.
Uses include isolated off-line full bridge and half bridge drives for driving motors, switches, and any other load requiring full electrical isolation.
The UC1725 is characterized for operation over the full military temperature range of -55°C to +125°C while the UC2725 and UC3725 are
characterized for -25°C to +85°C and 0°C to +70°C respectively.
BLOCK DIAGRAM
UDG-92051-1
1/94
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UC1725
UC2725
UC3725
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Power inputs (pins 7 & 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output current, source or sink (pin 2)
DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5 us) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Enable and Current limit inputs (pins 4 & 6). . . . . . . . -0.3 to 6V
Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W
Power Dissipation at TA ≤ 25°C (SO-14) . . . . . . . . . . . . 725mW
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
PLCC-20 (Top View)
Q Package
Note 1: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the specified terminals (pin numbers refer to DIL-8 package).
Note 2: See Unitrode Integrated Circuits databook for
information regarding thermal specifications and limitations of
packages.
DIL-8 (Top View)
J Or N Package
SOIC-16 (Top View)
DW Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
ISENSE
N/C
Timing
Enable
N/C
Input A
N/C
Input B
Gnd
VCC
N/C
Output
1
2
3-5
6
7
8-9
11
12-14
15
16
17
18-19
20
DIL-16 (Top View)
JE Or NE Package
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for
UC1725; -25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) =
0 to 15V, RT=10k, CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER INPUT SECTION (PINS 7 & 8)
Forward Diode Drop, Schottky Rectifier
IF = 50ma
.55
.7
V
IF = 500ma
1.1
1.5
V
Input bias current
VPIN4 = OV
-1
-10
µA
Threshold voltage
Delay to outputs
VPIN4 = 0 to 1V
CURRENT LIMIT SECTION (PIN 4)
0.4
0.5
0.6
V
100
250
ns
TIMING SECTION (PIN 5)
Output Off Time
27
30
33
µs
Upper Mono Threshold
6.3
7.0
7.7
V
Lower Mono Threshold
1.9
2.0
2.3
V
7.0
Vcc/2
8.0
V
HYSTERESIS AMPLIFIER (PINS 7 & 8)
Input Open Circuit Voltage
Inputs (pins 7 & 8), Open Circuited, TA= 25°C
Input Impedance
TA = 25°C
Hysteresis
Delay to Outputs
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VPIN7 - VPIN8 = VCC + 1V
2
23
28
33
kΩ
26.5
2*Vcc
100
30.5
V
300
ns
UC1725
UC2725
UC3725
ELECTRICAL
CHARACTERISTICS (cont.)
(Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for UC1725;
-25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) = 0 to 15V, Rt=10k,
CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
PARAMETER
ENABLE SECTION (PIN 6)
TEST CONDITIONS
High Level Input Voltage
MIN
2.1
TYP
MAX
UNITS
1.4
V
Low Level Input Voltage
1.4
.8
V
Input Bias Current
-250
-500
µA
OUTPUT SECTION
Output Low Level
Output High Level
Rise/Fall Time
IOUT = 20mA
0.35
0.5
V
IOUT = 200mA
0.6
2.5
V
IOUT = -20mA
IOUT = -200mA
13
12
13.5
13.4
V
V
VCC = 30V, Iout = -20mA
14
15
V
CT = 1nf
30
60
ns
20mA, VCC = 8V
0.8
1.5
V
UNDER VOLTAGE LOCKOUT
UVLO Low Saturation
Start-up Threshold
11.2
12
12.6
V
Threshold Hysteresis
.75
1.0
1.12
V
12
16
ma
TOTAL STANDBY CURRENT
Supply Current
APPLICATION AND OPERATION INFORMATION
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis amplifier as shown in Figure 3.
INPUTS: Figure 1 shows the rectification and detection
scheme used in the UC1725 to derive both power and
signal information from the input waveform. Vcc is generated by peak detecting the input signal via the internal
bridge rectifier and storing on a small external capacitor,
C1. Note that this capacitor is also used to bypass high
pulse currents in the output stage, and therefore should
be placed direclty between pins 1 and 3 using minimal
lead lengths.
UDG-92048
FIGURE 2 - Input Waveform (DIL-8 Pin 7 - Pin 8)
UDG-92047
FIGURE 1 - Input Stage
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting
(resetting) the comparator only if the input signal exceeds Vcc (-Vcc). In some cases it may be necessary to
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UDG-92049
FIGURE 3 - Signal Detection
3
UC1725
UC2725
UC3725
capacitor and resistor as shown in Figure 4. This, in turn,
controls the output off time according to the formula:
TOFF= 1.28 • RC.
If current limit feature is not required, simply ground pin 4
and leave pin 5 open.
OUTPUT: Gate drive to the power FET is provided by a
totem pole output stage capable of sourcing and sinking
currents in excess of 1 amp. The undervoltage lockout
circuit guarantees that the high level output will never be
less than 9 volts. In addition, during undervoltage lockout, the output stage will actively sink current to eliminate
the need for an external gate to source resistor. High
level output is also clamped to 15 volts. Under high capacitive loading however, the output may overshoot 2 to
3 volts, due to the drivers’ inabitlity to switch from full to
zero output current instantaneously. In a practical circuit
this is not normally a concern. A few ohms of series gate
resistance is normally required to prevent parasitic oscillations, and will also eliminate overshoot at the gate.
UDG-92050
FIGURE 4 - Current Limit
CURRENT LIMIT AND TIMING: Current sensing and
shutdown can be implemented directly at the output using the scheme shown in Figure 4. Alternatively, a current
transformer can be used in place of RSENSE. A small RC
filter in series with the input (pin 4) is generally needed to
eliminate the leading edge current spike caused by
parasitic circuit capacitances being charged during turn
on. Due to the speed of the current sense circuit, it is
very important to ground CF directly to Gnd as shown to
eliminate false triggering of the one shot caused by
ground drops.
ENABLE: An enable pin is provided as a fast, digital input that can be used in a number of applications to directly switch the output. Figure 6 shows a simple means
of providing a fast, high voltage translation by using a
small signal, high voltage transistor in a cascode configuration. Note that the UC1725 is still used to provide
power, drive and protection circuitry for the power FET.
One shot timing is easily programmed using an external
UDG-92052
UDG-92053
FIGURE 6 - Using Enable Pin as a High Speed Input
Path
FIGURE 5 - Output Circuit
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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4
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