UCC1946 UCC2946 UCC3946 Microprocessor Supervisor with Watchdog Timer FEATURES DESCRIPTION • Fully Programmable Reset Threshold • Fully Programmable Reset Period • Fully Programmable Watchdog Period • 2% Accurate Reset Threshold • VDD Can Go as Low as 2V • 18µA Maximum IDD • Reset Valid Down to 1V The UCC3946 is designed to provide accurate microprocessor supervision, including reset and watchdog functions. During power up, the IC asserts a reset signal RES with VDD as low as 1V. The reset signal remains asserted until the VDD voltage rises and remains above the reset threshold for the reset period. Both reset threshold and reset period are programmable by the user. The IC is also resistant to glitches on the VDD line. Once RES has been deasserted, any drops below the threshold voltage need to be of certain time duration and voltage magnitude to generate a reset signal. These values are shown in Figure 1. An I/O line of the microprocessor may be tied to the watchdog input (WDI) for watchdog functions. If the I/O line is not toggled within a set watchdog period, programmable by the user, WDO will be asserted. The watchdog function will be disabled during reset conditions. The UCC3946 is available in 8-pin SOIC(D), 8-pin DIP (N or J) and 8-pin TSSOP(PW) packages to optimize board space. BLOCK DIAGRAM VDD 8 400nA RP POWER TO CIRCUITRY 4 1.235V RTH . 3 RES 5 WDO 2 POWER ON RESET 400nA 8-BIT COUNTER WP 6 A3 A2 100mV CLR A1 A0 CLK 1.235V WATCHDOG TIMING WDI 7 EDGE DETECT 1 GND Note: Pinout represents the 8-pin TSSOP package. SLUS247A - SEPTEMBER 1999 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UDG-98001 UCC1946 UCC2946 UCC3946 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAM VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. SOIC-8, TSSOP-8, DIL-8 (Top View) D, PW, N or J Package GND 1 8 VDD RTH 2 7 WDI RES 3 6 WP RP 4 5 WDO ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 2.1V to 5.5V for UCC1946 and UCC2946; VDD = 2V to 5.5V for UCC3946; TA = 0°C to 70°C for UCC3946, –40°C to 85°C for UCC2946, and –55°C to 125°C for UCC1946; T A = TJ PARAMETERS TEST CONDITIONS MIN TYP MAX UCC3946 Operating Voltage 2.0 Supply Current Minimum VDD (Note 1) TYP MAX UNITS UCC1946 & UCC2946 5.5 10 MIN 2.1 18 12 1 5.5 V 18 µA 1.1 V 1.260 V Reset Section Reset Threshold VDD Rising 1.210 Threshold Hysteresis 1.235 Output Low Voltage 1.170 15 Input Leakage Output High Voltage 1.260 1.235 15 5 ISOURCE = 2mA VDD – 0.3 mV 5 VDD – 0.3 nA V ISINK = 2mA 0.1 0.1 V VDD = 1V, ISINK = 20uA 0.2 0.4 V 320 ms VDD to Output Delay VDD = -1mV/µs (Note 2) Reset Period CRES = 64nF 120 160 200 µs 120 260 140 200 Watchdog Section WDI Input High 0.7· VDD 0.7· VDD WDI Input Low Watchdog Period V 0.3· VDD CWD = 64nF 1.12 Watchdog Pulse Width Output High Voltage ISOURCE = 2mA Output Low Voltage ISINK = 2mA 2.08 1.60 2.56 s 50 50 ns VDD – 0.3 V 0.1 2 0.96 V VDD – 0.3 Note 1: This is the minimum supply voltage where RES is considered valid. Note 2: Guaranteed by design. Not 100% tested in production. Powered by ICminer.com Electronic-Library Service CopyRight 2003 1.60 0.3· VDD 0.1 V UCC1946 UCC2946 UCC3946 PIN DESCRIPTIONS GND: Ground reference for the IC. VDD: Supply voltage for the IC. RES: This pin is high only if the voltage on the RTH has risen above 1.235V. Once RTH rises above the threshold, this pin remains low for the reset period. This pin will also go low and remain low if the RTH voltage dips below 1.235V for an amount of time determined by Figure 1. WDI: This pin is the input to the watchdog timer. If this pin is not toggled or strobed within the watchdog period, WDO is asserted. RTH: This input compares its voltage to an internal 1.25V reference. By using external resistors, a user can program any reset threshold he wishes to achieve. WDO: This pin is the watchdog output. This pin will be asserted low if the WDI pin is not strobed or toggled within the watchdog period. WP: This pin allows the user to program the watchdog period by adjusting an external capacitor. RP: This pin allows the user to program the reset period by adjusting an external capacitor. APPLICATION INFORMATION The UCC3946 supervisory circuit provides accurate reset and watchdog functions for a variety of microprocessor applications. The reset circuit prevents the microprocessor from executing code during undervoltage conditions, typically during power-up and power-down. In order to prevent erratic operation in the presence of noise, voltage “glitches” whose voltage amplitude and time duration are less than the values specified in Fig. 1 are ignored. Programming the Reset Voltage and Reset Period The watchdog circuit monitors the microprocessor’s activity, if the microprocessor does not toggle WDI during the programmable watchdog period WDO will go low, alerting the microprocessor’s interrupt of a fault. The WDO pin is typically connected to the non-maskable input of the microprocessor so that an error recovery routine can be executed. Figure 2. Typical RTH threshold vs. temperature. 180 160 140 12.5 120 12 100 11.5 IDD (uA) OVERDRIVE VOLTAGE WITH RESPECT TO RESET THRESHOLD (mV) 200 RT SENSES GLITCH, RES GOES LOW FOR RESET PERIOD 80 60 11 10.5 40 20 10 GLITCHES ARE IGNORED, RESB REMAINS HIGH 9.5 0 100 110 120 130 140 150 160 170 180 9 DELAY (µS) 2 Figure 1. Overdrive voltage vs. delay to output low on RESB. Slew rate: –1V/mS; monitored voltage = VDD. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 4 VDD (V) Figure 3. Typical IDD vs VDD. 3 5 UCC1946 UCC2946 UCC3946 APPLICATION INFORMATION (cont.) VDD 8 400nA POWER TO CIRCUITRY RP 4 CRP VDD RES 1.235V R1 3 RESET RTH 2 POWER ON RESET R2 400nA uP WP I/O 8-BIT COUNTER 6 A3 CWP WDO A2 100mV CLR 5 A1 NMI A0 CLK 1.235V WATCHDOG TIMING WDI 7 EDGE DETECT GND 1 UDG-98002 Note: Pinout represents the 8-pin TSSOP package. Figure 4. Typical application diagram. The UCC3946 allows the reset trip voltage to be programmed with two external resistors. In most applications VDD is monitored by the reset circuit, however, the design allows voltages other than VDD to be monitored. Referring to Fig. 4, the voltage below which reset will be asserted is determined by: VRESET = 1.235 • R1 + R2 R2 In order to keep quiescent currents low, resistor values in the megaohm range can be used for R1 and R2. A manual reset can be easily implemented by connecting a momentary push switch in parallel with R2. RES is guaranteed to be low with VDD voltages as low as 1V. Once VDD rises above the programmed threshold, RES remains low for the reset period defined by: TRP = 3 .125 • CRP where TRP is time in milliseconds and CRP is capacitance in nanofarads. CRP is charged with a precision current source of 400nA, a high quality, low leakage capacitor Powered by ICminer.com Electronic-Library Service CopyRight 2003 (such as an NPO ceramic) should be used to maintain timing tolerances. Fig. 5 illustrates the voltage levels and timings associated with the reset circuit. Programming the Watchdog Period The watchdog period is programmed with CWP as follows: TWP = 25 • CWP where TWP is in milliseconds and CWP is in nanofarads. A high quality, low leakage capacitor should be used for CWP. The watchdog input WDI must be toggled with a high/low or low/high transition within the watchdog period to prevent WDO from assuming a logic level low. WDO will maintain the low logic level until WDI is toggled or RES is asserted. If at any time RES is asserted, WDO will assume a high logic state and the watchdog period will be reinitiated. Fig. 6 illustrates the timings associated with the watchdog circuit. Connecting WDO to RES 4 UCC1946 UCC2946 UCC3946 APPLICATION INFORMATION (cont.) In order to provide design flexibility, the reset and watchdog circuits in the UCC3946 have separate outputs. Each output will independently drive high or low, depending on circuit conditions explained previously. In some applications, it may be desirable for either the RES or WDO to reset the microprocessor. This can be done by connecting WDO to RES. If the pins try to drive to different output levels, the low output level will dominate. Additional current will flow from VDD to GND during these states. If the application cannot support additional current (during fault conditions), RES and WDO can be connected to the inputs of an OR gate whose output is connected to the microprocessor’s reset pin. A 0.1µF capacitor connected from VDD to GND is recommended to decouple the UCC3946 from switching transients on the VDD supply rail. Since RP and WP are precision current sources, capacitors CRP and CWP should be connected to these pins with minimal trace length to reduce board capacitance. Care should be taken to route any traces with high voltage potential or high speed digital signals away from these capacitors. Resistors R1 and R2 generally have a high ohmic value, traces associated with these parts should be kept short in order to prevent any transient producing signals from coupling into the high impedance RTH pin. Layout Considerations UDG-97067 t1: VDD > 1V, RES is guaranteed low. t2: VDD > programmed threshold, RES remains low for TRP. t3: TRP expires, RES pulls high. t4: Voltage glitch occurs, but is filtered at the RTH pin, RES remains high. t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, RES is asserted for TRP. t6: VDD dips below threshold (minus hysteresis), RES is asserted. Figure 5. Reset circuit timings. Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 UCC1946 UCC2946 UCC3946 APPLICATION INFORMATION (cont.) TRP VDD RESET 0V TWP VDD WDI 0V VDD WDO 0V t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 UDG-98007 t1: Microprocessor is reset. t7: WDI is toggled before TWP expires. t2: WDI is toggled some time after reset, but before TWP expires. t8: WDI is toggled before TWP expires. t3: WDI is toggled before TWP expires. t9: RES is momentarily triggered, RES is asserted low for TRP. t4: WDI is toggled before TWP expires. t10: Microprocessor is reset, RES pulls high. t5: WDI is not toggled before TWP expires and WDO asserts low, triggering the microprocessor to enter an error recovery routine. t11: WDI is toggled some time after reset, but before TWP expires. t6: The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog timer. t13: WDI is toggled before TWP expires. t12: WDI is toggled before TWP expires. t14: VDD dips below the reset threshold, RES is asserted. Figure 6. Watchdog circuit timings. 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