a 16-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode AD5516* FEATURES High Integration: 16-Channel DAC in 12 mm ⴛ 12 mm LFBGA 14-Bit Resolution via Increment/Decrement Mode Guaranteed Monotonic Low Power, SPITM, QSPITM, MICROWIRE TM, and DSPCompatible 3-Wire Serial Interface Output Impedance 0.5 ⍀ Output Voltage Range ⴞ2.5 V (AD5516-1) ⴞ5 V (AD5516-2) ⴞ10 V (AD5516-3) Asynchronous Reset-Facility (via RESET Pin) Asynchronous Power-Down Facility (via PD Pin) Daisy-Chain Mode Temperature Range: –40ⴗC to +85ⴗC APPLICATIONS Level Setting Instrumentation Automatic Test Equipment Optical Networks Industrial Control Systems Data Acquisition Low Cost I/O GENERAL DESCRIPTION The AD5516 is a 16-channel, 12-bit voltage-output DAC. The selected DAC register is written to via the 3-wire serial interface. DAC selection is accomplished via address bits A3–A0. 14-bit resolution can be achieved by fine adjustment in Increment/ Decrement Mode (Mode 2). The serial interface operates at clock rates up to 20 MHz and is compatible with standard SPI, MICROWIRE, and DSP interface standards. The output voltage range is fixed at ± 2.5 V (AD5516-1), ± 5 V (AD5516-2), and ± 10 V (AD5516-3). Access to the feedback resistor in each channel is provided via RFB0 to RFB15 pins. The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to 5.25 V, VSS = –4.75 V to –12 V, and VDD = +4.75 V to +12 V and requires a stable 3 V reference on REF_IN. PRODUCT HIGHLIGHTS 1. Sixteen 12-bit DACs in one package, guaranteed monotonic 2. Available in a 74-lead LFBGA package with a body size of 12 mm ⴛ 12 mm FUNCTIONAL BLOCK DIAGRAM DVCC AVCC VDD REF_IN VBIAS VSS ROFFS R FB AD5516 VOUT0 DAC RESET ROFFS BUSY ANALOG CALIBRATION LOOP R FB DAC ROFFS R FB MODE1 ROFFS INTERFACE CONTROL LOGIC SCLK DIN MODE2 7-BIT BUS DOUT SYNC R FB RFB15 VOUT15 DAC DCEN RFB 14 VOUT14 DAC 12-BIT BUS DGND RFB1 VOUT1 DACGND AGND RFB0 POWER-DOWN LOGIC PD *Protected by U.S. Patent No. 5,969,657; other patents pending SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = AD5516 –SPECIFICATIONS 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications T to T unless otherwise noted.) MIN MAX Parameter1 A Version2 Unit DAC DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Increment/Decrement Step-Size Bipolar Zero Error Positive Full-Scale Error Negative Full-Scale Error 12 ±2 –1/+1.3 ± 0.25 ±7 ± 10 ± 10 Bits LSB max LSB max LSB typ LSB max LSB max LSB max VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range3 Input Current 3 2.875/3.125 ±1 V V min/max µA max 10 0.5 ppm/°C typ Ω typ ± 2.5 ±5 ± 10 5 200 7 –85 120 V typ V typ V typ kΩ min pF mA typ dB typ µV max ± 10 0.8 0.4 2.4 2 150 10 µA max V max V max V min V min mV typ pF max 5 pF typ 0.4 4 0.4 2.4 ±1 5 V max V min V max V min µA max pF typ Sinking 200 µA Sourcing 200 µA Sinking 200 µA Sourcing 200 µA DCEN = 0 DCEN = 0 +4.75/+15.75 –4.75/–15.75 4.75/5.25 2.7/5.25 V min/max V min/max V min/max V min/max 5 5 17 1.5 mA max mA max mA max mA max 3.5 mA typ. All Channels Full-Scale 3.5 mA typ. All Channels Full-Scale 13 mA typ 1 mA typ 2 3 2 2 105 µA max µA max µA max µA max mW typ 200 nA typ 200 nA typ 200 nA typ 200 nA typ VDD = +5 V, VSS = –5 V ANALOG OUTPUTS (VOUT 0–15) Output Temperature Coefficient3, 4 DC Output Impedance3 Output Range5 AD5516-1 AD5516-2 AD5516-3 Resistive Load3, 6 Capacitive Load3, 6 Short-Circuit Current3 DC Power-Supply Rejection Ratio3 DC Crosstalk3 DIGITAL INPUTS3 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and SYNC) Input Capacitance Conditions/Comments Mode 1 ± 0.5 LSB typ, Monotonic; Mode 1 Monotonic; Mode 2 Only < 1 nA typ of FSR VDD = +12 V ± 5%, VSS = –12 V ± 5% ± 5 µA typ DVCC = 5 V ± DVCC = 3 V ± DVCC = 5 V ± DVCC = 3 V ± 5% 10% 5% 10% 3 DIGITAL OUTPUTS (BUSY, DOUT) Output Low Voltage, DVCC = 5 V Output High Voltage, DVCC = 5 V Output Low Voltage, DVCC = 3 V Output High Voltage, DVCC = 3 V High Impedance Leakage Current (DOUT only) High Impedance Output Capacitance (DOUT only) POWER REQUIREMENTS Power Supply Voltages VDD VSS AVCC DVCC Power Supply Currents7 IDD ISS AICC DICC Power-Down Currents7 IDD ISS AICC DICC Power Dissipation7 NOTES 1 See Terminology section. 2 A Version: Industrial temperature range –40°C to +85°C; typical at +25°C. 3 Guaranteed by design and characterization; not production tested. 4 AD780 as reference for the AD5516. 5 Output range is restricted from V SS + 2 V to VDD – 2 V. Output span varies with reference voltage and is functional down to 2 V. 6 Ensure that you do not exceed T J (MAX). See Absolute Maximum Ratings section. 7 Outputs unloaded. Specifications subject to change without notice. –2– REV. 0 AD5516 (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND MIN to TMAX unless otherwise noted.) AC CHARACTERISTICS = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications T Parameter1, 2 4 Output Voltage Settling Time (Mode 1) Output Voltage Settling Time (Mode 2)4 Slew Rate Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk AD5516-1 Digital Feedthrough Output Noise Spectral Density @ 1 kHz A Version3 Unit Conditions/Comments 32 2.5 0.85 1 5 10 1 150 s max s max V/s typ nV-s typ nV-s typ nV-s typ nV-s typ nV/(Hz)1/2 typ 100 pF, 5 kΩ Load Full-Scale Change 100 pF, 5 kΩ Load, 1 Code Increment 1 LSB Change around Major Carry AD5516-1 NOTES 1 See Terminology section. 2 Guaranteed by design and characterization; not production tested. 3 A version: Industrial temperature range –40°C to +85°C. 4 Timed from the end of a write sequence. Specifications subject to change without notice. TIMING CHARACTERISTICS (VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V. All specifications TMIN to TMAX unless otherwise noted.) Parameter1, 2, 3 Limit at TMIN, TMAX (A Version) Unit Conditions/Comments fUPDATE1 fUPDATE2 fCLKIN t1 t2 t3 t4 t5 t6 t7 t7MODE2 t8MODE1 t9MODE2 t10 t114 t12 32 750 20 20 20 15 5 5 0 10 400 10 200 10 20 20 kHz max kHz max MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min DAC Update Rate (Mode 1) DAC Update Rate (Mode 2) SCLK Frequency SCLK High Pulsewidth SCLK Low Pulsewidth SYNC Falling Edge to SCLK Falling Edge Setup Time DIN Setup Time DIN Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time (Standalone Mode) Minimum SYNC High Time (Daisy-Chain Mode) BUSY Rising Edge to SYNC Falling Edge 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode) SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode) SCLK Rising Edge to DOUT Valid (Daisy-Chain Mode) RESET Pulsewidth NOTES 1 See Timing Diagrams in Figures 1 and 2. 2 Guaranteed by design and characterization; not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DV CC) and timed from a voltage level of (V IL + VIH)/2. 4 This is measured with the load circuit of Figure 3. Specifications subject to change without notice. –3– AD5516 SERIAL INTERFACE TIMING DIAGRAMS SCLK 1 2 17 t3 t2 18 t1 t6 t7 SYNC t9 MODE2 t4 t5 MSB DIN LSB BIT 17 BIT 0 t8 MODE1 BUSY t12 RESET Figure 1. Serial Interface Timing Diagram SCLK t3 t7 MODE2 t2 t1 t10 t6 SYNC t4 MSB DIN t5 LSB BIT 17 BIT 0 BIT 17 INPUT WORD FOR DEVICE N BIT 0 INPUT WORD FOR DEVICE N+1 t11 DOUT BIT 17 t8 MODE1 UNDEFINED BIT 0 INPUT WORD FOR DEVICE N BUSY Figure 2. Daisy-Chaining Timing Diagram 200A TO OUTPUT PIN IOL 1.6V CL 50pF 200A IOH Figure 3. Load Circuit for DOUT Timing Specifications –4– REV. 0 AD5516 ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C unless otherwise noted.) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V AVCC to AGND, DACGND . . . . . . . . . . . . . . –0.3 V to +7 V DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V REF_IN to AGND, DACGND . . . . . –0.3 V to AVCC + 0.3 V VOUT 0–15 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V RFB 0–15 to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Operating Temperature Range, Industrial . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . . 150°C 74-Lead LFBGA Package, JA Thermal Impedance . . 41°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model Function Output Voltage Span Package Option AD5516ABC-1 AD5516ABC-2 AD5516ABC-3 16 DACs 16 DACs 16 DACs ± 2.5 V ±5 V ± 10 V 74-Lead LFBGA 74-Lead LFBGA 74-Lead LFBGA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD5516 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E TOP VIEW F F G G H H J J K L K L 1 2 3 4 5 6 7 8 9 10 11 74-LEAD LFBGA BALL CONFIGURATION LFBGA Number Ball Name LFBGA Number Ball Name LFBGA Number Ball Name LFBGA Number Ball Name LFBGA Number Ball Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 NC NC RESET BUSY DGND DVCC DOUT DIN SYNC NC NC NC NC NC DCEN B5 B6 B7 B8 B9 B10 B11 C1 C2 C6 C10 C11 D1 D2 D10 DGND DGND NC NC SCLK NC REF_IN VOUT0 DACGND NC AVCC1 NC RFB0 DACGND AVCC2 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 NC VOUT1 NC AGND1 PD VOUT2 R FB1 AGND2 RFB14 RFB2 RFB15 VOUT14 RFB13 VOUT3 VOUT15 H10 H11 J1 J2 J6 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 VOUT13 VOUT12 RFB3 VOUT14 NC RFB12 RFB11 RFB4 VOUT5 RFB5 NC VSS2 VSS1 VOUT10 VOUT9 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 RFB10 RFB9 VOUT11 NC VOUT6 RFB6 VOUT7 NC VDD2 VDD1 RFB7 VOUT8 RFB8 NC NC = Not Internally Connected PIN FUNCTION DESCRIPTIONS Mnemonic Function AGND (1–2) AVCC (1–2) VDD (1–2) VSS (1–2) DGND DVCC DACGND REF_IN VOUT (0–15) RFB (0–15) SYNC Analog GND pins Analog supply pins. Voltage range from +4.75 V to +5.25 V. VDD supply pins. Voltage range from +4.75 V to +15.75 V. VSS supply pins. Voltage range from –4.75 V to –15.75 V. Digital GND pins Digital supply pin. Voltage range from 2.7 V to 5.25 V. Reference GND supply for all 16 DACs. Reference input voltage for all 16 DACs. The recommended value of REF_IN is 3 V. Analog output voltages from the 16 DAC channels. Feedback resistors. For nominal output voltage range connect each RFB to its corresponding VOUT. Active low input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial clock input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 20 MHz. Serial data input. Data must be valid on the falling edge of SCLK. SCLK DIN –6– REV. 0 AD5516 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Function DOUT Serial data output. DOUT can be used for daisy-chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes. Data is clocked out on DOUT on the rising edge of SCLK and is valid on the falling edge of SCLK. Active high control input. This pin is tied high to enable daisy-chain mode. Active low control input. This resets all DAC registers to power-on value. Active high control input. All DACs go into power-down mode when this pin is high. The DAC outputs go into a high-impedance state. Active low output. This signal tells the user that the analog calibration loop is active. It goes low during conversion. The duration of the pulse on BUSY determines the maximum DAC update rate, fUPDATE. Further writes to the AD5516 are ignored while BUSY is active. DCEN1 RESET2 PD1 BUSY NOTES 1 Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition. 2 Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition. TERMINOLOGY Integral Nonlinearity (INL) This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of –1 LSB maximum ensures monotonicity. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in mV. Output Settling Time This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within ± 0.5 LSB of its final value (see TPC 7). Digital-to-Analog Glitch Impulse Bipolar zero error is the deviation of the DAC output from the ideal midscale of 0 V. It is measured with 10...00 loaded to the DAC. It is expressed in LSBs. This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011...11 to 100...00 or 100...00 to 011...11). Positive Full-Scale Error Digital Crosstalk This is the error in the DAC output voltage with all 1s loaded to the DAC. Ideally the DAC output voltage, with all 1s loaded to the DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB (AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs. This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs. Negative Full-Scale Error This is the area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-secs. Bipolar Zero Error This is the error in the DAC output voltage with all 0s loaded to the DAC. Ideally the DAC output voltage, with all 0s loaded to the DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2), and –10 V (AD5516-3). It is expressed in LSBs. Output Temperature Coefficient This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/°C of FSR. DC Power Supply Rejection Ratio DC power supply rejection ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dBs. VDD and VSS are varied ± 5%. REV. 0 Analog Crosstalk Digital Feedthrough This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., SYNC is high. It is specified in nV-secs and measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured in nV/(Hz)1/2. –7– AD5516 –Typical Performance Characteristics 1.0 REF_IN = 3V 0.8 TA = 25ⴗC 1.0 2.0 REF_IN = 3V 0.8 TA = 25ⴗC 1.5 0.6 0.6 0.4 0.4 REF_IN = 3V 0.2 0 –0.2 –0.4 ERROR – LSB INL ERROR – LSB DNL ERROR – LSB 1.0 0.2 0 –0.2 INL 0.5 +VE DNL 0 –0.5 –VE DNL –0.4 –1.0 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 1000 2000 3000 DAC CODE 4000 –1.5 0 1000 –2.0 –40 4000 3 –1 0.006 0 MIDSCALE –0.006 –0.002 POSITIVE FS ERROR –20 0 20 40 0.0 –0.004 NEGATIVE FS ERROR –3 –40 0.002 –0.002 –0.001 –2 –0.008 60 80 –0.003 –40 TEMPERATURE – ⴗC –20 0 20 40 60 80 –0.01 –8 –6 –4 TEMPERATURE – ⴗC TPC 5. VOUT vs. Temperature TPC 4. Bipolar Zero Error and Full-Scale Error vs. Temperature 3.0 –2 0 2 CURRENT – mA 4 6 8 TPC 6. VOUT Source and Sink Capability –0.029 TA = 25ⴗC REF_IN = 3V TA = 25ⴗC REF_IN = 3V 2.0 TA = 25ⴗC REF_IN = 3V NEW VALUE –0.030 1.0 VOUT – V 80 0.004 VOUT – V VOUT – V 0 60 40 REF_IN = 3V TA = 25ⴗC 0.008 0.001 BIPOLAR ZERO ERROR 20 0.01 AVDD = +12V AVSS = –12V REF_IN = 3V MIDSCALE LOADED 0.002 1 0 TPC 3. Typical INL Error and DNL Error vs. Temperature 0.003 REF_IN = 3V 2 –20 TEMPERATURE – ⴗC TPC 2. Typical INL Plot TPC 1. Typical DNL Plot ERROR – LSB 2000 3000 DAC CODE PD 5V/DIV VOUT 2V/DIV CALIBRATION TIME 0 –0.031 OLD VALUE –1.0 TIME BASE = 2.5s/DIV 2s/DIV 2.5s/DIV –0.032 –2.0 5V 0V –3.0 TPC 7. Full-Scale Settling Time –0.033 TPC 8. Exiting Power-Down to Full Scale –8– BUSY TPC 9. Major Code Transition Glitch Impulse REV. 0 AD5516 450 40 40 REF_IN = 3V TA = 25ⴗC REF_IN = 3V TA = 25ⴗC 400 300 250 200 150 FREQUENCY – % FREQUENCY – % FREQUENCY 350 20 20 100 50 0 2.4893 2.4896 VOUT – V 2.4899 TPC 10. VOUT Repeatability; Programming the Same Code Multiple Times 0 –10 0 LSBs 0 –10 10 TPC 11. Bipolar Error Distribution 30 0 LSBs 10 TPC 12. Positive Full-Scale Error Distribution 2.5 REF_IN = 3V TA = 25ⴗC REF_IN = 3V TA = 25ⴗC 20 ERROR – LSB FREQUENCY – % 2.0 10 1.5 1.0 0.5 0 –10 0 0 LSBs 10 0 TPC 13. Negative Full-Scale Error Distribution REV. 0 20 40 60 80 STEP SIZE 100 120 130 TPC 14. Increment Step vs. Accuracy –9– AD5516 Table I illustrates ideal analog output versus DAC code. FUNCTIONAL DESCRIPTION The AD5516 consists of sixteen 12-bit DACs in a single package. A single reference input pin (REF_IN) is used to provide a 3 V reference for all 16 DACs. To update a DAC’s output voltage the required DAC is addressed via the 3-wire serial interface. Once the serial write is complete, the selected DAC converts the code into an output voltage. The output amplifiers translate the DAC output range to give the appropriate voltage range (± 2.5 V, ± 5 V, or ± 10 V) at output pins VOUT0 to VOUT15. The AD5516 uses a self-calibrating architecture to achieve 12-bit performance. The calibration routine servos to select the appropriate voltage level on an internal 14-bit resolution DAC. Noise during the calibration (BUSY low period) can result in the selection of a voltage within a ± 0.25 LSB band around the normal selected voltage. See TPC 10. AD5516-2 VDAC = AD5516-3 VDAC = 4 × VREF _ IN × 2.5 × D 3×2 N 8 × VREF _ IN × 2.5 × D 3 × 2N VREF _ IN × 2.5 3 – 2 VREF _ IN × 2.5 3 – 4 VREF _ IN × 2.5 3 VREF_IN × 2.5/3 – 1 LSB 0V –VREF_IN × 2.5/3 1111 1111 1111 1000 0000 0000 0000 0000 0000 Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the user to increment or decrement the DAC output in 0.25 LSB steps, resulting in a 14-bit monotonic DAC. The amount by which the DAC output is incremented or decremented is determined by Mode 2 bits DB6–DB0, e.g., for a 0.25 LSB increment/decrement DB6...DB0 = 0000001, while for a 2.5 LSB increment/decrement, DB6...DB0 = 0001010. The MODE bits determine whether the DAC data is incremented (01) or decremented (10). The maximum amount that the user is allowed to increment or decrement the DAC output is 127 steps of 0.25 LSB, i.e., DB6...DB0 = 1111111. Mode 2 update takes approximately 1 µs. The Mode 2 feature allows increased resolution but overall increment/decrement accuracy varies with increment/decrement step as shown in TPC 14. Mode 2 is useful in applications where greater resolution is required, for example, in servo applications requiring fine-tune to 14-bit resolution. The architecture of each DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage at the REF_IN Pin provides the reference voltage for the corresponding DAC. The input coding to the DAC is offset binary; this results in ideal DAC output voltages as follows: – Analog Output, VOUT Mode 1 (MODE bits = 00): The user programs a 12-bit data word to one of 16 channels via the serial interface. This word is loaded into the addressed DAC register and is then converted into an analog output voltage. During conversion the BUSY output is low and all SCLK pulses are ignored. At the end of a conversion BUSY goes high indicating that the update of the addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. Mode 1 conversion takes 25 µs typ. DIGITAL-TO-ANALOG SECTION 3 × 2N LSB The AD5516 has two modes of operation. On power-on, all DACs power up to a reset value (see RESET section). 2 × VREF _ IN × 2.5 × D MSB MODES OF OPERATION It is essential to minimize noise on REFIN for optimal performance. The AD780’s specified decoupling makes it the ideal reference to drive the AD5516. AD5516-1 VDAC = Table I. DAC Register Contents AD5516-1 Where: D = decimal equivalent of the binary code that is loaded to the DAC register, i.e., 0–4096 N = DAC resolution = 12 MSB 0 LSB 0 A3 MODE BITS A2 A1 A0 DB11 DB10 DB9 DB8 DB7 ADDRESS BITS DB6 DB5 DB4 DB3 DB2 DB1 DB0 DATA BITS Figure 4. Mode 1 Data Format MSB 0 LSB 1 A3 MODE BITS A2 A1 A0 0 0 0 0 0 DB6 DB5 ADDRESS BITS DB4 DB3 DB2 DB1 MSB 1 DB0 7 INCREMENT BITS LSB 0 MODE BITS A3 A2 A1 A0 0 0 0 0 0 DB6 DB5 ADDRESS BITS DB4 DB3 DB2 DB1 DB0 7 DECREMENT BITS Figure 5. Mode 2 Data Format –10– REV. 0 AD5516 The user must allow 200 ns (min) between two consecutive Mode 2 writes in standalone mode and 400 ns (min) between two consecutive Mode 2 writes in daisy-chain mode. Daisy-Chain Mode (DCEN = 1) In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 18 clock pulses are applied, the data ripples out of the shift register and appears on the DOUT line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next device in the chain, a multidevice interface is constructed. Eighteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 18N where N is the total number of devices in the chain. See the timing diagram in Figure 2. See Figures 4 and 5 for Mode 1 and Mode 2 data formats. When MODE bits = 11, the device is in No Operation mode. This may be useful in daisy-chain applications where the user does not wish to change the settings of the DACs. Simply write 11 to the MODE bits and the following address and data bits will be ignored. SERIAL INTERFACE The AD5516 has a 3-wire interface that is compatible with SPI/ QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 18-bit words. This 18-bit word consists of two mode bits, four address bits, and 12 data bits as shown in Figure 4. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device’s input shift register to the addressed DAC. The serial interface works with both a continuous and burst clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. RESET Function The RESET function on the AD5516 can be used to reset all nodes on this device to their power-on reset condition. This is implemented by applying a low-going pulse of minimum 20 ns to the RESET Pin on the device. A3–A0 Four address bits (A3 = MSB Address, A0 = LSB). These are used to address one of 16 DACs. Table III. Typical Power-ON Values Table II. Selected DAC A3 A2 A1 A0 Selected DAC 0 0 : 1 0 0 : 1 0 0 : 1 0 1 : 1 DAC 0 DAC 1 Output Voltage AD5516-1 AD5516-2 AD5516-3 –0.073 V –0.183 V –0.391 V BUSY Output During conversion, the BUSY output is low and all SCLK pulses are ignored. At the end of a conversion, BUSY goes high indicating that the update of the addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. DAC 15 DB11–DB0 These are used to write a 12-bit word into the addressed DAC register. Figures 1 and 2 show the timing diagram for a write cycle to the AD5516. MICROPROCESSOR INTERFACING The AD5516 is controlled via a versatile 3-wire serial interface that is compatible with a number of microprocessors and DSPs. SYNC FUNCTION In both standalone and daisy-chain modes, SYNC is an edgetriggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t3. AD5516 to ADSP-2106x SHARC DSP Interface The ADSP-2106x SHARC DSPs are easily interfaced to the AD5516 without the need for extra logic. The AD5516 expects a t3 (SYNC falling edge to SCLK falling edge setup time) of 15 ns min. Consult the ADSP-2106x User Manual for information on clock and frame sync frequencies for the SPORT register and contents of the TDIV, RDIV registers. Standalone Mode (DCEN = 0) After SYNC goes low, serial data will be shifted into the device’s input shift register on the falling edges of SCLK for 18 clock pulses. After the falling edge of the 18th SCLK pulse, data will automatically be transferred from the input shift register to the addressed DAC. SYNC must be taken high and low again for further serial data transfer. SYNC may be taken high after the falling edge of the 18th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t6. If SYNC is taken high before the 18th falling edge of SCLK, the data transfer will be aborted and the addressed DAC will not be updated. See the timing diagram in Figure 1. REV. 0 Device –11– AD5516 A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In write sequences data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5516 on the falling edge of its SCLK. The SPORT transmit control register should be set up as follows: DTYPE ICLK TFSR INTF LTFS LAFS SENDN SLEN = = = = = = = = AD5516 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register (SSPCON). See user PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to provide a SYNC signal and enable the serial port of the AD5516. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are required. Figure 8 shows the connection diagram. 00, Right Justify Data 1, Internal Serial Clock 1, Frame Every Word 1, Internal Frame Sync 1, Active Low Frame Sync Signal 0, Early Frame Sync 0, Data Transmitted MSB First 10011, 18-Bit Data Words (SLEN = Serial Word) SCLK Figure 6 shows the connection diagram. DIN SYNC ADSP-2106x* AD5516* PIC16C6x/7x* AD5516* SCK/RC3 SDI/RC4 RA1 *ADDITIONAL PINS OMITTED FOR CLARITY SYNC DIN TFS Figure 8. AD5516 to PIC16C6x/7x Interface DT AD5516 to 8051 SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 6. AD5516 to ADSP-2106x Interface AD5516 to MC68HC11 The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5516, the MOSI output drives the serial data line (DIN) of the AD5516. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5516, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to transmit 18 data bits, it is important to left justify the data in the SPDR register. PC7 must be pulled low to start a transfer and taken high and low again before any further read/write cycles can take place. A connection diagram is shown in Figure 7. MC68HC11* AD5516* SYNC PC7 SCLK SCK DIN MOSI *ADDITIONAL PINS OMITTED FOR CLARITY Figure 7. AD5516 to MC68HC11 Interface A serial interface between the AD5516 and the 80C51/80L51 microcontroller is shown in Figure 9. The AD5516 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. TxD of the microcontroller drives the SCLK of the AD5516, while RxD drives the serial data line. P3.3 is a bit programmable pin on the serial port that is used to drive SYNC. The 80C51/80L51 provides the LSB first, while the AD5516 expects MSB of the 18-bit word first. Care should be taken to ensure the transmit routine takes this into account. 8051* AD5516* SCLK TxD DIN RxD SYNC P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 9. AD5516 to 8051 Interface When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the AD5516 clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires an 18-bit word, P3.3 must be left low after the first eight bits are transferred, and brought high after the complete 18 bits have been transferred. DOUT may be tied to RxD for data verification purposes when the device is in daisy-chain mode. –12– REV. 0 AD5516 APPLICATION CIRCUITS POWER SUPPLY DECOUPLING The AD5516 is suited for use in many applications, such as level setting, optical, industrial systems, and automatic test applications. In level setting and servo applications where a fine-tune adjust is required, the Mode 2 function increases resolution. The following figures show the AD5516 used in some potential applications. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5516 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5516 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (AVCC1, AVCC2) it is recommended to tie those pins together. The AD5516 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as closely to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low-impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. AD5516 in a Typical ATE System The AD5516 is ideally suited for the level setting function in automatic test equipment. A number of DACs are required to control pin drivers, comparators, active loads, parametric measurement units, and signal timing. Figure 10 shows the AD5516 in such a system. DAC PARAMETRIC MEASUREMENT UNIT ACTIVE LOAD DAC SYSTEM BUS DAC DRIVER STORED DATA AND INHIBIT PATTERN DAC FORMATTER DUT DAC PERIOD GENERATION AND DELAY TIMING DAC COMPARE REGISTER DAC DACs SYSTEM BUS COMPARATOR Figure 10. AD5516 in an ATE System AD5516 in an Optical Network Control Loop The AD5516 can be used in optical network control applications that require a large number of DACs to perform a control and measurement function. In the example shown below, the outputs of the AD5516 are fed into amplifiers and used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured and the readings are multiplexed into an 8-channel, 14-bit ADC (AD7865). The increment and decrement modes of the DACs are useful in this application as it allows the user 14-bit resolution. The power supply lines of the AD5516 should use as large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on REFIN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process. The control loop is driven by an ADSP-2106x, a 32-bit SHARC DSP. 0 AD5516 15 0 MEMS MIRROR ARRAY 15 S E N S ADG609 ⴛ2 O R S 0 AD7865 7 AD8644 ⴛ2 ADSP-2106x Figure 11. AD5516 in an Optical Control Loop REV. 0 –13– AD5516 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 74-Lead LFBGA (BC-74) A1 CORNER INDEX CORNER A1 CORNER INDEX CORNER 10.00 (0.3937) BSC 12.00 (0.4724) BSC 11 10 9 8 7 6 5 4 3 2 1 TOP VIEW 12.00 (0.4724) BSC 1.00 (0.0394) BSC DETAIL A 1.70 (0.0669) MAX A B C D E 10.00 F (0.3937) G BSC H J K L BOT TOM VIEW 1.00 (0.0394) BSC DETAIL A 0.50 (0.0197) MIN 0.63 (0.0248) BSC SEATING PLANE BALL DIAMETER CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-192 –14– REV. 0 –15– –16– PRINTED IN U.S.A. C02792–0–5/02(0)