Revised October 1999 74ACT16245 16-Bit Transceiver with 3-STATE Outputs General Description Features The ACT16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. ■ Bidirectional non-inverting buffers ■ Separate control logic for each byte ■ 16-bit version of the ACT245 ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT16245SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT16245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Description Pin Names Description OEn Output Enable Input (Active LOW) T/R Transmit/Receive Input A0–A15 Side A Inputs/Outputs B0–B15 Side B Outputs/Inputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS500296 www.fairchildsemi.com 74ACT16245 16-Bit Transceiver with 3-STATE Outputs August 1999 74ACT16245 Functional Description Bus B data is transmitted to Bus A. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. The ACT16245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the T/R input is HIGH, then Bus A data is transmitted to Bus B. When the T/R input is LOW, Truth Tables Inputs OE1 Outputs T/R1 L L Bus B0–B7 Data to Bus A0–A7 L H Bus A0–A7 Data to Bus B0–B7 H X HIGH-Z State on A0–A7, B0–B7 Inputs OE2 Outputs T/R2 L L Bus B8–B15 Data to Bus A8–A15 L H Bus A8–A15 Data to Bus B8–B15 H X HIGH-Z State on A8–A15, B8–B15 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to + 7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA DC Output Voltage (VO) 0V to VCC 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V ± 50 mA Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ± 50 mA per Output Pin −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current Storage Temperature 0V to VCC Output Voltage (VO) −0.5V to VCC +0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) −65°C to +150°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC TA = −40°C to+85°C (V) Typ Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 4.5 3.86 3.76 5.5 4.86 4.76 Units V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IOZT Maximum I/O Leakage Current IIN Maximum Input Leakage Current ICCT Maximum ICC/Input ICC Max Quiescent IOLD Minimum Dynamic IOHD Output Current (Note 3) Supply Current V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH 5.5 ±0.5 ±5.0 µA 5.5 ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC −2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min 5.5 0.6 5.5 8.0 5.5 VO = VCC, GND Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. 3 www.fairchildsemi.com 74ACT16245 Absolute Maximum Ratings(Note 1) 74ACT16245 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay An, Bn to Bn, An tPZH Output Enable tPZL Time tPHZ Output Disable tPLZ Time VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 4) Min Typ Max Min Max 5.0 3.2 5.7 8.4 3.2 9.0 2.6 5.1 7.9 2.6 8.4 3.7 6.4 9.4 2.7 10.0 4.1 7.4 10.5 3.4 11.6 5.0 5.0 2.2 5.4 8.7 2.2 9.3 2.0 5.2 8.2 2.0 8.8 Note 4: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Typ Units CIN Symbol Input Pin Capacitance Parameter 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 25 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions Units ns ns ns 74ACT16245 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS48A 5 www.fairchildsemi.com 74ACT16245 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 www.fairchildsemi.com 6 74ACT16245 16-Bit Transceiver with 3-STATE Outputs Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com