Revised May 2005
74ACT16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
Features
The ACT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is low, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
■ Separate control logic for each byte
■ 16-bit version of the ACT373
■ Outputs source/sink 24 mA
■ TTL-compatible inputs
Ordering Code:
Order Number
Package Number
Package Description
74ACT16373SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACT16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active Low)
LEn
Latch Enable Input
I0–I15
Inputs
O0–O15
Outputs
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500297
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74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs
August 1999
74ACT16373
Functional Description
Truth Tables
The ACT16373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Inputs
Outputs
LE1
OE1
I0–I7
O0–O7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
Inputs
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
Supply Voltage (VCC)
20 mA
20 mA
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
Storage Temperature
0V to VCC
40qC to 85qC
Operating Temperature (TA)
20 mA
20 mA
0.5V to VCC 0.5V
50 mA
50 mA
Minimum Input Edge Rate ('V/'t)
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
per Output Pin
Junction Temperature
0V to VCC
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
4.5V to 5.5V
Input Voltage (VI)
140qC
65qC to150qC
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
VIH
VIL
VOH
VOL
TA
25qC
Typ
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
4.5
3.86
3.76
5.5
4.86
4.76
Maximum LOW
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
0.36
0.44
Maximum 3-STATE
Leakage Current
IIN
40qC to 85qC
Minimum HIGH
4.5
IOZ
TA
Maximum Input
Leakage Current
Units
Conditions
Guaranteed Limits
V
V
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
V
IOUT
50 PA
VIN
VIL or VIH
V
IOH
24 mA
IOH
24 mA (Note 2)
50 PA
V
IOUT
VIN
VIL or VIH
V
IOL
24 mA
24 mA (Note 2)
5.5
0.36
0.44
5.5
r 0.5
r 5.0
PA
5.5
r 0.1
r 1.0
PA
1.5
8.0
80.0
75
mA
VOLD
1.65V Max
75
mA
VOHD
3.85V Min
ICCT
Maximum ICC/Input
5.5
ICC
Max Quiescent Supply Current
5.5
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 3)
0.6
IOL
VI
VIL, VIH
VO
VCC, GND
VI
VCC, GND
mA
VI
VCC 2.1V
PA
VIN
VCC or GND
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
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74ACT16373
Absolute Maximum Ratings(Note 1)
74ACT16373
AC Electrical Characteristics
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Dn to On
tPLH
Propagation Delay
tPHL
LE to On
tPZH
Output Enable
tPZL
Delay
tPHZ
Output Disable
tPLZ
Delay
VCC
TA
25qC
(V)
CL
50 pF
40qC to 85qC
TA
CL
50 pF
(Note 4)
Min
Typ
Max
Min
Max
5.0
3.1
5.3
7.9
3.1
8.4
2.6
4.6
7.3
2.6
7.8
3.1
5.4
7.9
3.2
8.4
2.8
4.9
7.3
2.8
7.8
2.5
4.7
7.4
2.5
7.9
2.7
4.8
7.5
2.7
8.0
5.0
5.0
5.0
2.1
5.1
7.9
2.1
8.2
2.0
4.5
7.4
2.0
7.9
Units
ns
ns
ns
ns
Note 4: Voltage Range 5.0 is 5.0V r 0.5V.
AC Operating Requirements
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 5)
Setup Time, HIGH or
tS
LOW, Input to Clock
Hold time, HIGH or
tH
LOW, Input to Clock
tW
CS Pulse Width,
HIGH or LOW
TA
40qC to 85qC
CL
50 pF
5.0
3.0
3.0
ns
5.0
1.5
1.5
ns
5.0
4.0
4.0
ns
Note 5: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol
Parameter
Typ
Units
CIN
Input Capacitance
4.5
pF
VCC
5.0V
CPD
Power Dissipation Capacitance
30
pF
VCC
5.0V
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Units
Guaranteed Minimum
4
Conditions
74ACT16373
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
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74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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