74FST3125 Product Preview 4-Bit Bus Switch The ON Semiconductor 74FST3125 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. The device consists of four independent 1–bit switches with separate Output/Enable (OE) pins. Port A is connected to Port B when OE is low. If OE is high, the switch is high Z. • RON 4 Typical • Less Than 0.25 ns–Max Delay Through Switch • Nearly Zero Standby Current • No Circuit Bounce • Control Inputs are TTL/CMOS Compatible • Pin–For–Pin Compatible With QS3125, 74FST3125, CBT3125 • All Popular Packages: QSOP–16, TSSOP–14, SOIC–14 OE1 1A 1B OE2 2A 2B GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 4A 4B OE3 3A 3B Figure 1. Pin Assignment for SOIC and TSSOP OE1 1A OE2 1 2 3 4 5 6 7 8 NC OE1 1A 1B OE2 2A 2B GND 16 15 14 13 12 11 10 9 http://onsemi.com MARKING DIAGRAMS SO–14 D SUFFIX CASE 751A 1 14 14 1 VCC OE4 4A 4B OE3 3A 3B NC FST3125 ALYW TSSOP–14 DT SUFFIX CASE 948G 1 14 16 FST 3125 AWLYWW 1 Figure 2. Pin Assignment for QSOP 3 FST3125 AWLYWW 1 QSOP–16 QS SUFFIX CASE 492 1 2 14 14 A L, WL Y W, WW 1B 1 = = = = Assembly Location Wafer Lot Year Work Week PIN NAMES 4 Pin Description OE1, OE2, OE3, OE4 2A OE3 3A OE4 4A 5 6 2B 10 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B NC 9 8 3B 12 11 4B Figure 3. Logic Diagram Semiconductor Components Industries, LLC, 2001 Not Connected ORDERING INFORMATION 13 This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. June, 2001 – Rev. 0 Bus Switch Enables 1 Device Package Shipping 74FST3125D SO–14 55 Units/Rail 74FST3125DR2 SO–14 2500 Units/Reel 74FST3125DT TSSOP–14 96 Units/Rail 74FST3125DTR2 TSSOP–14 2500 Units/Reel 74FST3125M QSOP–16 50 Units/Rail 74FST3125MEL QSOP–16 2000 Units/Reel Publication Order Number: 74FST3125/D 74FST3125 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage 0.5 to 7.0 V VI DC Input Voltage 0.5 to 7.0 V VO DC Output Voltage 0.5 to 7.0 V IIK DC Input Diode Current VI GND 50 mA IOK DC Output Diode Current VO GND 50 mA IO DC Output Sink Current 128 mA ICC DC Supply Current per Supply Pin 100 mA IGND DC Ground Current per Ground Pin 100 mA TSTG Storage Temperature Range 65 to 150 C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias JA Thermal Resistance MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) 2000 200 N/A V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 85C (Note 4) 500 mA SOIC TSSOP QSOP 260 C 150 C 125 170 200 C/W Level 1 Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. Tested to EIA/JESD22–A114–A. 2. Tested to EIA/JESD22–A115–A. 3. Tested to JESD22–C101–A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free–Air Temperature t/V Input Transition Rise or Fall Rate Min Max Unit 4.0 5.5 V (Note ) 0 5.5 V (HIGH or LOW State) 0 VCC V 40 85 C DC 5 ns/V 0 Operating, Data Retention Only Switch Control Input Switch I/O – VCC = 5.0 V 0.5 V 5. Unused control inputs may not be left open. All control inputs must be tied to a high– or low–logic input voltage level. http://onsemi.com 2 74FST3125 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions IIN = 18mA VCC TA = 40C to 85C (V) Min Typ* 4.5 Max Unit 1.2 V VIK Clamp Diode Resistance VIH High–Level Input Voltage VIL Low–Level Input Voltage 4.0 to 5.5 .08 V II Input Leakage Current 0 VIN 5.5 V 5.5 1.0 A IOZ OFF–STATE Leakage Current 0 A, B VCC 5.5 1.0 A RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 4.0 to 5.5 2.0 V VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 A ICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. AC ELECTRICAL CHARACTERISTICS Limits TA = 40C to 85C VCC = 4.5 to 5.5 V Symbol Parameter Conditions Figures Min Max VCC = 4.0 V Min Max Unit 0.25 0.25 ns tPHL, tPLH Prop Delay Bus to Bus (Note 7) VI = OPEN 4 and 5 tPZH, tPZL Output Enable Time VI = 7 V for tPZL VI = OPEN for tPZH 4 and 5 1.0 5.0 5.5 ns tPHZ, tPLZ Output Disable Time VI = 7 V for tPLZ VI = OPEN for tPHZ 4 and 5 1.5 5.3 5.6 ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 3 pF CI/O Input/Output Capacitance VCC, OE = 5.0 V 5 pF 8. TA = 25C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 3 74FST3125 AC Loading and Waveforms VI 500 FROM OUTPUT UNDER TEST CL * 500 NOTES: 1. Input driven by 50 source terminated in 50 . 2. CL includes load and stray capacitance. *CL = 50 pF Figure 4. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 3.0 V 90 % 1.5 V 1.5 V 10 % Vmi 10 % tPLH GND tPLH VOH 1.5 V 1.5 V OUTPUT VOL Figure 5. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % tPZL OUTPUT 3.0 V GND tPZL 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 6. Enable/Disable Delays http://onsemi.com 4 VOH + 0.3 V 74FST3125 PACKAGE DIMENSIONS SO–14 D SUFFIX CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G B M M F R X 45 C –T– SEATING PLANE D 14 PL 0.25 (0.010) M K M T B S A S http://onsemi.com 5 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 74FST3125 PACKAGE DIMENSIONS TSSOP–14 DT SUFFIX CASE 948G–01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B –U– L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A –V– ÇÇÇ ÉÉ ÇÇÇ ÉÉ K1 J J1 SECTION N–N –W– C 0.10 (0.004) –T– SEATING PLANE D G H DETAIL E http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 74FST3125 PACKAGE DIMENSIONS QSOP–16 QS SUFFIX CASE 492–01 ISSUE O –A– Q R H x 45 U RAD. 0.013 X 0.005 DP. MAX –B– MOLD PIN MARK RAD. 0.005–0.010 TYP G L 0.25 (0.010) M P T DETAIL E V K C N 8 PL –T– D 16 PL 0.25 (0.010) SEATING PLANE M T B S A S J M F DETAIL E http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.189 0.196 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0 8 N 0 7 P 0.007 0.011 Q 0.020 DIA R 0.025 0.035 U 0.025 0.035 8 V 0 MILLIMETERS MAX MIN 4.80 4.98 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0 8 0 7 0.18 0.28 0.51 DIA 0.64 0.89 0.64 0.89 0 8 74FST3125 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 74FST3125/D