74FST3383 10−Bit Low Power Bus Exchange The ON Semiconductor 74FST3383 is a 10−bit low power bus exchange. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. http://onsemi.com MARKING DIAGRAMS Features • • • • • • • • RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin−For−Pin Compatible With QS3383, FST3383, CBT3383 All Popular Packages: SOIC−24, TSSOP−24, QSOP−24 All Devices in Package TSSOP are Inherently Pb−Free* 24 24 FST3383 AWLYWW 1 SOIC−24 DW SUFFIX CASE 751E 1 24 24 OE C0 A0 B0 D0 C1 A1 B1 D1 C2 A2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FST 3383 ALYW 1 VCC D4 B4 A4 C4 D3 B3 A3 C3 D2 B2 BX TSSOP−24 DT SUFFIX CASE 948H 1 24 24 1 QSOP−24 QS SUFFIX CASE 492B FST3383 AWLYYWW 1 Figure 1. 24−Lead Pinout TRUTH TABLE OE BX A0−A4 B0−B4 Function H X HIGH−Z State HIGH−Z State Disconnect L L C0−C4 D0−D4 Connect L H D0−D4 C0−C4 Exchange NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care A L, WL Y, YY W, WW = = = = Assembly Location Wafer Lot Year Work Week PIN NAMES Pin Description OE Bus Switch Enable BX Bus Exchange A0−A4, B0−B4 Buses A, B C0−C4, D0−D4 Buses C, D ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 Publication Order Number: 74FST3383/D 74FST3383 A0 C0 B0 D0 A4 C4 B4 D4 BX OE Figure 2. Logic Diagram ORDERING INFORMATION Package Shipping † 74FST3383DW SOIC−24 48 Units / Rail 74FST3383DWR2 SOIC−24 2500 Units / Tape & Reel 74FST3383DT TSSOP−24* (Pb−Free) 96 Units / Rail 74FST3383DTR2 TSSOP−24* (Pb−Free) 2500 Units / Tape & Reel 74FST3383QS QSOP−24 96 Units / Rail 74FST3383QSR QSOP−24 2500 Units / Tape & Reel Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 74FST3383 MAXIMUM RATINGS Symbol Value Unit DC Supply Voltage *0.5 to )7.0 V VI DC Input Voltage *0.5 to )7.0 V VO DC Output Voltage *0.5 to )7.0 V VI t GND *50 mA VO t GND *50 mA 128 mA VCC Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current ICC DC Supply Current per Supply Pin $100 mA IGND DC Ground Current per Ground Pin $100 mA TSTG Storage Temperature Range *65 to )150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup SOIC TSSOP QSOP °C °C 125 170 200 °C/W Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage Latchup Performance 260 )150 UL 94 V−0 @ 0.125 in Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) u2000 u200 N/A V Above VCC and Below GND at 85°C (Note 4) $500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate Switch I/O Operating, Data Retention Only Min Max Unit 4.0 5.5 V (Note 5) 0 5.5 V (HIGH or LOW State) 0 5.5 V *40 )85 °C DC 5 ns/V 0 Switch Control Input VCC = 5.0 V $ 0.5 V 5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level. http://onsemi.com 3 74FST3383 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIK Clamp Diode Resistance VIH High−Level Input Voltage VIL Low−Level Input Voltage VCC (V) Conditions IIN = *18mA TA = *405C to )855C Min Typ* 4.5 4.0 to 5.5 Max Unit *1.2 V 2.0 V 4.0 to 5.5 0.8 V Input Leakage Current 0 v VIN v 5.5 V 5.5 $1.0 mA IOZ OFF−STATE Leakage Current 0 v A, B v VCC 5.5 $1.0 mA RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 W VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.4 V, IIN = 15 mA 4.5 8 15 11 20 II VIN = 2.4 V, IIN = 15 mA 4.0 ICC Quiescent Supply Current VIN = VCC or GND, IOUT = 0 5.5 3 mA DICC Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA *Typical values are at VCC = 5.0 V and TA = 25°C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. AC ELECTRICAL CHARACTERISTICS TA = *405C to )855C CL = 50 pF, RU = RD = 500 W VCC = 4.5−5.5 V Symbol tPHL, tPLH Parameter Conditions Min Prop Delay, BX to An, Bn, Cn or Dn tPZH, tPZL tPHZ, tPLZ Max Unit 0.25 0.25 ns 1.0 5.8 6.5 VI = OPEN Prop Delay Bus to Bus (Note 7) Max VCC = 4.0 V Min Output Enable Time, BX to An, Bn, Cn or Dn VI = 7 V for tPZL 1.0 5.8 6.5 Output Enable Time, IOE to An, Bn, Cn or Dn VI = OPEN for tPZH 1.0 5.8 6.5 Output Disable Time, BX to An, Bn, Cn or Dn VI = 7 V for tPLZ 1.0 5.3 6.2 Output Disable Time, IOE to An, Bn, Cn or Dn VI = OPEN for tPHZ 1.0 5.3 6.2 ns ns 7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). CAPACITANCE (Note 8) Symbol Parameter Conditions Typ Max Unit CIN Control Pin Input Capacitance VCC = 5.0 V 6 pF CI/O Port Input/Output Capacitance VCC, OE = 5.0 V 13 pF 8. TA = )25°C, f = 1 MHz, Capacitance is characterized but not tested. http://onsemi.com 4 74FST3383 AC Loading and Waveforms VI 500 W FROM OUTPUT UNDER TEST CL* 500 W NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF Figure 3. AC Test Circuit tf = 2.5 nS 90 % SWITCH INPUT tf = 2.5 nS 90 % 1.5 V 3.0 V 1.5 V 10 % 10 % tPLH GND tPLH VOH 1.5 V OUTPUT 1.5 V VOL Figure 4. Propagation Delays tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 90 % 1.5 V 1.5 V 10 % 10 % tPZL OUTPUT 3.0 V GND tPZL 1.5 V tPZH VOL + 0.3 V VOL tPHZL VOH 1.5 V OUTPUT Figure 5. Enable/Disable Delays http://onsemi.com 5 VOH − 0.3 V 74FST3383 PACKAGE DIMENSIONS SOIC−24 D SUFFIX CASE 751E−04 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 24 13 −B− 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C −T− SEATING PLANE 22X G K M http://onsemi.com 6 X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 74FST3383 PACKAGE DIMENSIONS TSSOP−24 DT SUFFIX CASE 948H−01 ISSUE A 24X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S 2X 24 L/2 13 B −U− L PIN 1 IDENT. 12 1 0.15 (0.006) T U S S S A −V− C 0.10 (0.004) −T− SEATING PLANE G D N K ÉÉ ÇÇÇ ÇÇÇ ÉÉ ÇÇÇ H SECTION N−N J DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.25 (0.010) K1 J1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M −W− N DETAIL E F DETAIL E http://onsemi.com 7 74FST3383 PACKAGE DIMENSIONS QSOP−24 QS SUFFIX CASE 492B−01 ISSUE O −A− Q R H x 45_ U L MOLD PIN MARK RAD. 0.013 X 0.005 DP. MAX −B− RAD. 0.005−0.010 TYP G P 0.25 (0.010) DETAIL E T M V N 8 PL J K C 24 PL −T− D 0.25 (0.010) M SEATING PLANE M T B S A F S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.337 0.344 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0_ 8_ N 0_ 7_ P 0.027 0.037 Q 0.035 DIA R 0.035 0.045 U 0.035 0.045 V 0_ 8_ MILLIMETERS MAX MIN 8.56 8.74 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0_ 8_ 0_ 7_ 0.69 0.94 0.89 DIA 0.89 1.14 0.89 1.14 0_ 8_ DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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