CS8126 5.0 V, 750 mA Low Dropout Linear Regulator with Delayed RESET The CS8126 is a low dropout, high current 5.0 V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced RESET circuitry. Familiar PNP regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the CS8126 suitable for use in automotive and battery operated equipment. Additional on–chip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor RESET function is included on–chip with externally programmable delay time. During power–up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capacitor discharge (0.2 V type). Note: The CS8126 is lead compatible with the LM2927 and LM2926. http://onsemi.com TO–220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO–220 FIVE LEAD TVA SUFFIX CASE 314K 1 1 TO–220 FIVE LEAD THA SUFFIX CASE 314A Pin 1. VIN 2. VOUT 3. GND 4. Delay 5. RESET 5 TO–220 FIVE LEAD THE SUFFIX CASE 314J 1 5 Features • Low Dropout Voltage (0.6 V at 0.5 A) • 3.0% Output Accuracy • Active RESET • External RESET Delay for Reset • Protection Circuitry – Reverse Battery Protection – +60 V, –50 V Peak Transient Voltage – Short Circuit Protection – Internal Thermal Overload Protection D2PAK 7–PIN DPS SUFFIX CASE 936H 1 7 Pin 1. VIN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC SO–16L D SUFFIX CASE 751B 16 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2001 January, 2001 – Rev. 11 1 Publication Order Number: CS8126/D CS8126 PIN CONNECTIONS SO–16L 1 16 VIN NC NC NC NC RESET NC Delay VOUT NC VOUT(SENSE) NC NC GND NC NC VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias Pre–Regulator Bandgap Reference Error Amp – + Charge Current Generator Anti–Saturation and Current Limit Thermal Shutdown Delay Latching Discharge – Q S R – + Reset Comparator + Delay Comparator VDischarge + – GND Figure 1. Block Diagram http://onsemi.com 2 RESET CS8126 ABSOLUTE MAXIMUM RATINGS* Rating Value Unit Internally Limited – –50, 60 V Internally Limited – 4.0 kV Junction Temperature Range –40 to +150 °C Storage Temperature Range –55 to +150 °C 260 peak 230 peak °C °C Power Dissipation Peak Transient Voltage (46 V Load Dump) Output Current ESD Susceptibility (Human Body Model) Lead Temperature Soldering: Wave Solder (through hole styles only) (Note 1.) Reflow (SMD styles only) (Note 2.) 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ELECTRICAL CHARACTERISTICS (TA = –40°C to +125°C, TJ = –40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kΩ to VCC, unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit – 4.85 5.00 5.15 V Output Stage (VOUT) Output Voltage Dropout Voltage IOUT1 = 500 mA – 0.35 0.60 V Supply Current IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA – – – 2.0 6.0 55 7.0 12 100 mA mA mA Line Regulation VIN = 6.0 to 26 V, IOUT = 50 mA – 5.0 50 mV Load Regulation IOUT = 50 to 500 mA, VIN = 14 V – 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 – dB Current Limit – 0.75 1.20 – A Overvoltage Shutdown – 32 – 40 V – 95 – V –15 –30 – V – –80 – V 150 180 210 °C Maximum Line Transient VOUT ≤ 5.5 V Reverse Polarity Input Voltage DC VOUT ≥ –0.6 V, 10 Ω Load Reverse Polarity Input Voltage Transient 1.0% Duty Cycle, T < 100 ms, 10 Ω Load Thermal Shutdown Note 3. 3. Guaranteed By Design http://onsemi.com 3 CS8126 ELECTRICAL CHARACTERISTICS (continued) (TA = –40°C to +125°C, TJ = –40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kΩ to VCC, unless otherwise noted.) Characteristic Test Conditions Min Typ Max Unit RESET and Delay Functions Delay Charge Current VDelay = 2.0 V 5.0 10 15 µA RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.65 4.50 4.90 4.70 VOUT – 0.01 VOUT – 0.15 V V RESET Hysteresis VRH = VRT(ON) – VRT(OFF) 150 200 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V 200 400 800 mV Delay Hysteresis – RESET Output Voltage Low 1.0 V < VOUT < VRTL, 3.0 kΩ to VOUT – 0.1 0.4 V RESET Output Leakage Current VOUT > VRT(ON) – 0 10 µA Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT – 0.2 0.5 V Delay Time CDelay = 0.1 µF*. Note 4. 16 32 48 ms * Delay Time CDelay VDelayThreshold Charge CDelay 3.2 105 (typ) ICharge 4. Assumes Ideal Capacitor PACKAGE LEAD DESCRIPTION PACKAGE LEAD # TO–220 5 LEAD D2PAK 7–PIN SO–16L LEAD SYMBOL 1 1 1 VIN 2 2 16 VOUT Regulated 5.0 V output. 3 4 11 GND Ground connection. 4 5 8 Delay Timing capacitor for RESET function. 5 6 6 RESET – 3 14 VOUT(SENSE) – 7 2, 3, 4, 5, 7, 9, 10, 12, 13, 15 NC FUNCTION Unregulated supply voltage to IC. CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. Remote sensing of output voltage. No Connection. http://onsemi.com 4 CS8126 TYPICAL PERFORMANCE CHARACTERISTICS RLOAD = 25 Ω Room Temp. 120 110 55 50 45 35 ICQ (mA) ICQ (mA) 40 30 25°C 25 20 15 RLOAD = 6.67 100 90 80 125°C 70 60 RLOAD = 10 50 40 30 20 –40°C 10 5.0 RLOAD = 25 10 0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 RLOAD = NO LOAD 0 1.0 2.0 3.0 4.0 7.0 8.0 Figure 2. ICQ vs. VIN Over Temperature Figure 3. ICQ vs. VIN Over RLOAD 5.5 5.0 5.0 4.5 4.5 4.0 4.0 3.5 3.5 3.0 125°C 2.5 2.0 –40°C 1.5 10 9.0 10 RLOAD = NO LOAD RLOAD = 6.67 3.0 2.5 2.0 1.5 1.0 RLOAD = 10 1.0 0.5 9.0 Room Temp. 5.5 VOUT (V) VOUT (V) 6.0 VIN (V) RLOAD = 25 Ω 0.5 25°C 0 0 0 100 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VIN (V) VIN (V) Figure 4. VOUT vs. VIN Over Temperature Figure 5. VOUT vs. VIN Over RLOAD 6.0 VIN 6.0–26 V 80 TEMP = –40°C 4.0 40 Load Regulation (mV) 60 Line Regulation (mV) 5.0 VIN (V) TEMP = 25°C 20 TEMP = 40°C 0 –20 –40 TEMP = 125°C 2.0 0 –2.0 VIN = 14 V –6.0 TEMP = 125°C –8.0 –60 –10 –80 –12 –100 TEMP = 25°C –4.0 –14 0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700 Output Current (mA) Output Current (mA) Figure 6. Line Regulation vs. Output Current Over Temperature Figure 7. Load Regulation vs. Output Current Over Temperature http://onsemi.com 5 800 CS8126 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 900 100 700 600 Quiescent Current (mA) Dropout Voltage (mV) 25°C 125°C 500 400 300 –40°C 200 100 80 25°C VIN = 14 V 70 –40°C 60 50 40 30 20 10 0 0 0 100 200 300 400 500 600 700 800 0 100 200 300 600 700 Figure 8. Dropout Voltage vs. Output Current Over Temperature Figure 9. Quiescent Current vs. Output Current Over Temperature 800 103 COUT ==10 COUT 10µF, mF,ESR = 1 ESR & 0.1=µF, 1 &ESR 0.1 = mF, 0 ESR = 0 70 102 101 ESR (Ω) 60 50 40 COUT = 10 µF, ESR = 1.0 Ω 30 COUT = 47/68 µF 100 Stable Region 10–1 COUT = 47 µF 10–2 20 COUT = 10 µF, ESR = 10 Ω 101 102 103 104 105 106 COUT = 68 µF 10–3 10 100 500 Output Current (mA) 80 0 400 Output Current (mA) 90 Rejection (dB) 125°C 90 800 107 10–4 108 100 101 102 Freq. (Hz) Output Current (mA) Figure 10. Ripple Rejection Figure 11. Output Capacitor ESR 103 RESET CIRCUIT WAVEFORM VOUT VRT(ON) VRT(OFF) (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max:RESET Voltage (1.0 V) VRH (1) RESET (2) (3) VRL tDelay Delay VDC(HI) VDC(LO) VDH VDIS (2) Figure 12. RESET Circuit Waveform http://onsemi.com 6 CS8126 CIRCUIT DESCRIPTION The CS8126 RESET function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram). voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(H1). The Delay time for the RESET function is calculated from the formula: Low Voltage Inhibit Circuit This circuit monitors output voltage, and when the output voltage falls below VRT(OFF), causes the RESET output transistor to be in the ON (saturation) state. When the output voltage rises above VRT(ON), this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit. Delay time CDelay VDelayThreshold ICharge Delay time CDelay 3.2 105 RESET Delay Circuit This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output If CDelay = 0.1 µF, Delay time (ms) = 32 ms ± 50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. APPLICATION DIAGRAM VOUT VIN C1 * 100 nF RRST 4.7 kΩ CS8126 RESET Delay Delay 0.1 µF C2** 10 µF to 100 µF GND * C1 is required if the regulator is far from the power source filter. ** C2 is required for stability. Figure 13. Application Diagram APPLICATION NOTES Stability Considerations temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low http://onsemi.com 7 CS8126 Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. RJA 150°C TA PD (2) The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. IIN VIN IOUT Smart Regulator Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Control Features Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Figure 14. Single Output Regulator With Key Performance Parameters Labeled IQ Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Heat Sinks A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. RJA RJC RCS RSA (3) where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) VIN(max) VOUT(min)IOUT(max) VIN(max)IQ VOUT (1) http://onsemi.com 8 CS8126 ORDERING INFORMATION Device Description Shipping TO–220 FIVE LEAD STRAIGHT 50 Units/Rail CS8126–1YTVA5 TO–220 FIVE LEAD VERTICAL 50 Units/Rail CS8126–1YTHA5 TO–220 FIVE LEAD HORIZONTAL 50 Units/Rail CS8126–1YTHE5 TO–220 FIVE LEAD SURFACE MOUNT 50 Units/Rail CS8126–1YTHER5 TO–220 FIVE LEAD SURFACE MOUNT 750 Tape & Reel CS8126–1YDPS7 D2PAK, 7–PIN 50 Units/Rail CS8126–1YDPSR7 D2PAK, CS8126–1YT5 7–PIN 750 Tape & Reel CS8126–1YDW16 SO–16L 46 Units/Rail CS8126–1YDWR16 SO–16L 1000 Tape & Reel MARKING DIAGRAMS TO–220 FIVE LEAD T SUFFIX CASE 314D TO–220 FIVE LEAD TVA SUFFIX CASE 314K TO–220 FIVE LEAD THA SUFFIX CASE 314A TO–220 FIVE LEAD THE SUFFIX CASE 314J D2PAK 7–PIN DPS SUFFIX CASE 936H SO–16L D SUFFIX CASE 751B 1 XXXXXXXX AWLYWW XXXXXXXX AWLYWW XXXXXXXX AWLYWW XXXXXXXX AWLYWW 1 1 1 1 1 XXX... A WL, L YY, Y WW, W = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week http://onsemi.com 9 XXXXXXXXXX AWLYWW XXXXXXXX AWLYWW 16 CS8126 PACKAGE DIMENSIONS TO–220 FIVE LEAD T SUFFIX CASE 314D–04 ISSUE E –T– –Q– SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. C B E A U L K J H G D DIM A B C D E G H J K L Q U 1234 5 5 PL 0.356 (0.014) M T Q M INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972 TO–220 FIVE LEAD TVA SUFFIX CASE 314K–01 ISSUE O –T– SEATING PLANE C B –Q– E W A U F L 1 2 3 4 K 5 M D 0.356 (0.014) M J 5 PL T Q M G S R http://onsemi.com 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5° MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5° CS8126 TO–220 FIVE LEAD THA SUFFIX CASE 314A–03 ISSUE E –T– B –P– Q C E OPTIONAL CHAMFER A U F L DIM A B C D E F G J K L Q S U K G 5X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. SEATING PLANE 5X J S D 0.014 (0.356) M T P M INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827 TO–220 FIVE LEAD THE SUFFIX CASE 314J–01 ISSUE O –T– SEATING PLANE C B –Q– E W A U F L 1 D 0.356 (0.014) M 2 3 4 5 5 PL T Q K J M G –M– S 0.102 (0.004) –N– http://onsemi.com 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 4. DIMENSIONS EXCLUSIVE OF MOLD FLASH AND METAL BURRS. 5. FOOTPAD LENGTH MEASURED FROM LEAD TIP WITH REFERENCE TO DATUM -M-. 6. COPLANARITY 0.004" MAX. REFERENCE TO DATUM -N- STANDOFF HEIGHT 0.00 - 0.010". DIM A B C D E F G J K L Q S U W INCHES MIN MAX 0.568 0.583 0.395 0.405 0.170 0.180 0.028 0.036 0.045 0.055 0.543 0.558 0.067 BSC 0.014 0.022 0.073 0.088 0.324 0.339 0.146 0.156 0.000 0.010 0.460 0.475 5° MILLIMETERS MIN MAX 14.43 14.81 10.03 10.29 4.32 4.57 0.71 0.91 1.14 1.40 13.79 14.17 1.70 BSC 0.36 0.56 1.85 2.24 8.23 8.61 3.71 3.96 0.00 0.25 11.68 12.07 5° CS8126 D2PAK 7–PIN DPS SUFFIX CASE 936H–01 ISSUE O –T– SEATING PLANE B U C M NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. E 8 V DIM A B C D E F G H J K M N U V A 1 2 34 5 6 7 K F G D H 7 PL 0.13 (0.005) M T B J M INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.036 0.045 0.055 0.058 0.078 0.050 BSC 0.100 0.110 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 0.256 REF 0.305 REF MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 1.41 1.98 1.27 BSC 2.54 2.79 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 6.50 REF 7.75 REF N SO–16L D SUFFIX CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 12 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 CS8126 PACKAGE THERMAL DATA Parameter TO–220 FIVE LEAD D2PAK 7–PIN SO–16L Unit RΘJC Typical 2.1 2.1 23 °C/W RΘJA Typical 50 10–50* 105 °C/W *Depending on thermal properties of sustrate. RΘJA = RΘJC + RΘCA. http://onsemi.com 13 CS8126 Notes http://onsemi.com 14 CS8126 Notes http://onsemi.com 15 CS8126 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2745 Email: [email protected] EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: [email protected] ON Semiconductor Website: http://onsemi.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland For additional information, please contact your local Sales Representative. http://onsemi.com 16 CS8126/D