ETC HCF4515

HCF4515B
OUTPUT "LOW" ON SELECT
4-BIT LATCH/4-TO-16 LINE DECODER
■
■
■
■
■
■
QUIESCENT CURRENT SPECIF. UP TO 20V
STROBED INPUT LATCH
INHIBIT CONTROL
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF4515B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in SOP package.
HCF4515B consists of a 4-bit strobed latch and a
4 to 16 line decoder. The latches hold the last
input data presented prior to the strobe transition
from 1 to 0. Inhibit control allows all outputs to be
placed at 1 regardless of the state of the data or
strobe inputs. The decode truth table indicates all
combinations of data inputs and appropriate
selected outputs.
SOP
ORDER CODES
PACKAGE
TUBE
T&R
SOP
HCF4515BM1
HCF4515M013TR
PIN CONNECTION
September 2002
1/9
HCF4515B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 3, 21, 22
11, 9, 10, 8,
7, 6, 5, 4, 18,
17, 20, 19,
14, 13, 16,
15
23
12
24
FUNCTIONAL DIAGRAM
2/9
SYMBOL
NAME AND FUNCTION
STROBE
Strobe Input
DATA 1 to 4 Address Inputs
S0 to S15 Multiplexer Outputs
(Active HIGH)
INHIBIT
VSS
Enable Input
Negative Supply Voltage
VDD
Positive Supply Voltage
HCF4515B
LOGIC DIAGRAM
TRUTH TABLE
INPUTS
INHIBIT
A
B
C
D
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
STROBE
SELECT OUTPUT
STROBE = "H"
Refer to truth table
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
ALL OUTPUTS "L"
STROBE = "L"
Data at the negative going
transition of strobe shall
be provided on the each
output while strobe is held
low.
X : Don’t Care
3/9
HCF4515B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
4/9
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
HCF4515B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
CI
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
18
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
150
300
600
3000
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
±0.1
5
7.5
0.05
0.05
0.05
1.5
3
4
V
V
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±1
µA
V
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
Unit
V
mA
mA
±1
µA
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
5/9
HCF4515B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
tPHL tPLH Propagation Delay Time
tPHL tPLH Propagation Delay Time
tTHL tTLH Transition Time
tW
tsetup
Strobe Pulse Width
Setup Time
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Value (*)
Unit
Min.
Typ.
Max.
970
370
270
500
220
170
200
100
80
250
100
70
150
70
40
485
185
135
250
110
85
100
50
40
125
50
35
75
35
20
Strobe or Data
Inhibit
ns
ns
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C
(1) : If more than one unit is cascaded. tr should be made less than or equal to the sum of the transition time and the fixed propagation delay
of the output of the driving stage for the estimated capacitive load.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
6/9
HCF4515B
WAVEFORM : SETUP TIME and STROBE PULSE WIDTH (f=1MHz; 50% duty cycle)
7/9
HCF4515B
SO-24 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
2.65
a1
0.1
0.104
0.2
a2
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.012
C
0.5
0.020
c1
45˚ (typ.)
D
15.20
15.60
0.598
0.614
E
10.00
10.65
0.393
0.419
e
1.27
0.050
e3
13.97
0.550
F
7.40
7.60
0.291
0.300
L
0.50
1.27
0.020
0.050
S
8 ˚ (max.)
L
s
e3
b1
e
a1
b
A
a2
C
c1
E
D
13
F
24
1
1
2
PO13T
8/9
HCF4515B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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