IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: – – – – – – – IDT74LVCR16952A Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ±0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion This 16-bit registered transceiver is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type registered transceivers with separate input and output control for independent control of data flow in either direction. For example, the A-to-B Enable (CEAB) must be LOW to enter data from the A port. CLKAB controls the clocking function. When CLKAB toggles from LOWto-HIGH, the data present on the A port will be clocked into the register. OEAB performs the output enable function on the B port. Data flow from the B port to A port is similar but requires using CEBA, CLKBA, and OEBA inputs. Full 16-bit operation is achieved by tying the control pins of the independent transceivers together. Drive Features for LVC162952A: – Balanced Output Drivers: ±12mA – Low Switching Noise All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. APPLICATIONS: The LVCR162952A has series resistors in the device output structure which will significantly reduce line noise when used with light loads.This driver has been developed to drive ±12mA at the designated threshold levels. • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 54 31 1 CEBA 1 CLKBA 2 CEBA 55 2 CLKBA 28 1 1 OEAB 2 OEAB 3 26 1 CEAB 1 CLKAB 1 OEBA 2 CEAB 2 2 CLKAB 27 29 56 2 OEBA C 1A 1 30 5 CE D 52 2A 1 1B 1 15 C CE D C CE D C CE D TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS INDUSTRIAL TEMPERATURE RANGE 42 2B 1 SEPTEMBER 2000 1 c 1999 Integrated Device Technology, Inc. DSC-4484/- IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS (1) OEAB 1 56 1 OEBA Symbol VTERM Description Terminal Voltage with Respect to GND Max. – 0.5 to +6.5 1 CLKAB 2 55 1 CLKBA TSTG Storage Temperature – 65 to +150 °C 1 CEAB 3 54 1 CEBA IOUT DC Output Current – 50 to +50 mA GND 4 53 Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through mA 52 IIK IOK ICC – 50 5 ±100 mA ISS each VCC or GND 1 1A 1 6 1A 2 GND 1B 1 51 1B 2 V CC V CC 7 50 1A 3 8 49 1A 4 9 48 1A 5 10 47 1B 5 11 46 GND 1A 6 12 45 1B 6 1A 7 13 44 1B 7 43 1B 8 GND SO56-1 14 SO56-2 15 SO56-3 1A 8 2A 1 42 2B 1 17 40 18 39 19 38 20 37 2A 6 21 36 V CC 22 35 23 34 24 33 GND 25 32 2 CEAB 26 31 2 CEBA 2 CLKAB 27 30 2 CLKBA 2 O EAB 28 29 2 O EBA GND 2A 4 2A 5 2A 7 2A 8 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1B 4 41 2A 3 LVC Link 1B 3 16 2A 2 CAPACITANCE (TA = +25oC, f = 1.0MHz) 2B 2 2B 3 GND 2B 4 Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 6.5 8 pF VIN = 0V 6.5 8 pF 2B 5 CI/O 2B 6 V CC LVC Link NOTE: 1. As applicable to the device type. 2B 7 2B 8 GND FUNCTION TABLE (1, 2) xCEAB SSOP/ TSSOP/ TVSOP TOP VIEW PIN DESCRIPTION Pin Names xOEAB Description A-to-B Output Enable Input (Active LOW) xOEBA B-to-A Output Enable Input (Active LOW) xCEAB A-to-B Clock Enable Input (Active LOW) xCEBA B-to-A Clock Enable Input (Active LOW) xCLKAB A-to-B Clock Input xCLKBA B-to-A Clock Input xAx A-to-B Data Inputs or B-to-A 3-State Outputs xBx B-to-A Data Inputs or A-to-B 3-State Outputs c 1998 Integrated Device Technology, Inc. Unit V Inputs xCLKAB xOEAB xAx Outputs xBx H X L X B0(3) X L L X B0(3) L ↑ L L L L ↑ L H H X X H X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition 2. A-to-B data flow is shown: B-toA data flow is similar but uses xCEBA, xCLKBA, and xOEBA. 3. Output level of B before the indicated steady-state input conditions were established. 2 DSC-123456 IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40OC to +85OC Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Min. 1.7 Typ.(1) — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Test Conditions VCC = 2.3V to 2.7V Max. — Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — — 10 µA 3.6 ≤ VIN ≤ 5.5V(2) — — 10 ∆ICC Quiescent Power Supply Current Variation — — 500 One input at VCC - 0.6V other inputs at VCC or GND µA LVC Link NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VOL Output LOW Voltage Min. VCC – 0.2 Max. — IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — VCC = 3.0V IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 VCC = 2.7V VCC = 3.0V IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 Unit V V LVC Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to +85°C. 3 IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol CPD Parameter Power Dissipation Capacitance per transceiver Outputs enabled CPD Power Dissipation Capacitance per transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF pF SWITCHING CHARACTERISTICS (1) VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tSK(o) Parameter Propagation Delay xCLKAB, xCLKBA to xBx, xAx Output Enable Time xOEBA, xOEAB to xAx, xBx Output Disable Time xOEBA, xOEAB to xAx, xBx Set-up Time, HIGH or LOW xAx, xBx before xCLKAB↑, xCLKBA↑ Hold Time, HIGH or LOW xAx, xBx after xCLKAB↑, xCLKBA↑ Set-up Time, HIGH or LOW xCEAB, xCEBA before xCLKAB↑, xCLKBA↑ Hold Time, HIGH or LOW xCEAB, xCEBA after xCLKAB↑, xCLKBA↑ Pulse Width HIGH or LOW xCLKAB or xCLKBA Output Skew(2) Min. 2 Max. 7.6 Min. 2 Max. 6.6 Unit ns 1.5 8 1.5 7 ns 1.5 7.5 1.5 6.5 ns 2.5 — 2.5 — ns 1.5 — 1.5 — ns 1.8 — 1.4 — ns 2 — 2 — ns 3 — 3 — ns — — — 500 ps NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 VCC = 3.3V±0.3V IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit 2 x Vcc V 6 6 VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF t PHL V IH VT 0V ENABLE AND DISABLE TIMES V LOAD V IN t PLH DISABLE ENABLE GND V IH CONTROL INPUT V OUT VT tPZL D.U.T. OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH 500 Ω RT V OH VT V OL LVC Link Open Pulse (1, 2) Generator t PHL OPPOSITE PHASE INPUT TRANSITION TEST CIRCUITS FOR ALL OUTPUTS 500 Ω t PLH OUTPUT LVC Link V CC V IH VT 0V SAME PHASE INPUT TRANSITION CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 0V tPLZ V LOAD/2 V LOAD/2 VT V OL+ V LZ V OL tPHZ VT V OH V OH- V HZ 0V 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD DATA INPUT t SU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open LVC Link SYNCHRONOUS CONTROL OUTPUT SKEW - tsk (x) tSU tH LVC Link V IH INPUT VT 0V t PHL1 tPLH1 PULSE WIDTH V OH OUTPUT 1 tSK (x) t SK (x) LOW -HIGH-LOW PULSE VT V OL tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT LVC Link t PLH2 tPHL2 tSK (x) = tPLH2 - tPLH1 or t PHL2 - t PHL1 LVC NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. Link 5 IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LVC Temp. Range X XX XXXX XX Bus-Hold Family Device Type Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 952A 16-Bit Registered Transceiver with 3-State Outputs R16 Double-Density with Resistors, ±12mA Blank 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 No Bus-hold -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6