ETC ISP12320

QLogic Corporation
ISP12320 Intelligent, Dual Channel Ultra320
SCSI Processor
Data Sheet
Features
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Supports 133-MHz PCI-X, with a maximum
transfer rate of 1 GB/sec over the PCI bus
❒ 133-MHz, 64-bit PCI-X host bus interface
❒ Backward compatible to 66-MHz conventional
PCI
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Compliance with PCI Local Bus Specification
rev 2.1
Compliance with ANSI draft T10/1365D SCSI
Parallel Interface–4 (SPI-4)
SCSI features set: Supports packetized SCSI
protocol, and quick arbitration and select (QAS)
Supports Ultra320 (Fast-160) SCSI. Backward
compatible with Ultra160, Ultra2, and legacy SCSI
devices.
Compliance with PCI Bus Power Management
Interface Specification revision 1.0 (PC98)
Two concurrently operating wide, Ultra320 SCSI
channels
Up to 320 MB/sec parallel SCSI transfer rates per
channel
Supports single-ended and low voltage differential
(LVD) SCSI
SCSI initiator and target modes of operation
On-chip RISC processors (one for each channel) to
execute operations at the I/O control-block level
from the host memory
On-chip embedded synchronous RAMs to support
on-chip processors
Supports PCI dual-address cycle (64-bit
addressing)
No host intervention required to execute SCSI
operations from start to finish
Simultaneous, multiple logical threads
JTAG boundary scan support
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applications. This device interfaces the PCI bus to two
Ultra320 SCSI buses and contains an onboard RISC
processor. The product is a fully autonomous device,
capable of managing multiple I/O operations and
associated data transfers from start to finish without host
intervention. The ISP12320 provides power management
feature support in accordance with the PCI Bus Power
Management Interface Specification. The ISP12320 is
host-software compatible with the QLogic ISP12160A
chip.
ISP Initiator and Target Firmware
The ISP12320 firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery, while the multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP12320 can switch between initiator and target modes.
Software Drivers
Software drivers are available for all major operating
systems. ISP12320 BIOS firmware is also available.
Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP12320 incorporates two
high-speed proprietary RISC processors; two intelligent
SCSI bus controllers (SCSI executive processors [SXPs]);
and a host bus, dual-channel DMA controller. The SCSI
bus controllers and the host bus DMA controller operate
independently and concurrently under the control of the
onboard RISC processors for maximum system
performance.
Product Description
The ISP12320 supports dual channel, Ultra320
(Fast-160) SCSI functionality and is pin compatible with
QLogic’s ISP12160A dual SCSI processor. The product is
a single-chip, highly integrated bus master, dual-channel
SCSI I/O processor for SCSI initiator and target
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ISP12320
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QLogic Corporation
The complete I/O subsystem solution including the ISP12320 and associated supporting memory devices is shown in
figure 1.
SCSI
TARGETS
ISP12320
HOST
MEMORY
TARGET
PCI
INTERFACE
SCSI
I/F
PCI
IOCB
64
P
C
I
DATA
SCSI
16
TARGET
FIFO
DMA
CONTROL
SCSI
TARGETS
MAILBOX
B
U
S
TARGET
SCSI
I/F
RISC
SCSI
16
TARGET
CODE/DATA
MEMORY
NVRAM
FLASH
BIOS
Figure 1. I/O Subsystem Design Using the ISP12320
Product Architecture
The following sections describe the ISP12320 modules.
PCI-X Interface
The ISP12320 PCI-X interface has the following
features:
■ 66-MHz or 133-MHz, 64-bit, true multifunction,
intelligent bus master PCI-X interface
■ 33-MHz and 66-MHz 64-bit intelligent bus master
conventional PCI interface (PCI 2.2)
■ 64-bit host memory addressing (dual-address cycle)
■ 10-channel DMA controller
■ 32-bit PCI target mode for communication with the
host
■ Pipelined DMA registers for efficient scatter/gather
operations
■ 64-bit DMA transfer counter to support large
I/O transfer lengths
■ Support for PCI-X split transactions
■ Support for PCI power management
■ Support for the message signaled interrupt function
■ Support for flash BIOS PROM
■ Support for subsystem ID
■ 3.3-V and 5.0-V tolerant PCI-X I/O buffers
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ISP12320
The ISP12320 is designed to interface directly to the
PCI or PCI-X bus and operate as a 64-bit DMA bus master.
This function is accomplished through a PCI bus interface
unit (PBIU) containing an onboard DMA controller. The
PBIU generates and samples PCI control signals, generates
host memory addresses, and facilitates the transfer of data
between host memory and the onboard frame buffer. It also
allows the host to access the ISP12320 internal registers
and communicate with the onboard RISC processors.
The ISP12320 onboard DMA controller consists of
10 independent DMA channels that initiate transactions on
the PCI bus and transfer data between the host memory and
frame buffer or the RISC RAM.
The PBIU internally arbitrates between the DMA
channels and alternately services them. Each DMA channel
has a set of DMA registers that are programmed for
transfers by the RISC processors.
SCSI Executive Processors
The ISP12320 SXPs support the following:
■ Synchronous (Fast-5 and Fast-10), Ultra (Fast-20),
Ultra2 (Fast-40), Ultra3 (Fast-80), and Ultra320
(Fast-160) SCSI synchronous data transfer rates up
to 320 MB/sec per channel
■ Asynchronous SCSI data transfer rates up to
12 MB/sec
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QLogic Corporation
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Programmable SCSI processor
❒ Specialized instruction set with 16-bit
microword
❒ 1K ™ 16 internal RAM control store
32-bit, configurable SCSI transfer counter
Command, status, message in, and message out
buffers
Device information storage area
On-chip, LVD SCSI transceivers
Programmable active negation
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
RISC Processors
The ISP12320 RISC processors have the following
features:
■ Execution of multiple I/O control blocks from the
host memory
■ Reduced host intervention and interrupt overhead
■ One interrupt or less per I/O operation
One of the major features of the ISP12320 is its ability
to handle complete I/O transactions from start to finish with
no host intervention. This high level of integration is
accomplished with the onboard RISC processors.
The ISP12320 RISC processors control the chip interfaces;
execute simultaneous, multiple IOCBs; and maintain the
required thread information for each transfer.
Packaging
The ISP12320 is available in a 492-pin plastic ballgrid
array (PBGA) package.
© 2001 QLogic Corporation. All rights reserved worldwide.
QLogic is a trademark of QLogic Corporation.
All other brand and product names are trademarks or registered trademarks of their respective owners.
Specifications are subject to change without notice.
QLogic Corporation, 26600 Laguna Hills Drive, Aliso Viejo, CA 92656, (800) 867-7274 or (949) 389-6000
January 31, 2001
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ISP12320
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