ITPM-ER02-IT8172 Date:06/17/2002 Errata V0.2 for IT8172G V0.6 Note: The corrections have been highlighted in red in the corresponding pages attached. Errata Version Section Correction Page 0.2 4 In Table 4-2, the signal VLMDOWN/GPIO14 should be corrected to VLMDOWN/GPIO13 and the signal VLMMUTE/GPIO13 should be corrected to VLMMUTE/ GPIO14. 15 0.1 1 • In the ATA 33 IDE Bus Controller features, one note will be added: There is one special condition in PCI IDE Function Bit Decoding. Please refer to the IT8172G Application Note, ITTM-AN-01040. 1 6 • In Table 6-7, added one note for IDE Controller: “There is one special condition in PCI IDE Function Bit Decoding. Please refer to the IT8172G Application Note, ITTM-AN-01040.” 39 1 IT8172G V0.6 Errata 02 Released on 6/17/2002 Pin Configuration Table 4-2. Pin-out Tables in Alphabetical Order [continued] Signal MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 Pin AC18 AD18 AF20 AE20 AD19 AE21 AB26 Y24 AA26 W24 V23 V24 V25 T22 Signal PAR PCA0/FRA0 PCA1/FRA1 PCA2/FRA2 PCA3/FRA3 PCA4/FRA4 PCA5/FRA5 PCA6/FRA6 PCA7/FRA7 PCA8/FRA8 PCA9/FRA9 PCA10/FRA10 PCA11/FRA11 PCA12/FRA12 Pin K3 AC8 AE8 AF7 AD8 AE7 AF6 AD7 AE6 AF5 AF4 AE5 AD6 AC7 MWE# AF23 PCA13/FRA13 AF3 NMI# PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 C26 G4 E1 F2 G3 H4 F1 G2 H3 G1 H2 J3 L5 H1 PCA14/FRA14 PCA15/FRA15 PCA16/FRA16 PCA17/FRA17 PCA18/FRA18 PCA19/FRA19 PCA20/FRA20 PCA21/FRA21 PCA22/FRA22 PCA23/FRA23 PCA24/FRA24 PCA25/FRA25 PCAS# PCD0/FRD0 AE4 AD5 AC6 AF2 AE3 AD4 AC5 AF1 AE2 AD3 AC4 AE1 AE16 AF11 Signal PCRW# PE PME# PPD0 PPD1 PPD2 PPD3 PPD4 PPD5 PPD6 PPD7 PWRBTM PWRON# RAS# RDWR#/ VALIDIN#/EVALID# RDY#/RDRDY# REQ0# REQ1# REQ2# RESET# RI# ROMSIZ1 RTCRST# RTS# RXD SCRCLK0 SCRCLK1/GNT3# SCRIO0 SCRIO1/REQ3# PAD13 K4 PCD1/FRD1 AE11 SCRPFET0# PAD14 M5 PCD2/FRD2 AD11 PAD15 J2 PCD3/FRD3 AF10 PAD16 M3 PCD4/FRD4 AB11 PAD17 M2 PCD5/FRD5 AD10 PAD18 M1 PCD6/FRD6 AC9 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 N4 P5 N3 N2 N1 P4 P2 P1 R1 R5 R2 R3 R4 PCD7/FRD7 PCD8/FRD8 PCD9/FRD9 PCD10/FRD10 PCD11/FRD11 PCD12/FRD12 PCD13/FRD13 PCD14/FRD14 PCD15/FRD15 PCDS# PCICLK PCIRST# PCLK AD9 AB4 AC2 AA4 AB2 Y4 AA2 AA1 Y2 AF16 U4 W1 AD16 www.ite.com.tw SCRPFET1#/ REQ4# SCRPRES0# SCRPRES1#/ INTD# SCRRST0# SCRRST1#/ GNT4# SERIRQ SERR# SIZ0 SIZ1 SLCT SLIN# SPDIFO STB# STOP# SWRST# SZ0/CMD6 SZ1/CMD7 SZ2/CMD8 Pin AD15 D10 T1 A6 B7 C8 A7 A10 C11 E11 B11 D16 B16 AF25 Signal TCK TDI TDO TEST0 TEST1 TEST2 TEST3 TMS TRDY# TRST# TXD USBD1M USBD1P USBD2M Pin D5 A3 B4 D6 AD22 AC21 AE23 C4 L3 B3 D8 B18 D17 C18 K26 USBD2P P23 V3 U1 T3 M22 A5 D13 A16 C7 A4 A14 A15 B14 D14 A20 D18 B17 AB10 AB17 E10 E17 K5 K22 U5 U22 E12 E13 E14 E15 USBOVR# USBPEN# VCCRTC VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC5 VCC5 VCCH VLMDOWN/ GPIO13 VLMMUTE/ GPIO14 VLMUP/GPIO1 2 VSS B13 VSS M13 C15 VSS M14 C13 K2 AC15 AE15 B9 B10 B1 A8 K1 V26 L23 J25 L22 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS M15 N12 N13 N14 N15 P12 P13 P14 P15 R12 R13 R14 R15 A13 B15 C14 A19 A1 D4 B2 M12 IT8172G V0.6 Errata 02 Released on 6/17/2002 Features 1. Features n n n - The priority order of interrupt request lines can be assigned by software - Module interrupts can be masked on/off independently by setting the corresponding mask registers CPU Interface - Directly connects the following 32-bit RISC microprocessor interfaces • MIPS 5 – NEC Vr5432, QED RM5231, RM5230 • MIPS 4 – NEC Vr4310 • Hitachi – SH4 (7750) - Supports CPU bus frequency up to 100 MHz SDRAM Controller - 32-bit data bus interface - Supports two banks of SDRAM, up to 128 MB in size - Provides deep buffer for CPU to SDRAM burst transfer - Provides deep buffer for PCI to SDRAM burst transfer - Supports bus frequency at up to 100 MHz Flash/ROM Interface - Flash memory area support up to 64M bytes, with 8-bit, 16-bit and 32-bit data access capability - ROM area size up to 4M bytes, with 8-bit, 16-bit and 32-bit data access capability - Maximum 12 chip-select signals supported - Shared with 68K like peripheral bus n Peripheral Bus Controller* - Glueless 68K like bus interface - No external latch required for addressing - 8-bit and 16-bit data bus interface - Shared with the Flash/ROM Interface - Supports up to four DMA channels - Cycle posting to avoid performance hit from slow device n PCI Bus Controller - Provides CPU to PCI buffers for burst transfer - PCI arbiter supports up to 5 individual bus master devices - 33 MHz bus frequency - 32-bit data bus interface n Interrupt Controller - Supports a maskable interrupt (INT0#) to CPU - Supports a non-maskable interrupt (NMI#) to CPU for severe events n DMA Controller - Supports four channels request for LPC or ECP DMA mode data transfer - Supports PCI bus master accessing to SDRAM n Chaining DMA Controller - Supports four independent software DMA channels for transferring data between the SDRAM and PCI devices - Supports chaining and non-chaining modes - Supports rotating and fixed priority types n Timers - Two 16-bit auto-reload counters with pre-scale (1,1/4,1/8,1/16) from dividing of the CPU clock - Supports the interrupt generation upon the timer time-out - Provides one Watchdog timer to monitor VALIDOUT# signal n Smart Card Interface - Compliant with Personal Computer Smart Card (PC/SC) Working Group standard - Compliant with smart card (ISO 7816) protocols - Card present detection - Supports smart card insertion power on feature - Supports one programmable clock frequency, and 7.1 MHz and 3.5 MHz (Default) card clocks - Supports two channels of smart card interface - Supports T=0, T=1 protocol n ATA 33 IDE Bus Controller - One channel IDE controller for two devices - Supports master/DMA/slave mode IDE - Supports any 16-bit and 32-bit ordering access to IDE data port in bus-slave access mode - Built in with 8-level 32-bit post-write buffer - Built in with 16-level 16-bit pre-fetch buffer - Compatible with ATA/ATAPI-4 - Compatible to ANSI ATA proposal PIO modes 0, 1, 2, 3, 4 with flow control, DMA modes 0, 1, 2 and UDMA modes 0, 1, 2 Note 1. There are some special conditions. Please refer to the IT8172 Application Note V2.1, ITTM-AN-01033. Note 2. There is one special condition in PCI IDE Function Bit Decoding. Please refer to the IT8172G Application Note, ITTM-AN-01040. www.ite.com.tw 1 IT8172G V0.6 Errata 01 Released on 12/25/2001 n n n n n n n CPU Interface n n n n n Table 6-7. Mapping Relation between AD Lines and Device Function Function Bus Number Device Number Device Function AD Line Number CPU/PCI Bridge 0 0 0 11 0 0 0 0 0 0 1 1 1 1 1 1 0 Audio Digital Controller 12 1 DMA Controller 12 2 Chain-DMA Controller 12 3 USB Host 12 4 PCI/Internal Bus Bridge 12 5 IDE Controller* 12 12 0 1 6 68K Controller 0 2 - External Device #1 13 0 3 - External Device #2 14 0 4 - External Device #3 15 0 5 - External Device #4 16 0 6 - External Device #5 17 - External Device #6 18 - External Device #7 19 - External Device #8 20 - External Device #9 21 - External Device #10 22 - External Device #11 23 - External Device #12 24 25 0 0 0 0 0 0 0 7 8 9 10 11 12 13 0 14 - External Device #13 0 15 - External Device #14 26 0 16 - External Device #15 27 0 17 - External Device #16 28 0 18 - External Device #17 29 0 19 - External Device #18 30 0 20 - External Device #19 31 Type 1 Configuration Access – If the Bus Number field of CONFADDR is not 0, a Type 1 Configuration is performed on PCI bus. The CONFADDR[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to ″01″ to indicate a Type 1 Configuration cycle. All other AD lines are driven to 0. * There is one special condition in PCI IDE Function Bit Decoding. Please refer to the IT8172G Application Note, ITTM-AN-01040. www.ite.com.tw 39 IT8172G V0.6 Errata 01 Released on 12/25/2001