+Tel:021-58998693 S3C2510A01-GB80 S3C2510A 1 PRODUCT OVERVIEW PRODUCT OVERVIEW 1.1 OVERVIEW Samsung's S3C2510A 16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc. To efficiently support those network applications, S3C2510A provides the followings: 16/32-bit ARM940T RISC embedded with 4K-byte I-cache and 4K-byte D-cache, memory controller with 24-bit external address pins, one external bus master with bus request/acknowledge pins, two 10/100 Mbps Ethernet controllers, PCI & PC Card host/agent controller, AAL5 SAR and UTOPIA L1/L2, two port full/low speed USB host with root hub, one port USB function device with transceiver, six general-purpose DMAs, two high-speed UARTs, one console UART, DES and 3DES for IP security, IIC serial interface, interrupt controller, six 32-bit programmable timers, 30-bit watchdog timer, 64 programmable I/O ports, and four PLLs for clock generation. The S3C2510A is developed using an ARM940T core, 0.18um CMOS standard cells and a memory compiler. Its powerful, elegant and fully static design is suitable for various network applications. Also S3C2510A adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture). 1-1 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A 1.2 FEATURES The following integrated on-chip functions are described in detail in this user's manual: • 16/32-bit ARM940T RISC Embedded • IIC Serial Interface • 4K-byte I-Cache and 4K-byte D-Cache • Interrupt Controller • Memory Controller with 24-bit External Address Pins — 2 Banks of SDRAM for 16/32-bit Bus — 8 Banks of Flash/ROM/SRAM/External I/O for 8/16/32-bit Bus — One External Bus Master with Bus Request/Acknowledge Pins • Six 32-bit Programmable Timers • 30-bit Watchdog Timer • 64 Programmable I/O Ports — 8 General-Purpose I/O — 6 External Interrupt Request — 6 Timer Output — 4 External DMA Request — 4 External DMA Acknowledge — 21 SAR Signals — 15 UART Signals • Four PLLs for each ARM940T (166MHz), System (133MHz), PCI & PC Card Controller Clock (33/66MHz), USB Host/Device Clock (48MHz), and Ethernet PHY (20/25MHz). • CPU Operating Frequency: Up to 166MHz • AHB Bus Operating Frequency: Up to 133MHz • Package Type: 416 PBGA • Two 10/100 Mbps Ethernet Controllers • PCI Host/Agent Controller or CardBus (PCMCIA) Host/Agent Controller — PCI Host mode: 5 (or more) PCI Slots Interface for PCI Cards — PC Card Host mode: 1 PC Card Socket Interface for 16-bit PC Card or CardBus PC Card • AAL5 SAR and UTOPIA L1/L2 • 2 Port Full/Low Speed USB HOST with Root Hub. • 1 Port Full Speed USB Function with Transceiver Spec. 1.1 • Core Operating at 1.8V ±5 %, -40~85 C • I/O Operating at 3.3V ±5 %, -40~85 C • Six General-Purpose DMAs • 3.3V input/output levels, 5V tolerant only for PCI. • Two High-Speed UARTs • One Console UART • DES and 3DES for IP Security 1-2 o o +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW 1.3 BLOCK DIAGRAM 2-bank SDRAM 10/100 Ethernet MAC DMA 10/100 Ethernet MAC DMA 4KB D-Cache A H B ARM940T (166 MHz) I/F 133 MHz AHB BUS DMA USB Host Controller DMA APB Bridge DMA Sys. Bus Arbiter Memory Controller Console UART Interrupt Controller DES/ 3DES WDT Six GDMA 8-bank Flash/ROM/ SRAM/ Ext I/O External Bus Master High Speed UART 4KB I-Cache AAL5 SAR & Utopia L1/L2 PCI/PC Card Host/Agent Controller High Speed UART 133 MHz APB BUS I2C GPIOs USB 1.1 Function Six Timers REQ/ACK Clock Gen. & Reset Drv. with 4 PLLs 10 MHz OSC. 20 MHz or 25 MHz Figure 1-1. Block Diagram 1-3 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A ARM940T The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-ona-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software. Memory organization Memory system is composed of 8 ROM/SRAM/Flash/Ext I/O banks and 2 SDRAM banks. Each ROM bank is fixed with 16M-byte address range and is supported with multiplexed and non-multiplexed address/data bus capability. Each SDRAM bank is supported with 128 MByte. Two Ethernet Controllers The S3C2510A includes two Ethernet controllers, which enables the user to configure SOHO router, internet gateway, etc. The main features are as follows. — Buffered DMA (BDMA) engine using burst mode — BDMA Tx/Rx buffers (256-byte/256-byte) — MAC Tx/Rx FIFOs (80-byte/16-byte) to support re-transmit after collision without DMA request — Data alignment logic — Support for old and new media (compatible with existing 10M-bit/s networks) — 10/100 Mbps operation to increase price/performance options and to support phased conversions — Full IEEE 802.3 compatibility for existing applications — Media Independent interface (MII) or 7-wire interface — Station management (STA) signaling for external physical layer configuration and link negotiation — On-chip CAM (21 addresses) — Full-duplex mode for doubled bandwidth — Pause operation hardware support for full-duplex flow control — Long packet mode for specialized environments — Short packet mode for fast testing — PAD generation for ease of processing and reduced processing time 1-4 +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW PCI & PC Card Host/Agent Controller S3C2510A's PCI & PC Card Host/Agent Controller complies with the PCI Local Bus Specification rev. 2.2, PC Card Standard Release 7.2, and various design guides. PCI & PC Card Controller connects the ARM940T processor core and local system memory to the PCI bus or CardBus socket. The PCI bus or CardBus uses a 32bit multiplexed, address/data bus, and various control and error signals. Mis-aligned transfers are supported as well as burst transfers at the maximum data rate of 264MB/s @66MHz (132MB/s @33MHz). S3C2510A can function as a PCI(or CardBus) master(initiator) or target(slave), and function as PCI host bridge(or CardBus host bus adapter) referred to as "host mode" or PCI device(or CardBus PC Card) referred to as "agent mode". In host mode, it can be used as host/PCI bridge (or CardBus socket controller) on main board . But in agent mode, it can be used as PCI device on PCI card or CardBus device on CardBus PC Card. The PCI & PC Card Host Controller provides PCI bus arbitration for the S3C2510A and up to five other PCI bus masters (except PCI target-only devices). It can be disabled to allow for external PCI arbiter (if more than five PCI bus masters will be connected). The PCI & PC Card Host Controller has one integrated block for PCI interface and CardBus interface (common silicon) and it supports only one interface as defined by PCI_PCCDM(PC Card Mode) pin. And PCI_HOSTM pin signal forces PCI & PC Card Controller to operate in host mode or agent mode. Each modes can be set as followings. PCI Host Mode PCI_PCCDM = 0, PCI_HOSTM=1 PCI Agent Mode PCI_PCCDM = 0, PCI_HOSTM=0 CardBus PC Card Host Mode PCI_PCCDM = 1, PCI_HOSTM=1, CardBus PC Card is inserted 16-bit PC Card (PCMCIA) Host Mode PCI_PCCDM = 1, PCI_HOSTM=1, 16-bit PC Card is inserted CardBus PC Card Agent Mode PCI_PCCDM = 1, PCI_HOSTM=0 NOTE: Each mode is selected by PCI_PCCDM & PCI_HOSTM pin input and inserted card type The PCI & PC Card Host/Agent Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented for flow-through operation of PCI & PC Card read/write burst operation. And doorbell and mailbox registers, CLKRUN# central resource control logic, integrated pull-up resistors are also implemented. As a CardBus host mode, it supports only single PC Card slot and generates interface signals to PC Card powerswitch. CardBus Host Controller supports 16-bit PC Card (PCMCIA card) or CardBus PC Card. CardBus Host Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented. As a PCI/CardBus agent mode, it supports independent three address decoders and provides address translation mechanism to map AHB local memory from PCI bus through three address bars and vice-versa. To support power management, it complies with PCI Bus Power Management Interface Specification Rev. 1.1 and PCI Mobile Design Guide Ver. 1.1. And also it supports DMA operation with two-channel dedicated DMA to enhance the performance. 1-5 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW PCI Host/Agent Controller Features are as Follows — 32-bit, 33/66 MHz, 5V tolerant, Up to 264M-byte/sec @66MHz — PCI Local Bus Specification Rev.2.2 compliant — PCI Bus Power Management Interface Specification Rev.1.1 compliant — PCI Mobile Design Guide Ver.1.1 compliant — Mini PCI Specification Rev.1.0 compliant — Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant — Supports PCI PME# pin and wake-up by software — Round-robin PCI bus arbiter supports five external REQ#, GNT# pins — Two-channel dedicated DMA — Integrated pull-up resistors CardBus PC Card Host/Agent Controller Features (Common Silicon with PCI) are as Follows — 32-bit, 33 MHz, 3.3V, Up to 132M-byte/sec — PC Card Standard Release 7.1 compliant — PCI Bus Power Management Interface Specification Rev.1.1 compliant — PCI Mobile Design Guide Ver.1.1 compliant — Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant — Single PC Card slot interface with hot insertion and removal — Interface to 16-bit PC Card (PCMCIA card) or CardBus PC Card — Interface to PC Card power-switch like TI TPS2211A and MAXIM MAX1602 — Integrated slew-rate controlled buffers for the difference between PCI and CardBus — Advanced filtering on card detect lines provide 60 microseconds of noise immunity — Supports CardBus CSTSCHG pin and Socket Event (Status Changed registers) registers — Two-channel dedicated DMA — Integrated pull-up resistors — Common memory, attribute memory and I/O interface supported for 16-bit PC Card 16-bit PC Card Host Controller Features (Common Silicon with PCI) are as Follows — PC Card Standard Release 7.1 compliant — Advanced filtering on card detect lines provide 60 microseconds of noise immunity — Two-channel dedicated DMA 1-6 S3C2510A +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW AAL5 SAR and UTOPIA L1/L2 The S3C2510A SAR is a powerful, cost-effective solution for providing packet-to-ATM connectivity. Once a data packet is given to the S3C2510A SAR, the packet is translated into cells using either the AAL5 protocol or the null AAL protocol. Then, without further host intervention, the cells are transmitted using selected scheduling algorithms. The host is notified upon completion of the packet transmission. The S3C2510A SAR also receives cells from the PHY devices, reassembles them into packets, and notifies the host when a packet has arrived. All packets are queued in system memory. Misaligned transfers are supported for ease of implementing LANE and MPOA protocols without requiring any packet data movement. VP scheduling is supported, as well as the more common VC scheduling, allowing a mix of Permanent Virtual Path (PVP), Switched Virtual Path (SVP), Permanent Virtual Channel (PVC), and Switched Virtual Channel (SVC) connections. Some key features are as follow: — CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis — AAL0 (raw cells) and AAL5 segmentation and reassembly — Segments and reassembles data up to about 70Mbps via UTOPIA interface — Generates and verifies CRC-10 for OAM cells and AAL-3/4 cells — Concurrent OAM cells and AAL5 cells on each active connection — Simultaneous segmentation and reassembly of up to 32 connection with internal memory and up to 4K connection with external memory — On chip 8K-byte SRAM for internal connection memory — CAM for connection number mapping (up to 32 connections) — Packet sizes up to 64K-byte — Scatter and gather packet capability for large packets — Starts of Packet offset available for ease of implementing bridging and routing between different protocols — Big/little endian mode for packet payload — Glue-less UTOPIA level 2 interface (up to 7 PHYs). USB Host Controller S3C2510A supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible, USB Rev1.1 compatible, 2 down stream ports. Support for Full/Low Speed USB devices. The S3C2510A USB Host controller complies with OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information. The main features are as follows — USB specification 1.0 compliant — Full/Low speed operation support. — Root hub built in with 2 downstream ports. 1-7 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Universal Serial Bus (USB) Function Device The S3C2510A includes a USB controller that enables the customers to implement USB devices for telephony, audio, and other applications. The USB controller is intended for the full-speed signaling rate of 12Mbit/s. Additionally, the S3C2510A USB controller has following features: — A total of 5 endpoints: 1 control endpoint and 4 data endpoints that can support control, interrupt, bulk transaction. — Two data endpoints have 32-byte FIFO, two data endpoints have 64-byte FIFO. — General DMA supported Universal Asynchronous Receiver Transmitter (UART) The S3C2510A has one console-UART and two high-speed UART. Consol UART can be used as system configuration or debug port. Each high-speed UART can be used as modem interface or other high-speed applications. The most important features of high-speed UART are as follows — Programmable baud rates — 32-byte Transmit FIFO and 32-byte Receive FIFO — UART source clock selectable (Internal clock: MCLK2, External clock : EUCLK) — Auto baud rate detection — Infra-red (IR) transmit/receive — Insertion of one or two Stop bits per frame — Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers — Parity checking DES/3DES Accelerator The DES Accelerator is a hardware accelerator for execution of the Data Encryption Standard(DES) algorithms as defined in FIPS PUB 46-1, which is equivalent to the Data Encryption Algorithm(DEA) provided in ANSI x3.921981. The main features are as follows — DES or Triple DES mode — ECB or CBC mode — Encryption or decryption support — General DMA support Six General DMA Channels The S3C2510A has six general DMA channels, which can be used for data transfer between memory and peripherals (memory to peripherals, peripherals to memory) or within memory space (memory to memory). On-chip peripherals with general DMA service are the two high-speed UART, the DES and the USB controller. General DMA can also support four external DMA requests from DMA request pins (xGDMA_Req0 – xGDMA_Req3). General DMA can also support the programmable cycle counts of the external DMA acknowledge signals (xGDMA_Ack0 – xGDMA_Ack3). 1-8 +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Six Programmable Timer The S3C2510A has six programmable timers. Each timer has its related pin, which is shared with programmable I/O function. Each timer can be programmed two operation mode. One is interval mode and the other is toggle mode. In interval mode, the initial timer output is set to low and it is set to high for 1 cycle time when timeout is reached. therefore the timer output is shaped like pulse wave. In toggle mode, the timer output is toggled when timeout is reached. Hardware Watchdog Timer The S3C2510A includes a watchdog timer, which is capable of generating system reset when the timeout value is reached. The time value is ranged up to 2^30 system clock cycles. The watchdog timer is used to reset and restart the system when a system has failed due to software error or to wrong response of external device. Programmable Interrupt Controller The S3C2510A has one programmable interrupt controller, which arranges the 36 programmable interrupt sources by the programmable priority. The interrupt controller supports 36 maskable interrupt sources, where 30 interrupts are from internal interrupts and 6 interrupts are from external interrupts. The interrupt with the highest priority is reported to the CPU. Programmable I/O Port Controller The S3C2510A has 64 programmable I/O ports, which can be used for another function. If another function is enabled, its I/O functionality is disabled. Six external interrupt request, four external DMA request, four external DMA acknowledge, six timer outputs, 21 SAR signals, and 15 UART signals are multiplexed with I/O function. Each I/O port can be programmed as Input or Output. 2 I C Controller The S3C2510A has IIC controller, which enables the customer to implement a simple and cost effective inter-IC connection. The IIC bus is a two-wire synchronous serial interface consisting of one data (SDA) and one clock (SCL) line. The S3C2510A IIC controller operates in only single master mode. 1-9 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A 1.4 S3C2510A PIN LIST AND PAD TYPE Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type Group Pin Name Pin No. I/O Type Pad Type Description System Configurations (21) XCLK T3 I phic S3C2510A PLL Clock Source. If CLKSEL is Low, PLL output clock is used as the system clock. If CLKSEL is high, XCLK is used as the system clock. HCLKO M23 O phbst24 System clock output. The internal system clock is monitored via HCLKO. If SDRAM is used, this clock should be used SDRAM clock CLKSEL U1 I phic Clock Select for CPU PLL. If CLKSEL is low, CPU PLL clock is used as ARM940T source clock. If high, XCLK (External clock) is used. FILTER R2 AO PHY_FREQ Y2 I phic PHY clock frequency select for PHY PLL. 0 = 20MHz 1 = 25MHz PHY_CLKSEL U3 I phic Clock Select for PHY PLL If this pin is set to Low, the PHY PLL generates clock depending on PHY_FREQ state. The PHY PLL goes into power down mode with PHY_CLKSEL set to High. PHY_FILTER T2 AO PHY_CLKO AD12 O 1-10 poar50_ PLL filter pin for System PLL. abb If the PLL is used, 320pF capacitor should be connected between the pin and ground. poar50_ PLL filter pin for PHY PLL. abb If the PLL is used, 320pF capacitor should be connected between the pin and ground. phob8 PHY clock Out PHY PLL clock output can be monitored by PHY_CLKO. This clock is used as the external PHY source clock. +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description System Configurations (21) CLKMOD[1] CLKMOD[0] AB4 AC2 I phic The CLKMOD pin determines internal clock scheme of S3C2510A. When CLKMOD is “00”, the nfast clock mode is defined. In this mode, the same clock is used as CPU clock and system clock. When CLKMOD is “01” or “10”, the sync mode is defined. In this mode, the system clock is half frequency of the CPU clock. When CLKMOD is "11", the async clock mode is defined. In this mode, the CPU clock and system clock can operate independently as long as the CPU clock is faster than system clock. In this case, BUS_FREQ[2:0] pins should be 3b’000 to select PCI PLL, 3b’001 to select USB PLL for programmable setting. CPU_FREQ[2] CPU_FREQ[1] CPU_FREQ[0] AE1 I phic CPU Clock Frequency Selection. I phic System Bus Clock Frequency Selection. AD1 AC3 BUS_FREQ[2] BUS_FREQ[1] BUS_FREQ[0] AD2 nRESET AB2 I phis Not Reset. NRESET is the global reset input for the S3C2510A and nRESET must be held to "low" for at least 64 clock cycles for digital filtering. TMODE AF3 I phicd Test Mode. The TMODE pin setting is interpreted as follows: 0 = normal operating mode 1 = chip test mode. BIG W3 I phicd BIG endian mode select pin. When this pin is set to “0”, the S3C2510A operates in litte endian mode. When this pin is set to “1”, the S3C2510A operates in big endian mode. PCI_PCCDM AA2 I phic PCI(1'b0) or PC Card(1'b1) Mode Select of PCI & PC Card Controller PCI_HOSTM Y3 I phic Host (1'b1) or Agent (1'b0) Mode Select of PCI & PC Card Controller AB3 AC1 1-11 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. Memory Interface (80) ADDR[23:0] ADDR[10] B14 XDATA[31:0] 1-12 I/O Type Pad Type Description O phot20 Address bus. The 24-bit address bus covers the full 16 M word address range of each ROM/SRAM /FLASH and external I/O bank. In the SDRAM interface, ADDR[14:13] is always used as bank address of SDRAM devices. If SDRAM devices with 2 internal bank is used, ADDR[13] should be connected to the BA of SDRAM. If SDRAM devices with 4 internal bank is used, ADDR[14:13] should be connected to the BA[1:0] of SDRAM. ADDR[10]/AP is the auto precharge control pin. The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR[10]/AP. B phbsut20 External bi-directional 32bit data bus. The S3C2510A supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank. nSDCS[1] nSDCS[0] G24 F26 O phot20 Not chip select strobe for SDRAM. Two SDRAM banks are supported. nSDRAS E25 O phot20 Not row address strobe for SDRAM. NSDRAS signal is used for both SDRAM banks. nSDCAS E26 O phot20 Not column address strobe for SDRAM. NSDCAS signal is used for both SDRAM banks. CKE L24 O phob12 Clock Enable for SDRAM CKE is clock enable signal for SDRAM. nSDWE/nWE16 F23 O phot20 Not Write Enable for SDRAM or 16 bit ROM/SRAM. This signal is always used as write enable of SDRAM and is used as write enable of only 16-bit ROM/SRAM/Flash. (That is, It is not enabled for 8 bit Memory) +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Memory Interface (80) nEWAIT K25 I phicu Not External wait signal. This signal is activated when an external I/O device or ROM/SRAM/Flash banks need more access cycles than those defined in the corresponding control register. nMCS[7] nMCS[6] nMCS[5] nMCS[4] nMCS[3] nMCS[2] nMCS[1] nMCS[0] J24 H26 H25 J26 K24 J25 K23 K26 O phot20 Not ROM/SRAM/Flash/ External I/O Chip select. The S3C2510A supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks. B0SIZE[1] B0SIZE[0] AE3 AF2 I phic Bank 0 Data Bus Access Size. Bank0 is used for the boot program. You use these pins to set the size of the bank 0 data bus as follows: “01” = Byte, “10” = Half word, “11” = Word, and “00” = reserved. nOE G25 O phot20 Not output enable. Whenever a memory read access occurs, the nOE output controls the output enable port of the specific memory device. nWBE[3]/nBE/ DQM[3] nWBE[2]/nBE/ DQM[2] nWBE[1]/nBE/ DQM[1] nWBE[0]/nBE/ DQM[0] F25 O phot20 Not write byte enable or DQM for SDRAM Whenever a memory write access occurs, the nWBE output controls the write enable port of the specific memory device. DQM is data input/output mask signal for SDRAM. H24 G26 Description H23 1-13 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description Memory Interface (80) XBMREQ M24 I phicd External Bus Master request. An external bus master uses this pin to request the external bus. When it activates the XBMREQ, the S3C2510A drives the state of external bus pins to high impedance. This lets the external bus master take control of the external bus. When it has control, the external bus master assumes responsibity for SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2510A can get the control of the bus and the XBMACK goes “low”. XBMACK L26 O phob8 External bus Acknowledge. TCK AC5 I phic JTAG Test Clock. The JTAG test clock shifts state information and test data into, and out of, the S3C2510A during JTAG test operations. TMS AE4 I phicu JTAG Test Mode Select. This pin controls JTAG test operations in the S3C2510A. This pin is internally connected pull-up. TDI AF4 I phicu JTAG Test Data In. The TDI level is used to serially shift test data and instructions into the S3C2510A during JTAG test operations. This pin is internally connected pull-up. TDO AD4 O phot12 nTRST AE5 I phicu TAP Control (5) 1-14 JTAG Test Data Out. The TDO level is used to serially shift test data and instructions out of the S3C2510A during JTAG test operations. JTAG Not Reset. Asynchronous reset of the JTAG logic. This pin is internally connected pull-up. +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description Ethernet Controller (2) MDC B1 O phob12 Management Data Clock. The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal. MDIO C2 B phbcut12 Management Data I/O. When a read command is being executed, data that is clocked out of the PHY is presented on this pin. When a write command is being executed, data that is clocked out of the controller is presented on this pin for the Physical Layer Entity, PHY. COL_0 C1 I phis Collision Detected/Collision Detected for 10M. COL is asserted asynchronously with minimum delay from the start of a collision on the medium in MII mode. COL_10M is asserted when a 10-Mbit/s PHY detects a collision. TX_CLK_0 D2 I phis Transmit Clock/Transmit Clock for 10M. The controller drives TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII mode, the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the 10M-bit/s PHY. TXD0[3] TXD0[2] TXD0[1]/ LOOP_10M TXD0[0]/ TXD_10M E4 E2 D1 O phob12 Transmit Data/Transmit Data for 10M. Transmit data is aligned on nibble boundaries. TXD[0] corresponds to the first bit to be transmitted on the physical medium, which is the LSB of the first byte and the fifth bit of that byte during the next clock. TXD_10M is shared with TXD[0] and is a data line for transmitting to the 10M-bit/s PHY. LOOP_10M is shared with TXD[1] and is driven by the loop-back bit in the control register. TX_EN_0 E3 O phob4 Transmit Enable/Transmit Enable for 10M. TX_EN provides precise framing for the data carried on TXD[3:0]. This pin is active during the clock periods in which TXD[3:0] contains valid data to be transmitted from the preamble stage through CRC. When the controller is ready to transfer data, it asserts TXEN_10M. Ethernet Controller0 (16) D3 1-15 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description Ethernet Controller0 (16) TX_ERR_0/ PCOMP_10M E1 O phob4 Transmit Error/Packet Compression Enable for 10M. TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY. If asserted for one or more TX_CLK periods, TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. PCOMP_10M is asserted immediately after the packet’s DA field is received. PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller (from National Semiconductor). The MAC can be programmed to assert PCOMP if there is a CAM match, or if there is not a match. The RIC (Repeater Interface Controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (See the DP83950 Data Sheet, published by National Semiconductor, for details on the RIC Management Bus.) This pin is controlled by a special register, with which you can define the polarity and assertion method (CAM match active or not match active) of the PCOMP signal. CRS_0 F2 I phis Carrier Sense/Carrier Sense for 10M. CRS is asserted asynchronously with minimum delay from the detection of a nonidle medium in MII mode. CRS_10M is asserted when a 10-Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also uses this signal. RX_CLK_0 F4 I phis Receive Clock/Receive Clock for 10M. RX_CLK is a continuous clock signal. Its frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are driven by the PHY off the falling edge of RX_CLK, and sampled on the rising edge of RX_CLK. To receive data, the RXCLK_10 M clock comes from the 10Mbit/s PHY. 1-16 +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description Ethernet Controller0 (16) RXD0[3] RXD0[2] RXD0[1] RXD0[0]/ RXD_10M G1 G2 F1 F3 I phis Receive Data/Receive Data for 10M. RXD is aligned on nibble boundaries. RXD[0] corresponds to the first bit received on the physical medium, which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock. RXD_10M is shared with RXD[0] and it is a line for receiving data from the 10M-bit/s PHY. RX_DV_0/ LINK_10M G3 I phis Receive Data Valid. PHY asserts RX_DV synchronously, holding it active during the clock periods in which RXD[3:0] contains valid data received. PHY asserts RX_DV no later than the clock period when it places the first nibble of the start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV prior to the first nibble of the SFD, then RXD[3:0] carries valid preamble symbols. LINK_10M is shared with RX_DV and used to convey the link status of the 10M-bit/s endec. The value is stored in a status register. RX_ERR_0 H2 I phisd Receive Error. PHY asserts RX_ERR synchronously whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV. COL_1 H4 I phis Collision Detected/Collision Detected for 10M. TX_CLK_1 H1 I phis Transmit Clock/Transmit Clock for 10M. TXD1[3] TXD1[2] TXD1[1]/ LOOP_10M TXD1[0]/ TXD_10M K2 J1 J2 H3 O phob12 Transmit Data/Transmit Data for 10M. TX_EN_1 J3 O phob4 Transmit Enable/Transmit Enable for 10M. TX_ERR_1/ PCOMP_10M K1 O phob4 Transmit Error/Packet Compression Enable for 10M. CRS_1 K4 I phis Carrier Sense/Carrier Sense for 10M. RX_CLK_1 L2 I phis Receive Clock/Receive Clock for 10M. Ethernet Controller1 (16) 1-17 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Ethernet Controller1 (16) RXD1[3] RXD1[2] RXD1[1] RXD1[0]/ RXD_10M M1 I phis Receive Data/Receive Data for 10M. RX_DV_1/ LINK_10M L3 I phis Receive Data Valid. RX_ERR_1 N2 I phisd Receive Error. PCI & PCICLK1 AA23 O phopcicb PCI clock output signal 1 PC Card PCICLK2 AE24 O phopcicb PCI clock output signal 2 Controller – PCICLK3/ EXT_PCICLK AD18 B phtbpcicb PCI clock output signal 3 or external PCI clock input PCI Host Mode PCIRST#/ EXT_PCIRST# AE19 B phtbpcicb PCI reset signal (65) REQ#/REQ#[1] AF22 B phtbpcicbu PCI bus request signal REQ#[2] AD21 I phtipcicbu REQ#[5] REQ#[4] REQ#[3] AC19 AE20 I (B) GNT#/GNT#[1] AC21 B GNT#[3] GNT#[2] AD20 AE21 O(B) phtbpcicb PCI bus grant signals GNT#[5] GNT#[4] AD19 AF20 O photcicb PCI bus grant signals 1-18 M2 Description L1 K3 PCI bus request signals phtbpcicbu PCI bus request signals AF21 phtbpcicbu PCI bus grant signal +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name PCI & AD[31:0] PC Card Controller – PCI Host C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] Mode (65) Pin No. I/O Type Pad Type Description B phtbpcicb PCI address / data 32-bit lines AD26 AA26 V26 T24 B phtbpcicb Command / byte enable 4-bit lines PAR W23 B phtbpcicb Even parity signal FRAME# AA25 B phtbpcicbu Signal indicating duration of access IRDY# AA24 B phtbpcicbu Signal indicating the master is ready TRDY# Y26 B phtbpcicbu Signal indicating the target is ready DEVSEL# Y25 B phtbpcicbu Target device selected signal STOP# Y24 B phtbpcicbu Stop signal for disconnect or retry LOCK# W26 O(B) phtbpcicbu Lock signal (always pull-up) PERR# W25 B phtbpcicbu Parity error report signal SERR# W24 I(BD) phtbdpcicbu System error report signal INTA# AF19 I(BD) phtbdpcicbu Level-sensitive Interrupt signal PME# AE22 I (B) phtbpcicbu PCI Power Management Event signal CLKRUN# L25 B phtbpcicbu PCI clock speed control signal PCI_XCLK AA3 I phic S3C2510A PCI PLL Clock Source. It can be system bus clock if BUS_FREQ[2:0] select PCI clock. PCI_CLKSEL AB1 I phic Clock Select for PCI PLL. If this pin is low, PCI PLL on. If high, PCI PLL off. PCI_FILTER R4 AO poar50_abb PLL filter pin for PCI PLL. • PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). • When in PCI host mode (PCI_PCCDM=0, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to PCI host signals as above. Extra 4 pins (PCICVS[2:1], PCICCD[2:1]) are not used in this mode. • These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to “S3C2510A PCI / PC Card Signals Reference Table”. 1-19 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description PCI & EXT_PCICLK AD18 I (B) phtbpcicb External PCI clock input PC Card EXT_PCIRST# AE19 B phtbpcicb PCI reset signal Controller REQ# AF22 O(B) phtbpcicbu PCI bus request signal – GNT# AC21 I (B) phtbpcicbu PCI bus grant signal PCI Agent IDSEL AD21 I phtipcicbu PCI Initialization Device Select signal Mode AD[31:0] B phtbpcicb PCI address / data 32-bit lines (53) C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] AD26 AA26 V26 T24 B phtbpcicb Command / byte enable 4-bit lines PAR W23 B phtbpcicb Even parity signal FRAME# AA25 B phtbpcicbu Signal indicating duration of access IRDY# AA24 B phtbpcicbu Signal indicating the master is ready TRDY# Y26 B phtbpcicbu Signal indicating the target is ready DEVSEL# Y25 B phtbpcicbu Target device selected signal STOP# Y24 B phtbpcicbu Stop signal for disconnect or retry LOCK# W26 I (B) phtbpcicbu Lock signal PERR# W25 B phtbpcicbu Parity error report signal SERR# W24 OD (BD) phtbdpcicbu System error report signal INTA# AF19 OD (BD) phtbdpcicbu Level-sensitive Interrupt signal PME# AE22 O(B) phtbpcicbu PCI Power Management Event signal CLKRUN# L25 O(B) phtbpcicbu PCI clock speed control signal • PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). • When in PCI agent mode (PCI_PCCDM=0, PCI_HOSTM=0), PCI & PC Card controller pins are mapped to PCI agent (general PCI device) signals as above. Extra 16 pins (PCICLK[2:1], PCIREQ[5:3], PCIGNT[5:2], PCICVS[2:1], PCICCD[2:1], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. • These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to “S3C2510A PCI / PC Card Signals Reference Table”. 1-20 +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description PCI & PC Card CCLK / EXT_CCLK AD18 B phtbpcicb CardBus clock output or external clock input Controller – CRST# / EXT_CRST# AE19 B phtbpcicb CardBus reset signal CardBus CREQ# AF22 I (B) phtbpcicbu CardBus bus request signal PC Card CGNT# AC21 O (B) phtbpcicbu CardBus bus grant signal Host Mode CAD[31:0] B phtbpcicb CardBus address / data 32-bit lines (63) C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] AD26 AA26 V26 T24 B phtbpcicb Command / byte enable 4-bit lines CPAR W23 B phtbpcicb Even parity signal CFRAME# AA25 B phtbpcicbu Signal indicating duration of access CIRDY# AA24 B phtbpcicbu Signal indicating the master is ready CTRDY# Y26 B phtbpcicbu Signal indicating the target is ready CDEVSEL# Y25 B phtbpcicbu Target device selected signal CSTOP# Y24 B phtbpcicbu Stop signal for disconnect or retry CBLOCK# W26 O (B) phtbpcicbu Lock signal (always pull-up) CPERR# W25 B phtbpcicbu Parity error report signal CSERR# W24 I (BD) phtbdpcicbu System error report signal CINT# AF19 I (BD) phtbdpcicbu Level-sensitive Interrupt signal CSTSCHG AE22 I (B) phtbpcicbu CardBus Status Changed signal CLKRUN# L25 B phtbpcicbu CardBus clock speed control signal CVS[2] CVS[1] N25 N24 B phbcbcvs CardBus Voltage Sense signal lines CCD#[2] CCD#[1] M26 M25 I phicbccd CardBus Card Detect signal lines VCCD[0] AE20 O (B) phtbpcicbu CardBus Power-Switch VCC control signal VCCD[1] AF20 O phopcicb CardBus Power-Switch VCC control signal VPPD_VCC AC19 O (B) phtbpcicbu CardBus Power-Switch VPP control signal VCC Voltage (5V/3.3V) VPPD_PGM AD19 O phopcicb CardBus Power-Switch VPP control signal Higher Voltage (12V) PCI_XCLK AA3 I phic S3C2510A PCI PLL Clock Source. PCI_CLKSEL AB1 I phic Clock Select for PCI PLL. PCI_FILTER R4 AO poar50_abb PLL filter pin for PCI PLL. 1-21 +Tel:021-58998693 S3C2510A01-GB80 PRODUCT OVERVIEW S3C2510A • PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). • When CardBus PC Card is inserted in CardBus PC Card host mode (PCI_PCCDM=1, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to CardBus PC Card host signals as above. Extra 6 pins (PCICLK1, PCICLK2, PCIREQ2, PCIREQ3, PCIGNT2, PCIGNT3) are not used in this mode. • These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table". Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description PCI & EXT_CCLK AD18 I (B) phtbpcicb External CardBus clock PC Card EXT_CRST# AE19 B phtbpcicb CardBus reset signal Controller CREQ# AF22 O (B) phtbpcicbu CardBus bus request signal – CGNT# AC21 I (B) phtbpcicbu CardBus bus grant signal CardBus CAD[31:0] B phtbpcicb CardBus address / data 32-bit lines PC Card Agent Mode (53) CC/BE#[3] AD26 B phtbpcicb Command / byte enable 4-bit lines CC/BE#[2] AA26 CC/BE#[1] V26 CC/BE#[0] T24 CPAR W23 B phtbpcicb Even parity signal CFRAME# AA25 B phtbpcicbu Signal indicating duration of access CIRDY# AA24 B phtbpcicbu Signal indicating the master is ready CTRDY# Y26 B phtbpcicbu Signal indicating the target is ready CDEVSEL# Y25 B phtbpcicbu Target device selected signal CSTOP# Y24 B phtbpcicbu Stop signal for disconnect or retry CBLOCK# W26 I (B) phtbpcicbu Lock signal CPERR# W25 B phtbpcicbu Parity error report signal CSERR# W24 OD (BD) phtbdpcicbu System error report signal CINT# AF19 OD (BD) phtbdpcicbu Level-sensitive Interrupt signal CSTSCHG AE22 O (B) phtbpcicbu CardBus Status Changed signal CLKRUN# L25 O (B) phtbpcicbu CardBus clock speed control signal GWA_EVENT AD21 I phtipcicbu External General Wakeup Event signal • PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). • When CardBus PC Card is inserted in CardBus PC Card agent mode (PCI_PCCDM=1, PCI_HOSTM=0), PCI & PC Card controller pins are mapped to CardBus PC Card agent signals as above. Extra 16 pins (PCICLK[2:1], PCIREQ[5:3], PCIGNT[5:2], PCICVS[2:1], PCICCD[2:1], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. • These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table". 1-22 +Tel:021-58998693 S3C2510A01-GB80 S3C2510A PRODUCT OVERVIEW Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Pin Name Pin No. I/O Type Pad Type Description PCI & PCRESET AE19 O(B) phtbpcicb 16-bit PC Card reset signal PC Card PCADDR[25:0] O(B) phtbpcicb 16-bit PC Card address lines Controller PCDATA[15:0] B phtbpcicb 16-bit PC Card data lines – 16-bit CE#[2] CE#[1] U23 T24 O(B) phtbpcicb Card enable signals (even and odd address) PC Card REG# AD26 O(B) phtbpcicb Attribute memory select signal (PCMCIA) Host Mode OE# U24 O(B) phtbpcicb Output enable signal of memory read cycles. (64) WE# AC21 O(B) phtbpcicb Write enable signal of memory write cycles IORD# U26 O(B) phtbpcicb I/O read signal of I/O read cycles IOWR# V25 O(B) phtbpcicb I/O write signal of I/O write cycles WAIT# W24 I(BD) phtbdpcicbu 16-bit PC Card bus cycle wait signal READY (IREQ#) AF19 I(BD) phtbdpcicbu Ready signal of memory interface or Interrupt request signal of I/O interface INPACK# AF22 I (B) phtbpcicbu Input acknowledge signal of I/O read cycles WP(IOIS16#) L25 I (B) phtbpcicbu Write protect signal of memory interface or 16bit I/O indicating signal of I/O interface BVD[1] (STSCHG#) AE22 I (B) phtbpcicbu Battery voltage detect 1 signal or Status change interrupt signal BVD[2] (SPKR#) AD21 I phtipcicbu Battery voltage detect 2 signal VS#[2] VS#[1] N25 N24 B phbcbcvs PC Card Voltage Sense signal lines CD#[2] CD#[1] M26 M25 I phicbccd PC Card Card Detect signal lines VCCD[0] AE20 O(B) phtbpcicbu PC Card Power-Switch VCC control signal VCCD[1] AF20 O phopcicb PC Card Power-Switch VCC control signal VPPD_VCC AC19 O(B) phtbpcicbu PC Card Power-Switch VPP control signals VCC Voltage (5V/3.3V) VPPD_PGM AD19 O phopcicb PC Card Power-Switch VPP control signals Higher Voltage (12V) • PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). • When 16-bit PC Card (PCMCIA card) is inserted in PC Card host mode (PCI_PCCDM=1, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to 16-bit PC Card host (PCMCIA host) signals as above. Extra 5 pins (PCICLK[3:2], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. • These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table". • PCI & PC Card controller doesn’t support 16-bit PC Card agent (PCMCIA card) mode. 1-23