Holtek 32-bit Microcontroller with ARM® Cortex™-M3 Core HT32F1755/HT32F1765/HT32F2755 Datasheet Revision: V1.00 Date: ��������������� August 13, 2012 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Table of Contents 1 General Description................................................................................................. 6 2 Features.................................................................................................................... 7 Core........................................................................................................................................ 7 Flash Memory Controller........................................................................................................ 8 Reset Control Unit.................................................................................................................. 8 Clock Control Unit................................................................................................................... 8 Power Management................................................................................................................ 9 Analog to Digital Converter..................................................................................................... 9 Analog Operational Amplifier/Comparator.............................................................................. 9 I/O Ports................................................................................................................................ 10 PWM Generation and Capture Timers – GPTM................................................................... 10 Motor Control Timer – MCTM............................................................................................... 11 Basic Function Timer – BFTM.............................................................................................. 11 Watchdog Timer.................................................................................................................... 12 Real Time Clock.................................................................................................................... 12 Inter-integrated Circuit – I2C................................................................................................. 13 Serial Peripheral Interface – SPI.......................................................................................... 13 Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 14 Smart Card Interface – SCI.................................................................................................. 14 Peripheral Direct Memory Access – PDMA.......................................................................... 15 Universal Serial Bus Device Controller – USB..................................................................... 15 CMOS Sensor Interface – CSIF (HT32F2755 only)............................................................. 16 Debug Support...................................................................................................................... 16 Package and Operation Temperature................................................................................... 16 3 Overview................................................................................................................. 17 Device Information................................................................................................................ 17 Block Diagram...................................................................................................................... 18 Memory Map......................................................................................................................... 19 Clock Structure..................................................................................................................... 20 Pin Assignment..................................................................................................................... 21 Rev. 1.00 2 of 45 August 13, 2012 Table of Contents On-chip Memory..................................................................................................................... 7 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 4 Electrical Characteristics...................................................................................... 28 Absolute Maximum Ratings.................................................................................................. 28 Recommended DC Characteristics...................................................................................... 28 On-Chip LDO Voltage Regulator Characteristics.................................................................. 28 Power Consumption............................................................................................................. 29 External Clock Characteristics.............................................................................................. 30 Internal Clock Characteristics............................................................................................... 31 PLL Characteristics............................................................................................................... 31 Memory Characteristics........................................................................................................ 31 I/O Port Characteristics......................................................................................................... 32 ADC Characteristics............................................................................................................. 33 Operation Amplifier/Comparator Characteristics.................................................................. 35 GPTM/MCTM Characteristics............................................................................................... 35 I2C Characteristics................................................................................................................ 36 SPI Characteristics............................................................................................................... 37 CSIF Characteristics............................................................................................................. 38 USB Characteristics.............................................................................................................. 39 5 Package Information............................................................................................. 41 48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 41 64-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 43 100-pin LQFP (14mm×14mm) Outline Dimensions.............................................................. 44 Rev. 1.00 3 of 45 August 13, 2012 Table of Contents Reset and Supply Monitor Characteristics............................................................................ 29 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 List of Tables Rev. 1.00 1. HT32F1755/1765/2755 Series Features and Peripheral List.................................................... 17 2. HT32F1755/1765/2755 Pin Descriptions.................................................................................. 24 3. Absolute Maximum Ratings....................................................................................................... 28 4. Recommended DC Operating Conditions................................................................................. 28 5. LDO Characteristics.................................................................................................................. 28 6. Power Consumption Characteristics......................................................................................... 29 7. LVD/BOD Characteristics.......................................................................................................... 29 8. High Speed External Clock (HSE) Characteristics.................................................................... 30 9. Low Speed External Clock (LSE) Characteristics..................................................................... 30 10. High Speed Internal Clock (HSI) Characteristics.................................................................... 31 11. Low Speed Internal Clock (LSI) Characteristics...................................................................... 31 12. PLL Characteristics................................................................................................................. 31 13. Flash Memory Characteristics................................................................................................. 31 14. I/O Port Characteristics........................................................................................................... 32 15. ADC Characteristics................................................................................................................ 33 16. OPA/CMP Characteristics....................................................................................................... 35 17. GPTM/MCTM Characteristics................................................................................................. 35 18. I2C Characteristics................................................................................................................... 36 19. SPI Characteristics.................................................................................................................. 37 20. CSIF Characteristics............................................................................................................... 38 21. USB DC Electrical Characteristics.......................................................................................... 39 22. USB AC Electrical Characteristics........................................................................................... 40 4 of 45 August 13, 2012 List of Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 List of Figures Rev. 1.00 1. HT32F1755/1765/2755 Block Diagram................................................................................... 18 2. HT32F1755/1765/2755 Memory Map...................................................................................... 19 3. HT32F1755/1765/2755 Clock Structure.................................................................................. 20 4. HT32F1755/1765/2755 48-LQFP Pin Assignment.................................................................. 21 5. HT32F1755/1765/2755 64-LQFP Pin Assignment.................................................................. 22 6. HT32F1755/1765/2755 100-LQFP Pin Assignment................................................................ 23 7. ADC Sampling Network Model................................................................................................ 34 8. I2C Timing Diagrams................................................................................................................ 36 9. SPI Timing Diagrams – SPI Master Mode............................................................................... 37 10. SPI Timing Diagrams – SPI Slave Mode and CPHA=1......................................................... 38 11. USB Signal Rise Time and Fall time and Cross-Point Voltage (VCRS) Definition.................... 40 5 of 45 August 13, 2012 List of Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 1 General Description The Holtek HT32F1755/1765/2755 devices are high performance and low power consumption 32-bit microcontrollers based around an ARM® Cortex™-M3 processor core. The Cortex™-M3 is a next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer, and including advanced debug support. The above features ensure that the HT32F1755/1765/2755 devices are suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control, fingerprint recognition and so on. Rev. 1.00 6 of 45 August 13, 2012 General Description The HT32F1755/1765/2755 devices operate at a frequency of up to 72MHz with a Flash accelerator to obtain maximum efficiency. It provides 128KB of embedded Flash memory for code/data storage and up to 64KB of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as ADC, I 2C, USART, SPI, PDMA, GPTM, MCTM, SCI, CSIF, USB2.0 FS, SWJ-DP (Serial Wire and JTAG Debug Port), etc., are also implemented in the device series. Several power saving modes provide the flexibility for maximum optimisation between wakeup latency and power consumption, an especially important consideration in low power applications. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 2 Features Core On-chip Memory ▀ 128KB on-chip Flash memory for instruction/data and options storage ▀ up to 64KB on-chip SRAM ▀ Supports multiple boot modes The ARM® Cortex™-M3 processor is structured using a Harvard architecture which uses separate busses to fetch instructions and load/store data. The instruction code and data are both located in the same memory address space but in different address ranges. The maximum address range of the Cortex™-M3 is 4GB due to its 32-bit bus address width. Additionally, a pre-defined memory map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated implementation for different device vendors. However, some regions are used by the ARM® Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference Manual for more information. The Figure 2. shows the memory map of the HT32F1755/1765/2755 series of devices, including Code, SRAM, peripheral, and other pre-defined regions. Rev. 1.00 7 of 45 August 13, 2012 Features ® ▀ 32-bit ARM Cortex™-M3 processor core ▀ Up to 72MHz operation frequency ▀ 1.25 DMIPS/MHz (Dhrystone 2.1) ▀ Single-cycle multiplication and hardware division ▀ Integrated Nested Vectored Interrupt Controller (NVIC) ▀ 24-bit SysTick timer The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for products requiring high performance and low power consumption microcontrollers. It offers many new features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Flash Memory Controller ▀ Flash accelerator for maximum efficiency ▀ 32-bit word programming with In System Programming Interface (ISP) and In Application Programming (IAP) ▀ Flash protection capability to prevent illegal access Reset Control Unit ▀ Supply supervisor: ● Power-on Reset – POR ● Brown-out Detector – BOD ● Programmable Low Voltage Detector – LVD The Reset Control Unit (RSTCU) has three kinds of reset, the power on reset, system reset and an APB unit reset. The power on reset, known as a cold reset, resets the full system during power up. A system reset resets the processor core and peripheral IP components with the exception of the SWJ-DP controller. The resets can be triggered by an external signal, internal events and the reset generators. Clock Control Unit ▀ External 4 to 16MHz crystal oscillator ▀ External 32,768Hz crystal oscillator ▀ Internal 8MHz RC oscillator trimmed to ±2% accuracy at 3.3V operating voltage and 25°C operating temperature ▀ Internal 32kHz RC oscillator ▀ Integrated system clock PLL ▀ Independent clock gating bits for peripheral clock sources The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry. The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS) which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use either the LSI or LSE as their clock source. The maximum operating frequency of the system core clock (CK_AHB) can be up to 72MHz. Rev. 1.00 8 of 45 August 13, 2012 Features The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory word program/page erase functions are also provided. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Power Management Analog to Digital Converter ▀ 12-bit SAR ADC engine ▀ Up to 1Msps conversion rate – 1μs at 56MHz, 1.17μs at 72MHz ▀ 8 external analog input channels ▀ Supply voltage range: 2.7V ~ 3.6V ▀ Conversion range: VREF+ ~ VREFA 12-bit multi-channel ADC is integrated in the device. There are a total of 10 multiplexed channels, which include 8 external channels on which the external analog signals can be measured, and 2 internal channels. If the input voltage is required to remain within a specific threshold window, an Analog Watchdog function will monitor and detect these signals. An interrupt will then be generated to inform the device that the input voltage is not within the preset threshold levels. There are three conversion modes to convert an analog signal to digital data. The ADC can be operated in one shot, continuous and discontinuous conversion modes. Analog Operational Amplifier/Comparator ▀ Two Operational Amplifiers or Comparator functions which are software configurable ▀ Supply voltage range: 2.7V ~ 3.6V Two Operational Amplifiers/Comparators (OPA/CMP) are implemented within the devices. They can be configured either as Operational Amplifiers or as Analog Comparators. When configured as comparators, they are capable of generating interrupts to the NVIC. Rev. 1.00 9 of 45 August 13, 2012 Features ▀ Single 3.3V power supply: 2.7V to 3.6V ▀ Integrated 1.8V LDO regulator for core and peripheral power supply ▀ VBAT battery power supply for RTC and backup registers ▀ Three power domains: 3.3V, 1.8V and Backup ▀ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down The Power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode. These operating modes reduce the power consumption and allow the application to achieve the best trade-off between the conflicting demands of CPU operating time, speed and power consumption. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 I/O Ports The GPIO ports are pin-shared with other alternative functions to obtain maximum functional flexibility on the package pins. The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the input or output pins. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit, EXTI. PWM Generation and Capture Timers – GPTM ▀ Two 16-bit General-Purpose Timers – GPTM ▀ Up to 4-channel PWM Compare Output or Input Capture function for each GPTM ▀ External trigger input T he General-P u r pose Timers, k now n as GPTM0 and GPTM1, consist of one 16 -bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. They can be used for a variety of purposes including general time measurement, input signal pulse width measurement, output waveform generation such as single pulse generation, or PWM output generation. The GPTM supports an Encoder Interface using a decoder with two inputs. Rev. 1.00 10 of 45 August 13, 2012 Features ▀ Up to 80 GPIOs ▀ Port A, B, C, D, E are mapped as 16 external interrupts – EXTI ▀ Almost all I/O pins are 5V-tolerant except for pins shared with analog inputs There are up to 80 General Purpose I/O pins, (GPIO), named PA0 ~ PA15 to PE0 ~ PE15 for the implementation of logic input/output functions. Each of the GPIO ports has a series of related control and configuration registers to maximise flexibility and to meet the requirements of a wide range of applications. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Motor Control Timer – MCTM The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs (Capture/Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter and several control/status registers. It can be used for a variety of purposes including measuring the pulse widths of input signals or generating output waveforms such as compare match outputs, PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM supports an Encoder interface controller to an incremental encoder with two inputs. The MCTM is capable of offering full functional support for motor control, hall sensor interfacing and brake input. Basic Function Timer – BFTM ▀ Two 32-bit compare/match count-up counters – no I/O control features ▀ One shot mode – counting stops after a match condition ▀ Repetitive mode – restart counter after a match condition The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes, repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare match event occurs. The BFTM also supports a one shot mode which forces the counter to stop counting when a compare match event occurs. Rev. 1.00 11 of 45 August 13, 2012 Features ▀ Single 16-bit up, down, up/down auto-reload counter ▀ 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor between 1 and 65536 ▀ Input Capture function ▀ Compare Match Output ▀ PWM waveform generation with Edge and Centre-aligned Modes ▀ Single Pulse Mode Output ▀ Complementary Outputs with programmable dead-time insertion ▀ Encoder interface controller with two inputs using quadrature decoder ▀ Support 3-phase motor control and hall sensor interface ▀ Brake input to force the timer’s output signals into a reset or fixed condition 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Watchdog Timer Real Time Clock ▀ 32-bit up-counter with a programmable prescaler ▀ Alarm function ▀ Interrupt and Wake-up event The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit count-up counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in the Backup Domain except for the APB interface. The APB interface is located in the VDD18 power domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power control unit when the V DD18 power domain is powered off, that is when the device enters the Power-Down mode. The RTC counter is used as a wakeup timer to generate a system resume signal from the Power-Down mode. Rev. 1.00 12 of 45 August 13, 2012 Features ▀ 12-bit down counter with 3-bit prescaler ▀ Interrupt or reset event for the system ▀ Programmable watchdog timer window function ▀ Registers write protection function The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT counter value register, a WDT delta value register, interrupt related circuits, WDT operation control circuitry and a WDT protection mechanism. The Watchdog Timer can be operated in an interrupt mode or a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter counts down and reaches a zero value. If the software does not reload the counter value before a Watchdog Timer underflow occurs, an interrupt or a reset will be generated when the counter underflows. In addition, an interrupt or reset is also generated if the software reloads the counter when the counter value is greater than or equal to the WDT delta value. This means the counter must be reloaded within a limited timing window using a specific method. The Watchdog Timer counter can be stopped while the processor is in the debug mode. There is a register write protect function which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Inter-integrated Circuit – I2C The SDA line which is connected directly to the I2C bus is a bi-directional data line between the master and slave devices and is used for data transmission and reception. The I2C module also has an arbitration detect function and clock synchronization to prevent situations where more than one master attempts to transmit data to the I2C bus at the same time. Serial Peripheral Interface – SPI ▀ Supports both master and slave mode ▀ Frequency of up to 36MHz for master mode and 18MHz for slave mode ▀ FIFO Depth: 8 levels ▀ Multi-master and multi-slave operation The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device acts as a master device which controls the data flow using the SEL and SCK signals to indicate the start of data communication and the data sampling rate. To receive a data byte, the streamed data bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data transmission is carried in a similar way but with a reverse sequence. The mode fault detection provides a capability for multi-master applications. Rev. 1.00 13 of 45 August 13, 2012 Features ▀ Support both master and slave mode with a frequency of up to 1MHz ▀ Provide an arbitration function and clock synchronization ▀ Supports 7-bit and 10-bit addressing mode and general call addressing ▀ Supports slave multi-addressing mode with maskable address The I2C Module is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module provides three data transfer rates: (1). 100kHz in the Standard mode, (2). 400kHz in the Fast mode and, (3). 1MHz in the Fast mode plus. The SCL period generation register is used to setup different kinds of duty cycle implementation for the SCL pulse. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Universal Synchronous Asynchronous Receiver Transmitter – USART The USART includes a programmable baud rate generator which is capable of dividing the CK_AHB to produce a clock for the USART transmitter and receiver. Smart Card Interface – SCI ▀ Support ISO 7816-3 standard ▀ Character mode ▀ Single transmit buffer and single receive buffer ▀ 11-bit ETU (Elementary Time Unit) counter ▀ 9-bit guard time counter ▀ 24-bit general purpose waiting time counter ▀ Parity generation and checking ▀ Automatic character retry on parity error detection in transmission and reception modes The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication with the external Smart Card. The overall functions of the Smart Card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for SCI transfer status. Rev. 1.00 14 of 45 August 13, 2012 Features ▀ Operating frequency up to 4.5MHz ▀ Supports both asynchronous and clocked synchronous serial communication modes ▀ IrDA SIR encoder and decoder ▀ RS485 mode with output enable control ▀ Full Modem function for USART0 ▀ Auto hardware flow control mode – RTS, CTS ▀ FIFO Depth: 16×9 bits for both receiver and transmitter The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication. The USART peripheral function supports five types of interrupt including Line Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt, Time Out Interrupt and MODEM Status Interrupt. The USART module includes a 16-byte transmitter FIFO (TX_FIFO) and a 16-byte receiver FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status Register, LSR. The status includes the type and the condition of transfer operations as well as several error conditions resulting from Parity, Overrun, Framing and Break events. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 Peripheral Direct Memory Access – PDMA Universal Serial Bus Device Controller – USB ▀ Complies with USB 2.0 full-speed (12Mbps) specification ▀ On-chip USB full-speed transceiver ▀ 1 control endpoint (EP0) for control transfer ▀ 3 single-buffered endpoints for bulk and interrupt transfer ▀ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer ▀ 1024 bytes EP-SRAM used as the endpoint data buffers The USB device controller is compliant with USB 2.0 full-speed specification. There is one control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM is used as the endpoint buffers. Each endpoint buffer size is programmable using corresponding registers, which provides maximum flexibility for various applications. The integrated USB full-speed transceiver helps to minimise the overall system complexity and cost. The USB functional block also contains the resume and suspend features to meet the requirements of low-power consumption. Rev. 1.00 15 of 45 August 13, 2012 Features ▀ 12 channels with trigger source grouping ▀ Supports Single and block transfer mode ▀ 8/16/32-bit width data transfer ▀ Supports Address increment, decrement or fixed mode ▀ 4-level programmable channel priority ▀ Auto reload mode 2 ▀ Supports trigger source: CSIF, ADC, SPI, USART, I C, GPTM, MCTM, SCI and software The Peripheral Direct Memory Access controller, PDMA, moves data between the peripherals (USART, SPI, ADC, GPTM, MCTM, CSIF, I2C and SCI, CPU for software mode) and the system memory on the AHB bus. Each PDMA channel has a source address, destination address, block length and transfer count. The PDMA can exclude the CPU intervention and avoid interrupt service routine execution. It improves system performance as the software does not need to join each data movement operation. 32-bit ARM Cortex™-M3 MCU HT32F1755/HT32F1765/HT32F2755 CMOS Sensor Interface – CSIF (HT32F2755 only) Debug Support ▀ ▀ ▀ ▀ Serial Wire or JTAG Debug Port SWJ-DP 6 instruction comparators and 2 literal comparators for hardware breakpoint or code/literal patch 4 comparato