ETC PI49FCT805TP

PI49FCT805T
PI49FCT2805T
PI49FCT806T
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Fast CMOS
Buffer/Clock Driver
Product Features
Product Description
•
•
•
•
•
•
•
Extremely low output skew: 0.5ns
Monitor output pin
Clock busing with Hi-Z state control
TTL input and CMOS output compatible
Extremely low static power (1 mW, typ.)
Hysteresis on all inputs
Packages available:
– 20-pin 209 mil wide SSOP (H)
– 20-pin 300 mil wide DIP (P)
– 20-pin 300 mil wide SOIC (S)
– 20-pin 150 mil wide QSOP (Q)
• Device models available on request
• Industrial Operation at -40ºC to +85ºC
Pericom Semiconductor’s PI49FCT series of logic circuits are
produced in the Company’s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
PI49FCT805T/2805T Logic Block Diagram
PI49FCT806T Logic Block Diagram
The PI49FCT805T and PI49FCT2805T are non-inverting clock
drivers. The PI49FCT806T is an inverting clock driver designed with
two independent groups of buffers. These buffers have Hi-Z state
Output Enable inputs (active LOW) with a 1-in, 5-out configuration
per group. Each clock driver consists of two banks of drivers, driving
five outputs each from a standard TTL compatible CMOS input.
The PI49FCT2805T also features a 25 Ohm on-chip resistor for lower
noise.
OEA
OEA
5
INA
5
OA0–4
INA
OB0–4
INB
5
INB
5
OEB
OB0–4
OEB
MON
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OA0–4
MON
1
PS7006B
01/28/99
PI49FCT805/2805T/806T
Fast
CMOS
Buffer/Clock Driver
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Product Pin Description
Pin Name
OEA, OEB
INA, INB
OAN, OBN
MON
GND
VCC
Description
Hi-Z State Output Enable Inputs (Active LOW)
Clock Inputs
Clock Outputs
Monitor Output
Ground
Power
PI49FCT806T Truth Table(1)
PI49FCT805/2805T Truth Table(1)
Inputs
OEA, OEB
L
L
H
H
Outputs
INA, INB
L
H
L
H
OAN, OBN
L
H
Z
Z
Inputs
MON
L
H
L
H
OEA, OEB
L
L
H
H
Outputs
INA, INB
L
H
L
H
OAN, OBN
H
L
Z
Z
Note:
1. H= High Voltage Level
L = Low Voltage Level
Z = High Impedance
Note:
1. H= High Voltage Level
L = Low Voltage Level
Z = High Impedance
PI49FCT805T Product Pin Configuration
PI49FCT806T Product Pin Configuration
VccA
OA0
OA1
OA2
GNDA
OA3
OA4
GNDB
OEA
INA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VccB
OB0
OB1
OB2
GNDB
OB3
OB4
MON
OEB
INB
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VccA
OA0
OA1
OA2
GNDA
OA3
OA4
GNDB
OEA
INA
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MON
H
L
H
L
VccB
OB0
OB1
OB2
GNDB
OB3
OB4
MON
OEB
INB
PS7006B
01/28/99
PI49FCT805/2805T/806T
Fast
CMOS
Buffer/Clock Driver
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... –65°C to +150°C
Ambient Temperature with Power Applied .......................... -40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) –0.5V to +7.0V
DC Input Voltage .................................................................. –0.5V to +7.0V
DC Output Current ............................................................................. 120mA
Power Dissipation ................................................................................... 0.5W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = -40°C to +85°C, VCC = 5.0V ± 5%)
Test Conditions(1)
Parameters Description
Min.
Typ(2)
2.4
3.3
Max.
Units
VOH
Output HIGH Voltage
VCC = Min., VIN = VIH or VIL
IOH = –24.0 mA
VOL
Output LOW Current
VCC = Min., VIN = VIH or VIL
IOL = 64 mA
0.3
0.55
V
IOL = 12 mA (25Ω)
0.3
0.50
V
VIH
Input HIGH Voltage
Guaranteed Logic HIGH Level
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
IIH
Input HIGH Current
VCC = Max.
IIL
Input LOW Current
IOZH
High Impedance
IOZL
Output Current
II
Input HIGH Current
VCC = Max., VIN =VCC (Max.)
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18 mA
IOS
Short Circuit Current
VCC = Max.(3), VOUT = GND
VH
Input Hysteresis
VCC = 5 V
V
2.0
V
0.8
V
VIN = VCC
1
µA
VCC = Max.
VIN = GND
–1
µA
VCC = Max.
VOUT = VCC
1
µA
VOUT = GND
–1
µA
20
µA
–0.7
–1.2
V
–120
–225
mA
–60
200
mV
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4)
Description
Test Conditions
Typ
Max.
Units
CIN
Input Capacitance
VIN = 0 V
6
10
pF
COUT
Output Capacitance
VOUT = 0 V
8
12
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
3
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PS7006B
01/28/99
PI49FCT805/2805T/806T
Fast
CMOS
Buffer/Clock Driver
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Power Supply Characteristics
Test Conditions(1)
Parameters Description
Min.
Typ(2)
Max.
Units
3
30
µA
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
∆ICC
Supply Current per
Input @ TTL HIGH
VCC = Max.
VIN = 3.4V(3)
0.5
2.0
mA
ICCD
Supply Current per
Input per MHz(4)
VCC = Max.,
Outputs Open
OEA = OEB = GND
Per Output Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
0.15
0.25
mA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fI = 10 MHZ
50% Duty Cycle
OEA = OEB = GND
Five Outputs Toggling
VIN = VCC
VIN = GND
7.7
14.0(5)
mA
VIN = 3.4V
VIN = GND
8.0
15.0(5)
VCC = Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs
Toggling
VIN = VCC
VIN = GND
4.3
8.4(5)
VIN = 3.4V
VIN = GND
4.8
10.4(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PS7006B
01/28/99
PI49FCT805/2805T/806T
Fast
CMOS
Buffer/Clock Driver
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PI49FCT805/806T Switching Characteristics over Operating Range
805/2805/806T 805/2805/806AT 805/2805/806BT 805/2805/806CT
Com.
Com.
Com.
Com.
Description
Conditions(1)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
INA to OAN, INB to OBN
CL = 50 pF
RL = 500Ω
1.5
6.5
1.5
5.8
1.5
5.0
1.5
4.5
ns
tPZH
tPZL
Output Enable Time
OEA to OAN, OEB to OBN
1.5
8.0
1.5
8.0
1.5
8.5
1.5
6.2
ns
tPHZ
tPLZ
Output Disable Time(4)
OEA to OAN, OEB to OBN
1.5
7.0
1.5
7.0
1.5
6.0
1.5
5.0
ns
tSKEW(o)(3)
Skew between two outputs
of same package
(same transition)
—
0.7
—
0.5
—
0.4
—
0.4
ns
tSKEW(p)(3)
Skew between opposite
transitions (tPHL-tPLH) of
the same output
—
1.0
—
0.7
—
0.5
—
0.5
ns
tSKEW(t)(3)
Skew between two outputs
of different package at
same temperature
(same transition)
—
1.5
—
1.0
—
1.0
—
1.0
ns
Parameters
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worse cast temperature (max. temp).
4. This parameter is guaranteed but not production tested.
Tests Circuits For All Outputs(1)
Switch Position
VCC
7.0V
500Ω
VIN
VOUT
Pulse
Generator
50pF
CL
500Ω
5
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Switch
Open Drain
Disable LOW
Enable LOW
Closed
All Other Inputs
Open
DEFINITIONS:
CL = Load capacitance: includes jig and
probe capacitance.
RT = Termination resistance: should be
equal to ZOUT of the Pulse Generator.
D.U.T.
RT
Test
PS7006B
01/28/99
PI49FCT805/2805T/806T
Fast
CMOS
Buffer/Clock Driver
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Switching Waveforms
Output Skew – tSK(o)
Propagation Delay
3V
3V
Input
Input
1.5V
1.5V
0V
0V
tPLHx
tPHLx
tPHL
tPLH
VOH
VOH
Output
Ox
1.5V
1.5V
VOL
tSK(o)
VOL
tSK(o)
VOH
Oy
1.5V
VOL
Enable and Disable Times
tPLHy
Enable
tPHLy
Disable
3V
OE
tSK(o) = | tPLHy – tPLHx | or | tPHLy – tPHLx |
1.5V
0V
tPZL
Output
Normally
Low
Output
High
3.5V
3.5V
Switch
Closed
3V
1.5V
0.3V
tPZH
Normally
Pulse Skew – tSK(p)
tPLZ
Input
0V
tPHZ
Switch
Open
0.3V
1.5V
VOL
VOH
1.5V
Output
1.5V
0V
0V
VOL
tSK(p) = | tPHL – tPLH |
Package Skew – tSK(t)
3V
Input
Ordering Information
1.5V
Orde ring Code
0V
tPLH1
tPHL1
VOH
Package 1
1.5V
Output
VOL
tSK(t)
tSK(t)
VOH
Package 2
M arking Code
PI49FCT805xTp
PI49FCT805Tpx
PI49FCT2805xTp
PI49FCT2805Tpx
PI49FCT806xTp
PI49FCT806Tpx
Note:
x = Speed Grades: “blank”, A, B, C.
p = Package Type:
H = 209-mil SSOP
P = 300-mil DIP
Q = 150-mil SOIC
S = 300-mil SOIC
Example:
PI49FCT2805ATH = A grade, H pkg marked as
PI49FCT2805THA
1.5V
Output
VOL
tPLH2
tPHL
tPLH
VOH
tPHL2
tSK(t) = | tPLH2 – tPLH1 | or | tPHL2 – tPHL1 |
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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