PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features Introduction • Sixteen full-duplex, serial time-division The PT7A5020 is a Multi-rate Large Digital Switch multiplexed (TDM) highway streams (MLDS). It provides 2,048 x 2,048 channel non- • Switching up to 2,048 incoming PCM channels blocking switching among 16 input streams and 16 to up to 2,048 outgoing PCM channels output streams at most. • Accept data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s (Single-Rate mode) or any combination This device can operate in two modes: Single-Rate of data rates of 2.048Mb/s, 4.096Mb/s and mode and Multi-Rate mode. In Single-Rate mode, the 8.192Mb/s (Multi-Rate mode) all 16 input streams and 16 output streams serial bit rate must be single rate of 8.192Mb/s, 4.096Mb/s or • 64 kbits/s granularity with optional 32 kbits/s (4- 2.048Mb/s. In Multi-Rate mode, the 16 input streams bit) and 16 kbits/s (2-bit) subrate switching and the 16 output streams are both divided into two • Tristate function per-channel for further parts, the serial bit rate of each one of the four parts expansion • Low-latency/frame integrity selection per-channel can be 8.192Mb/s, 4.096Mb/s or 2.048Mb/s • Automatic frame offset delay measurement. independently. • Per input stream offset programming The device has many features that are programmable • Intel/Motorola microprocessor interface on stream or channel basis, including message mode, • Connection memory block programming for fast input offset delay and high impedance output control. device initialization Per steam input delay control is particularly useful • Automatically identifies ST-BUS/GCI formats for managing large multi-chip switches that transport • Internal loopback per-channel for diagnostic both voice channel and concatenated data channels. purposes In addition, input stream can be individually • IEEE-1149.1 (JTAG) boundary scan calibrated for input frame offset using a dedicated pin. Applications • Medium and large switching platforms • CTI application • Voice/data multiplexer Pa r t Nu mb er Pa ck a ge PT7A5020J 84 - Pin PLCC PT7A5020M 100 - Pin MQFP • Digital cross-connect • ST-BUS/GCI interface functions • DM highway data rate adaptation • LAN/WAN gateways PT0088(03/02) 1 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Block Diagram CLK F0i FE/ W FPS HCLK Shift Out Processor STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 Single & M ultirate Tim ing Serial To Parallel Converter Data M em ory Output Select Control Register & CPU Interface A7-A0 D15-D8/ AD7-AD0 PT0088(03/02) Connection M em ory AS/ ALE IM CS DS/ RD Parallel To Serial Converter JTAG Test CTSo STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 DTA TDI TCK IC R/W / TM S TDO TRST RESET WR 2 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Information Pin Configuration WFPS 84 Pin PLCC WFPS 100 Pin MQFP PT0088(03/02) 3 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Description P in No. Typ e Na m e 31, 41, 56, 66, 76, 99 GND GND 2, 32, 63 5, 40, 67 Power VCC 3 - 10 77 - 84 68-75 58 - 65 O STo8 - 15 STo0 - 7 ST-BUS Output (Three-state Outputs): Serial data Output streame, data rates of 2.048, 4.096 or 8.192 Mb/s, programmable by bits DR0 - 1 in the IMS register. 12 -27 81-96 I STi0 - 15 ST-BUS Input: Serial data input stream, data rates of 2.048, 4.096 or 8.192 Mb/s, programmable by bits DR0 - 1 in the IMS register. 84-PLCC 100-MQFP 1, 11, 30, 54 64, 75 F0i Descr ip t ion Ground. +5V Power Supply. Frame Pulse: accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications when WFPS=0, and accepts a negative frame pulse which conforms to WFPS formats when WFPS=1. 28 97 I 29 98 I FE/HCLK 31 100 I CLK Clock: Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15). In Single-Rate mode, this input accepts a 4.096, 8.192 or 16.384 MHz clock; in Multi-Rate mode, this pin only accepts 16.384 MHz clock.. 33 6 I TMS Test Mode Select (Input): JTAG signal that controls the state transitions of the TAP controller. Pulled high by an internal pull-up when not driven. 34 7 I TDI Test Serial Data In: input for JTAG serial test instructions and data, pulled high by an internal pull-up when not driven. 35 8 O TDO Test Serial Data Out: output for JTAG serial data on the falling edge of TCK. It is held in high impedance state when JTAG scan is not enable. 36 9 I TCK Test Clock: clock to the JTAG test logic. Pulled high by an internal pull-up when not driven. Frame Evaluation/HCLK Clock: frame measurement input when WFPS=0, when WFPS=1, the HCLK (4.096MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. 37 10 I TRST Test Reset: Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the device is in the normal functional mode. 38 11 I IC Internal Connection: Connect to GND for normal operation. This pin must be low for normal operation and to comply with IEEE 1149 (JTAG) boundary scan requirements. It is pulled low internally when not driven. RESET Device Reset (Schmitt Trigger Input): active LOW, reset the device by clearing the device internal counters, registers and setting STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100nsec to reset the device. 39 PT0088(03/02) 12 I 4 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| P in No. 84-PLCC 100-MQFP Typ e Na m e Descr ip t ion 40 13 WFPS I Wide Frame Pulse Select: When 1, enables the WFP Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. 41-48 14-21 A0-A7 I Address 0 - 7: in non-multiplexed CPU bus operation, these lines provide the A0 - A7 address lines to the internal memories. I Data Strobe / Read: For Motorola multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. 49 22 DS/RD 50 23 R/W / WR I Read/Write / Write: In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For Intel multiplexed bus operation, this input is WR. This active low input is used with CS to control the data bus (AD0 - 7, D8 - D15) lines as inputs. 51 24 CS I Chip Select: Active low input used by a processor to activate the microprocessor port of MLDS. 52 25 AS/ALE I Address Strobe or Latch Enable: This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. 53 26 IM I C P U I n t e r f a c e Mo d e : Wh e n I M i s h i g h , t h e m i c r o p r o c e s s o r p o r t i s i n t h e multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. 55-62 32-39 AD0-7 I/O Address/Data Bus 0 to 7: These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. 65-72 42-49 D8-15 I/O D a t a B u s 8 - 1 5 : T h e s e p i n s a r e t h e e i g h t m o s t s i g n i fi c a n t d a t a b i t s o f t h e microprocessor port. O Data Transfer Acknowledgement: Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. O Control Output: This is a 4.096, 8.192 or 16.384Mb/s output containing 512, 1024 or 2048 bits per frame respectively in Single-Rate mode. In Multi-Rate mode, this output rate is 16.384 Mb/s. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. I Output Drive Enable: This is the output enable control for the STo0 to STo15 serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo0-15 are in a high impedance state. If this input is high, the STo0-15 output drivers are enabled. However, each channel may still be put into a high impedance state by using the per channel control bit in the connection memory. 73 50 74 55 DTA CSTo 76 57 ODE - 1-4 27-30 51-54 77-80 NC PT0088(03/02) No connection 5 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Absolute Maximum Ratings Storage Temperature ........................................................-65oC to +125oC Ambient Temperature with Power Applied ........................ -40oC to +85oC Supply Voltage to Ground Potential (Inputs & Vcc) ........... -0.3V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) -0.3V to +7.0V DC Input Voltage ............................................................... -0.3V to +7.0V DC Input and Output Current .......................................................... 20mA Power Dissipation ................................................................................ 2W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Sym C h a r a ct er ist ics Vcc Test C on d it ion s Min Typ Ma x Un it s Supply Votage 4.75 5.0 5.25 V VIH Input HIGH Voltage 2.4 Vcc V VIL Input LOW Voltage 0 0.4 V TA Operating Temperature -40 85 O 25 C Note: Typical figures are at 25oC and are for design aid only; not production tested. PT0088(03/02) 6 Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical, Power Supply and Capacitance Characteristics Sym ICC Descr ip t ion Supply Current Test C on d it ion s Min Typ Ma x Un it s Output unloaded, 2Mb/s 50 mA Output unloaded, 4Mb/s 90 mA Output unloaded, 8Mb/s 170 mA VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 Input Leakage Current (Input Pins) 15 IIL Input Leakage Current(with an internal pull-up or -down) 2.0 V V µΑ VO between GND and VCC 100 VOL Output LOW Voltage IOL = 10mA VOH Output HIGH Voltage IOH = 10mA IOZ Output High Impedance Leakage VO between GND and VCC CIN COUT 2.4 1.0 V 3.5 V 5 µΑ Input Pin Capacitance 10 pF Output Pin Capacitance 10 pF Ma x Un it s AC Electrical Characteristics Sym Descr ip t ion VTT TTL Threshold VHM TTL Rise/Fall Threshold Voltage High VLM TTL Rise/Fall Threshold Voltage Low PT0088(03/02) Test C on d it ion s Min Typ 1.5 2.0 0.8 7 V V V Ver:0 PT Pericom Technology Inc. Preliminary Data Sheet PT7A5020 Mult-Rate Large Digital Switch ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Pericom Technology Inc. Email: [email protected] China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0088(03/02) 8 Ver:0