PULSUS PS9604 Stereo, 24-Bit, 192kHz PCM-to-PWM Converter for Full Digital Power Amplifier Description R Y The PS9604 is a high performance, stereo, 24-bit, 192kHz PCM-to-PWM converter IC. The PS9604 uses a state-of-the-art digital signalprocessing algorithm to convert input PCM signal to PWM format without sacrificing the quality of audio signal. The PS9604 can be used with various 8X oversampling digital filters, for example, DF1704, SM5847, and PMD200. It can be set up to use different modulation indices and PWM mapping methods. The PS9604’s excellent SNR and ultra-low distortion makes it suitable for a size-sensitive consumer power amplifier application where high performance is required, such as high-quality AV receiver, digital TV, and hi-fi amplifiers. A high-end quality full-digital amplifier can be built using the PS9604, with minimal cost. EL IM IN Sampling Frequency: 32kHz to 192kHz 8X Oversampling at 96kHz 4X Oversampling at 192kHz Input Audio Data Word: 20-, 24-Bit 130 dB Dynamic Range 120 dB SNR (typical) Variable Modulation Index: 0.5 to 0.875 PWM Switching Frequency: 256~384kHz Variable PWM Mapping Method: Both Class AD, BD amplifications are supported Automatic Sample Rate Detection System Clock: 2048fs at 48kHz, 1024fs at 96kHz, 512fs at 192kHz Single 3.3 V Power Supply 28-Lead SOIC Package A Features Application Block Diagram MOD-INDEX [1:0] PR 24/20BIT BCLK WCLK LDATA RDATA REF_CLK FS_CLK 192K 96K SF1 SF0 Serial Input Interface NS_MODE Multi-bit Delta-Sigma Modulator MUTE PWM_MAP [1:0] H Bridge PWM Modulator PWM_L+ PWM_L- PWM Modulator PWM_R+ PWM_R- Gate Driver Gate Driver Sample Rate Detector Timing Generator RESET Copyright © Pulsus Technologies Inc. 2000 SYSCLK Power Supply VSS VDD 1 AUGUST 2000 REV0.4 PULSUS PS9604 Specifications ABSOLUTE MAXIMUM RATINGS Max 4.0 V Input Current, (Any pin except Supply) - ±10 mA Output Current (/Pin) - Input Voltage (Any pin except 5V tolerant) VSS – 0.3 Input Voltage (5V tolerant Input) VSS – 0.3 Storage Temperature -65 Units Y Min VSS – 0.3 ±30 mA VDD + 0.5 V +7.5 V +150 °C R Parameter Power Supply Voltage (VDD to VSS) A Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Input Voltage (Any pin except 5V tolerant) Input Voltage (5V tolerant Input) Typ Max 3.0 3.3 3.6 V VSS - VDD V VSS 5.5 V -40 +85 °C IM Ambient Operating Temperature Min IN Parameter Power Supply Voltage (VDD to VSS) Units ELECTRICAL CHARACTERISTICS Parameter Input Leakage Current EL High-Level Input Voltage (except RESET) Typ Max Units -1 - 1 μA 2.0 - - V V - - 0.8 High-Level Input Voltage (RESET) 1.1 - 2.4 V Low-Level Input Voltage (RESET) 0.6 - 1.8 V High-Level Output Voltage (IO = 2mA) VDD – 0.4 - - V Low-Level Output Voltage (IO = 2mA) - - 0.4 V Pull-up Resistance 20 50 100 kΩ Pull-down Resistance kΩ PR Low-Level Input Voltage (except RESET) Min 20 50 100 Input Capacitance (f = 1MHz, VDD = 0V) - - 10 pF Output Capacitance (f = 1MHz, VDD = 0V) - - 10 pF Copyright © Pulsus Technologies Inc. 2000 2 AUGUST 2000 REV0.4 PULSUS PS9604 Y Pin Assignment 1 28 VDD BCLK 2 27 PWM_R+ WCLK 3 26 LDATA 4 25 RDATA 5 SF1 6 SF0 7 96K 8 192K 9 R VDD PWM_R- A 24/20BIT M_INDEX1 23 M_INDEX0 22 PWM_MAP1 21 PWM_MAP0 20 RESET FS_CLK 10 19 MUTE REF_CLK 11 18 NS_MODE TEST_ENA 12 17 PWM_L- SYS_CLK 13 16 PWM_L+ VSS 14 15 VSS EL IM IN 24 PR PS9604 (28Lead SOIC, Top View) Copyright © Pulsus Technologies Inc. 2000 3 AUGUST 2000 REV0.4 PULSUS PS9604 Pin Descriptions PIN No. PIN NAME I/O 1 VDD - DESCRIPTION Digital Power, +3.3V BCLK IN 3 WCLK IN Word clock input for serial audio data. WCLK latch the shifted data input on the falling clock edge. This input is 5V tolerant. 4 LDATA IN Left channel serial data input. This input is 5V tolerant. Right channel serial data input. Both LDATA and RDATA are assumed to be MSB-first 2’s-compliment. If data is absent or held to a constant value (all 0’s or constant values for 8192 words at 44.1/48kHz sampling rate), or any of the input clocks are removed, an internal MUTE is activated. This input is 5V tolerant. IN 6 SF1 OUT 7 SF0 8 96K 10 12 OUT OUT R A 88.2/96kHz sampling rate indication output. This pin goes High when the sampling rate is 88.2/96kHz. 176.4/192kHz sampling rate indication output. This pin goes High when the sampling rate is 176.4/192kHz. 192K OUT FS_CLK IN Sampling rate clock input. This input is 5V tolerant. Internal pull-down resistor. REF_CLK IN Reference clock input. 12.288MHz Reference clock is required to detect sampling rate. This input is 5V tolerant. Internal pull-down resistor. TEST_ENA - PR 11 Sampling rate indication output. (SF1, SF0) = (0,0) : 44.1kHz (0,1) : other sampling rate (1,0) : 48kHz (1,1) : 32kHz EL 9 IN RDATA IM 5 Y 2 Bit clock input for serial audio data. BCLK shifts data input on the rising clock edge. Need not run continuously; may be gated or used in a burst fashion. This input is 5V tolerant. Chip test mode enabling input. This pin should be tied to GND for normal operation. Master system clock input. Connect to an external clock source. 2048Fs at 32/44.1/48kHz sampling rate, 1024Fs at 88.2/96kHz sampling rate, 512Fs at 176.4/192kHz sampling rate. This input is 5V tolerant. 13 SYS_CLK IN 14 VSS - Digital Ground 15 VSS - Digital Ground 16 PWM_L+ OUT Left channel Positive PWM output. 17 PWM_L- OUT Left channel Negative PWM output. Copyright © Pulsus Technologies Inc. 2000 4 AUGUST 2000 REV0.4 PULSUS Reset input. Active Low Schmitt-Trigger input. The Schmitt-Trigger input allows a slowly-rising input to reset the chip reliably. The RESET signal must be asserted ‘Low’ during power up. Deassert ‘High’ for normal operation. This input is 5V tolerant. RESET IN 21 PWM_MAP0 IN 22 PWM_MAP1 IN 23 M_INDEX0 IN 24 M_INDEX1 26 27 IN IN Input data word size selection. This pin selects between 24 bits input word size (High) and 20 bits input word size (Low). An internal 50kΩ pull-up to VDD will hold 24/20BIT high, so no connection is required if input word size is 24 bits. Internal pull-up resistor. Input must be driven by levels of VSS to VDD. PWM_R- OUT Right channel Negative PWM output. PWM_R+ OUT Right channel Positive PWM output. VDD - Digital Power, +3.3V PR 28 24/20BIT Modulation Index selection. (M_INDEX1, M_INDEX0) = (0,0) : 50.0% (0,1) : 62.5% (1,0) : 75.0% (1,1) : 87.5% Internal pull-up resistor. Input must be driven by levels of VSS to VDD. EL 25 PWM mapping method selection. (PWM_MAP1, PWM_MAP0) = (0,0) : 400kHz, AD (0,1) : 800kHz, AD (1,0) : 400kHz, BD (1,1) : 400kHz, AD Internal pull-up resistor. Input must be driven by levels of VSS to VDD. IM 20 Y IN Mute control. Active High input. Assert ‘High’ to mute both stereo outputs. Deassert ‘Low’ for normal operation. This input is 5V tolerant. Internal pull-down resistor. R MUTE IN A 19 NS_MODE Noise shaping mode selection. This pin selests between Noise shaping MODE0 (Low) and Noise shaping MODE1 (High). An internal 50kΩ pull-up to VDD will hold NS_MODE high, so no connection is required if Noise shaping MODE1 is required. Internal pull-up resistor. Input must be driven by levels of VSS to VDD. IN 18 PS9604 Copyright © Pulsus Technologies Inc. 2000 5 AUGUST 2000 REV0.4 PULSUS PS9604 PR EL IM IN A R Y Package Dimensions Copyright © Pulsus Technologies Inc. 2000 6 AUGUST 2000 REV0.4