STP2001.frm Page 1 Monday, August 25, 1997 2:46 PM STP2001QFP July 1997 Slave I/O DATA SHEET Integrated SBus Interface Slave I/O Controller DESCRIPTION The STP2001Slave I/O Controller is a highly integrated, low-cost, low-power device designed for use in single-processor systems with an SBus interface. The STP2001 provides serial I/O for keyboard, mouse and general-purpose use. In addition, a floppy disk interface, an external byte-wide expansion bus (EBus) for TOD and EPROM, I/O registers and reset control logic are integrated. Together, the STP2001 and the STP2000 Master I/O Controller, provide a complete I/O subsystem. The two serial ports for keyboard/mouse and general purpose use are compatible with the AMD AM85C30, rev C Serial Communications Controller. The TTY A/B serial ports are fully synchronous, while the keyboard/mouse ports are asynchronous only. All ports support data rates up to 38.4 Kb/s. The NCR82077 floppy disk interface is compatible with the Intel 8077A-1 single-chip floppy controller, supporting up to a 1 MBit/sec transfer rate. Features Benefits • Integrates two dual serial controllers, a high-speed floppy controller, uniprocessor interrupt, reset, and counter/timer circuitry, power-down control and an EBus in a single package • Saves cost, power, board space, and weight • Directly interfaces to CPU through the SBus • Improved performance • Auxiliary I/O registers (used for LED, floppy and system power-down) • High level of system integration; ease of design • Interrupt Controller for single-processor SBus system • High level of system integration; ease of design • System reset control • High level of system integration; ease of design • Counter/timers for single-processor SBus system • High level of system integration; ease of design • EBus interface • Generic 8-bit interface available • JTAG internal and boundary SCAN logic • Improved chip and board level testability • 160-pin PQFP packaging • Cost effective packaging • IC is also available from NCR Corp. (PN NCR89105) • Second source 1 This Material Copyrighted by Its Respective Manufacturer STP2001.frm Page 2 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP BLOCK, APPLICATION, AND LOGIC DIAGRAMS SBus SBus Slave Interface System Reset 8-Bit Bus Interface Reset/ Misc Misc. I/O Pins Interrupt Controller Interrupt Priority Level Counter/ Timers Interrupt Sources EPROM NVRAM Generic Serial Controller (NCR85C30) Keyboard/Mouse Controller (NCR85C30A) Floppy Controller (NCR82077) RS232 Serial Transceivers Keyboard/Mouse Floppy Disk Drive Figure 1. STP2001 Block Diagram SCSI Connector 160-Pin I/O Connector SCSI Ethernet Parallel Video Floppy Key/Mouse Audio Serial 2 1 DRAM Banks 0 RAMDAC VRAM Bank 0 STP2000 Master I/O MicroSPARC CPU Frame Buffer SBUS Slot 1 STP2001 Slave I/O Slot 0 SBus Connectors Floppy Connector Internal EBus TOD/NVRA Boot PROM Figure 2. STP2001 Typical Application 2 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 3 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller 32 SB_D[31:0] SB_SEL CHIP_SEL SBus Signals 5 3 3 EB_RD EBUS_LATCH SB_PA[W] GENERIC_RDY SB_PA[X] GENERIC_CS SB_PA[Y] TOD_CS SB_PA[Z] EPROM_CS EBus Interface SB_PA[16] SB_PA[4:0] SB_SIZ[2:0] FPY_DENSEL FPY_INDEX SB_RD FPY_MOTEN SB_AS FPY_DRVSEL SB_ACK[2:0] FPY_DIR FPY_STEP FPY_WRDAT SB_IRQ[7:1] M0_IRL[3:0] ENET_IRQ Interrupt Signals 8 EB_WR SB_PA[V] SB_CLK 7 4 EBD[7:0] STP2001QFP SCSI_IRQ PFD MSI_IRQ MODERR_IRQ FPY_WRGATE (FDTRK0) Floppy Interface FPY_WRPROT FPY_RDDATA (FDHDSEL) FPY_HEADSEL (FDDENSEN) FPY_EJECT FPY_DISKCHG Miscellaneous System Signals POWER_OFF FPY_CLK32 MON_MSE_MUX FPY_CLK24 LINK_TEST_EN CLK10_MHZ SER_TXD_A SYS_LED SER_RXD_A IU_ERROR SER_TRXC_A POR_RST_IN SER_SYNC_A SER_RTXC_A Reset Signals SYS_RST_OUT MMC_RST_OUT SER_DTR_A SER_RTS_A SER_CTS_A JTAG_TDIN JTAG Signals SER_DCD_A JTAG_TMS (JTAG_MODEL) SER_TXD_B JTAG_CLK SER_RXD_B JTAG_RESET JTAG_TDOUT Serial Interface SER_TRXC_B SER_RTXC_B SER_SYNC_B KBD_DIN Keyboard/Mouse Interface SER_DTR_B KBD_DOUT SER_RTS_B MSE_DIN (MOUSEDIN) SER_CTS_B MSE_OUT SER_DCD_B SER_CLK Figure 3. STP2001 Logical Connections July 1997 This Material Copyrighted by Its Respective Manufacturer 3 STP2001.frm Page 4 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP SIGNAL DESCRIPTIONS SBus Interface: 54 Pins Signal SB_D[31:0] SB_ACK[2:0] Type I/O 3-State Description SBus Data Bus SBus Acknowledge SB_CLK Input SBus Clock Input SB_RD Input SBus Read/Write SB_SEL Input SBus Select SB_SIZ[2:0] Input SBus Transfer Size SB_AS Input SBus Address Strobe (address is valid) CHIP_SEL [1] Input High order physical address bits (for slave decodes) SB_PA[V:Z] [2] Input High order physical address bits (for slave decodes) SB_PA[16] Input PA[16] (for system/user selection in INT/TMR) SB_PA[4:0] Input Low order physical address bits 1. The CHIP_SEL pin is an additional qualifier (active low) to the SB_SEL line. When sharing a single SBus select line with another device (such as the STP2000QFP), one of the high order SBus physical address lines, such as PA[27], can be tied to the CHIP_SEL pin to distinguish between the two devices. 2. In some system configurations, the high order physical address bits can be connected as follows: SB_A[V, W, X, Y, Z]=PA[24:20]. EBus Interface: 15 pins Signal EB_D[7:0] Type I/O Description EBus data EB_ADDRLATCH Output EBus address latch EB_RD Output EBus read EB_WR Output Ebus write TOD_CS Output TOD chip select EPROM_CS Output EPROM chip select GENERIC_CS Output Generic port chip select GENERIC_RDY Input Generic port ready (25 µA pull-up) 4 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 5 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP Floppy Interface: 17 pins Signal Type FPY_CLK32 Input 32 MHz clock for floppy DDS Description FPY_CLK24 Input 24 MHz clock for floppy ASF FPY_DENSENSE Input Density sense input (auxio1 register bit) FPY_DISKCHG Input Disk change FPY_WRPROT Input Write protect FPY_TRACK0 Input Track 0 indicator FPY_RDDATA Input Read data FPY_INDEX Input Track index FPY_EJECT Output Floppy eject (ME[3] of 82077 ASF) FPY_HEADSEL Output Head select FPY_STEP Output Drive step pulse FPY_DIR Output Head step direction FPY_WRDATA Output Write data FPY_WRGATE Output Write enable FPY_DRVSEL Output Floppy drive select (DS[0] of 82077 ASF) FPY_MOTEN Output Floppy motor enable (ME[0] of 82077 ASF) FPY_DENSEL Output Density select (ME[2] or DENSEL of 82077 ASF) Keyboard/Mouse Interface: 4 pins Signal KBD_DIN KBD_DOUT Type Input Output MSE_DIN Input MSE_OUT Output Description Keyboard data in Keyboard data out Mouse data in Mouse data out Reset Signals: 3 pins Signal POR_RST_IN Type Input Description Power-up reset input SYS_RST_OUT Output System (SBus) reset output MMC_RST_OUT Output MMC reset output July 1997 This Material Copyrighted by Its Respective Manufacturer 5 STP2001.frm Page 6 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP Serial Interface: 19 pins Signal SER_CLK Type Input Description 19.66 MHz serial clock SER_RTXC_A Input Receive/transmit clock A SER_CTS_A Input Clear to send A SER_RXD_A Input Receive data A SER_DCD_A Input Data carrier detect A SER_DTR_A Output Data terminal ready A SER_TXD_A Output Transmit data A SER_RTS_A Output SER_SYNC_A Request to send A I/O Sync IO, A Transmit clock A SER_TRXC_A I/O SER_RTXC_B Input Receive/transmit clock B SER_CTS_B Input Clear to send B SER_RXD_B Input Receive data B SER_DCD_B Input Data carrier detect B SER_DTR_B Output Data terminal ready B SER_TXD_B Output Transmit data B SER_RTS_B Output Request to send B SER_SYNC_B I/O Sync IO, B SER_TRXC_B I/O Transmit clock B Interrupt Signals: 16 pins Signal MO_IRL[3:0] Type Output Description Module 0 encoded interrupt level SB_IRQ[7:1] Input SBus interrupt requests ENET_IRQ Input Ethernet interrupt request SCSI_IRQ Input SCSI interrupt request PFD Input Power fail detect (level 15 interrupt) MSI_IRQ Input MSI interrupt MODERR_IRQ Input Processor level 15 interrupt (async error) 6 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 7 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP Miscellaneous System Signals: 6 pins Signal Type CLK_10MHZ Input Description 10 MHz clock for counter/ timer block MON_MSE_MUX Output Monitor/mouse mux select POWER_OFF Output Power off output (to power supply) LINK_TEST_EN Output T7213 link test enable SYS_LED Output IU_ERROR Input System LED output Processor watchdog reset/Video interrupt JTAG Signals: 5 pins Signal JTAG_TDO Type Output Description JTAG test data output JTAG_TDI Input JTAG test data input (100 µA pull-up) JTAG_CLK Input JTAG clock JTAG_TMS Input JTAG test mode select (100 µA pull-up) JTAG_RST Input JTAG reset (100 µA pull-up) July 1997 This Material Copyrighted by Its Respective Manufacturer 7 STP2001.frm Page 8 Monday, August 25, 1997 2:46 PM STP2001QFP Slave I/O Integrated SBus Interface Slave I/O Controller ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings [1] Symbol Parameter VCC Power supply voltage VIN Input voltage Rating Units 7.0 V 0 ≤ VIN ≤ VCC V II Current Drain VCC and GND 100 mA TL Lead temperature (less than 10 second soldering) 250 °C TJ Operating temperature 0 to +70 °C TS Storage temperature PD Power dissipation -55 to +150 °C 560 mW 1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol Parameter Min Typ Max 4.75 5.0 5.25 V Operating Temperature 0 25 70 °C Power dissipation – 280 560 mW VCC Supply voltage TA PD Units Capacitance Typ Max Units CIN Symbol Input capacitance Parameter 6 – pF COUT Output capacitance 6 – pF CBI Bidirectional pin capacitance 6 – pF 8 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 9 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP DC Characteristics Symbol Parameter Min Typ Max Units VIH Input high voltage 2.0 – – V VIL Input Low voltage – – 0.8 V VOH High level output voltage 4.4 4.5 – V VOL Low level output voltage IIN Input leakage current IOH High level source current (VOH = 2.4 V) IOL IOZ Low level sink current (VOL = 0.4 V) – 0 0.1 V -10 – 10 µA IOH = 2.0 mA 2 – – mA IOH = 4.0 mA 4 – – mA IOH = 8.0 mA 8 – – mA IOH = 16.0 mA 16 – – mA IOH = 24.0 mA 24 – – mA IOL = -2.0 mA 2 – – mA IOL = -4.0 mA 4 – – mA IOL = -8.0 mA 8 – – mA IOL = -16.0 mA 16 – – mA IOL = -24.0 mA 24 – – mA IOL = -48.0 mA 48 – – mA SCSIPAD (VOL = 0.5 V) 48 – – mA SCSIPADF (VOL = 0.5 V) 48 – – mA -10 – 10 µA Hi-Z output leakage current July 1997 This Material Copyrighted by Its Respective Manufacturer 9 STP2001.frm Page 10 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP AC Characteristics: SBus Timing Signal # Min Max Units SBus clock frequency 16.7 25.0 ns 1 Clock period 40.0 60.0 ns 2 Clock high 17.0 – ns 3 Clock low 17.0 – ns fSB Parameter Conditions 4 Hold WRT CLK rising 0.0 – ns 5 Setup to CLK rising 15.0 – ns 6 Setup to CLK rising 15.0 – ns rising [1] 7 Hold WRT CLK – 1.0 ns 8 CLK rising to output valid 100 pF load – 22.5 ns 9 CLK rising to output invalid 100 pF load – 22.5 ns 10 CLK rising to output valid 100 pF load – 22.5 ns 11 CLK rising to output invalid 100 pF load 2.5 25.0 ns 12 CLK rising to output low 100 pF load – 22.5 ns 13 CLK rising to output high 100 pF load – 22.5 ns 1. This is the only violation of SBus Specification B.0. No known implementation to date provides less than 1.0 ns hold time on these signals. AC Characteristics: EBus Timing Signal # Parameter 14 Setup to CLK rising 15 Hold WRT CLK rising 16 CLK rising to output valid 17 CLK rising to output invalid 18 CLK rising to output valid Conditions Min Max Units 15.0 – ns – 2.0 ns 100 pF load – 22.5 ns 100 pF load – 22.5 ns 100 pF load – 22.5 ns Conditions Min Max Units 100 pF load – 22.5 ns 50 – ns AC Characteristics: Miscellaneous Timing Signal # 19 20 Parameter CLK rising to output valid 10 MHz clock period [1] 1. This clock must be run at 10 MHz (100 ns period) for correct software operation. 10 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 11 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP AC Characteristics: Floppy Controller Timing Signal # Min Max Units 21 FPY_CLK32 clock period [1] Parameter Conditions 31.3 31.3 ns 22 FPY_CLK24 clock high time 16.7 25 ns 23 FPY_CLK24 clock low time 16.7 25 ns 24 FPY_CLK24 clock period [1] 41.7 41.7 ns 25 Internal clock period (tCI) [2] 62.5 250 ns 26 FPY_DIR change to FPY_STEP setup time 1.0 – µs 27 FPY_STEP pulse width 7 8 µs 1 15 ms 4 – tCI rate [3] 28 FPY_STEP 29 FPY_INDEX pulse width 30 FPY_RDDATA pulse width 50 – ns 31 FPY_RDDATA data rate [4] 250 K 1M bit/s 32 FPY_WRGATE to FPY_WRDATA setup time 250 – ns 33 FPY_WRDATA pulse width [5] 125 500 ns 1. The NCR82077 core uses a digital data separator to read the data off of the disk. Any variation from the nominal input clock frequencies will shift the capture range of the cell. 2. NOTE 4: Internal clock period is a function of the selected data rate. Data Rate Frequency Period 1 Mbs 16 MHz 62.5 ns 500 Kbs 8 MHz 125 ns 300 Kbs 4.8 MHz 208 ns 250 Kbs 4 MHz 250 ns 3. FPY_STEP Rate time is selected by a SPECIFY command. Failure to issue a specify command before issuing a Recalibrate or Seek command or implied seek will cause unpredictable results. 4. FPY_RDDATA data rate is determined by the floppy tape drive or tape drive. The values are: • 1 Mbs – 1.0 µs minimum • 500 Kbs – 2.0 µs minimum • 300 Kbs – 3.3 µs minimum • 250 Kbs – 4.0 µs minimum 5. FPY_WRDATA pulse width is based on the selected data rate. The values are 2 x tCI: • 1 Mbs - 2 x 62.5 = 125 ns • 500 Kbs - 2 x 125 = 250 ns • 300 Kbs - 2 x 208 = 416 ns • 250 Kbs - 2 x 250 = 500 ns July 1997 This Material Copyrighted by Its Respective Manufacturer 11 STP2001.frm Page 12 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP AC Characteristics: Serial/Keyboard/Mouse Controllers Timing Signal # Min Max Units 34 SER_CLK low width [1] Parameter Conditions 50 – ns 35 SER_CLK high width 50 – ns 36 SER_CLK cycle time (tPC) 122 – ns 37 SER_RTXC width 150 – ns tPC 38 SER_RTXC cycle time 39 SER_TRXC width 40 SER_TRXC cycle time 41 SER_DCD or SER_CTS width 200 – ns 42 SER_SYNC width 200 – ns 43 SER_RXD to SER_RTXC setup time 0 – ns 44 SER_RXD to SER_RTXC hold time 150 – ns 45 SER_SYNC to SER_RTXC setup time -200 – ns 4 – 150 – ns 4 – tPC 46 SER_SYNC to SER_RTXC hold time 5 – tPC 47 SER_TRXC to SER_TXD delay – 200 ns 48 SER_TXD to SER_TRXC delay – 200 ns 1. The input SER_CLK is used to clock the serial controllers and the keyboard/mouse controller. The timing numbers in this section apply to both of these controllers. 12 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 13 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP TIMING DIAGRAMS 1 2 3 SB_CLK 5 4 5 SB_AS, SB_SEL SB_RD SB_PA[X, Y, 3, 2, 1] SB_SIZE[2:0] SB_ACK[2:0] SB_D[31:0] 6 7 14 15 EB_D[7:0] GENERIC_RDY Figure 4. SBus/EBus Input Timing 1 2 3 SB_CLK 8 9 SB_ACK[2:0] 10 11 12 13 16 17 SB_D[31:0] SYS_RST_OUT EB_D[7:0] 1 IRL[3:0] EB_ADDRLATCH EPROM_CS GENERIC_CS TOD_CS, EB_RD EB_WR 1 Figure 5. SBus/EBus Output Timing July 1997 This Material Copyrighted by Its Respective Manufacturer 13 STP2001.frm Page 14 Monday, August 25, 1997 2:46 PM STP2001QFP Slave I/O Integrated SBus Interface Slave I/O Controller 20 2 3 CLK_10MHZ Figure 6. Counter/Timer Input Clock 21 FPY_CLK32 22 23 24 FPY_CLK24 Figure 7. Floppy Controller Clock Inputs FPY_DIR 26 28 FPY_STEP 27 29 FPY_INDEX Figure 8. Floppy Drive Interface Timing 31 30 FPY_RDDATA Figure 9. Floppy Read Data FPY_WRGATE 32 33 FPY_WRDATA Figure 10. Floppy Write Data 14 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 15 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP 36 35 34 SER_CLK Figure 11. Serial/Keyboard/Mouse Clock Input 38 37 37 SER_RTXC 40 39 39 41 41 42 42 SER_TRXC SER_CTS, SER_RTXC Figure 12. Serial Pulse Widths SER_RFXC, FM Mode Only 43 44 43 44 SER_RXD 45 46 SER_SYNC FM Mode Only SER_TRXC, 47 47 SER_TXD 48 SER_TRXC Figure 13. Serial Data Timing July 1997 This Material Copyrighted by Its Respective Manufacturer 15 STP2001.frm Page 16 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP PACKAGE INFORMATION 160-Pin PQFP Pin Assignment Pin 1 Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name ENET_IRQ 33 SB_PA[y] 65 SB_D[19] 97 SER_DTR_B 129 TOD_CS EB_RD 2 SCSI_IRQ 34 SB_PA[x] 66 SB_D[20] 98 SER_SYNC_B 130 3 FPY_DENSENSE 35 SB_PA[w] 67 SB_D[21] 99 KBD_DOUT 131 EB_WR 4 FPY_DISKCHG 36 SB_PA[v] 68 VCC 100 MSE_OUT 132 EB_D[0] 5 FPY_WRPROT 37 GND 69 SB_D[22] 101 POWER_OFF 133 GND 6 FPY_TRACK0 38 CHIP_SEL 70 SB_D[23] 102 JTAG_TDO 134 EB_D[1] 7 FPY_RDDATA 39 SB_RD 71 SB_D[24] 103 VCC 135 EB_D[2] 8 FPY_INDEX 40 SB_AS 72 SB_D[25] 104 SER_CLK 136 EB_D[3] 9 FPY_CLK24 41 SB_SEL 73 SB_D[26] 105 SER_RTXC_B 137 EB_D[4] 10 GND 42 SB_D[0] 74 SB_D[27] 106 SER_CTS_B 138 EB_D[5] 11 FPY_EJECT 43 SB_D[1] 75 GND 107 GND 139 EB_D[6] 12 FPY_HEADSEL 44 SB_D[2] 76 SB_D[28] 108 SER_RXD_B 140 VCC 13 FPY_STEP 45 SB_D[3] 77 SB_D[29] 109 SER_DCD_B 141 EB_D[7] 14 FPY_DIR 46 GND 78 SB_D[30] 110 SER_RTXC_A 142 EB_ADDRLATCH 15 GND 47 SB_D[4] 79 SB_D[31] 111 SER_CTS_A 143 SYS_RST_OUT 16 FPY_WRDATA 48 SB_D[5] 80 SB_SIZ[2] 112 VCC 144 MMC_RST_OUT 17 FPY_WRGATE 49 SB_D[6] 81 SB_SIZ[1] 113 SER_RXD_A 145 M0_IRL[0] 18 FPY_DRVSEL 50 SB_D[7] 82 SB_SIZ[0] 114 SER_DCD_A 146 M0_IRL[1] 19 VCC 51 SB_D[8] 83 GND 115 LINK_TEST_EN 147 GND 20 FPY_MOTEN 52 SB_D[9] 84 SB_ACK[2] 116 MSE_DIN 148 M0_IRL[2] 21 FPY_DENSEL 53 VCC 85 SB_ACK[1] 117 KBD_DIN 149 M0_IRL[3] 22 VCC 54 SB_D[10] 86 SB_ACK[0] 118 MON_MSE_MUX 150 CLK_10MHZ 23 FPY_CLK32 55 SB_D[11] 87 SER_DTR_A 119 JTAG_TDI 151 SB_IRQ[1] 24 SB_PA[0] 56 SB_D[12] 88 SER_TXD_A 120 JTAG_CLK 152 SB_IRQ[2] 25 SB_PA[1] 57 SB_D[13] 89 GND 121 JTAG_TMS 153 SB_IRQ[3] 26 SB_PA[2] 58 SB_D[14] 90 SER_RTS_A 122 JTAG_RST 154 SB_IRQ[4] 27 GND 59 SB_D[15] 91 SER_SYNC_A 123 GENERIC_RDY 155 SB_IRQ[5] 28 SB_PA[3] 60 GND 92 SER_TRXC_A 124 IU_ERROR 156 SB_IRQ[6] 29 SB_PA[4] 61 SB_CLK 93 SER_TXD_B 125 POR_RST_IN 157 SB_IRQ[7] 30 SB_PA[16] 62 SB_D[16] 94 SER_TRXC_B 126 GENERIC_CS 158 PFD 31 SB_PA[z] 63 SB_D[17] 95 VCC 127 SYS_LED 159 MODERR_IRQ 32 VCC 64 SB_D[18] 96 SER_RTS_B 128 EPROM_CS 160 MSI_IRQ 16 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2001.frm Page 17 Monday, August 25, 1997 2:46 PM Slave I/O Integrated SBus Interface Slave I/O Controller STP2001QFP 160-Pin PQFP Package Dimensions July 1997 This Material Copyrighted by Its Respective Manufacturer 17 STP2001.frm Page 18 Monday, August 25, 1997 2:46 PM STP2001QFP Slave I/O Integrated SBus Interface Slave I/O Controller ORDERING INFORMATION Part Number STP2001QFP Description 160-Pin Plastic Leaded Chip Carrier (PQFP) Document Part Number: STP2001 18 This Material Copyrighted by Its Respective Manufacturer July 1997