STP2000.frm 1 Mon Jul 7 08:11:43 1997 STP2000QFP July 1997 Master I/O 32-bit SBus Master I/O Controller DATA SHEET DESCRIPTION The STP2000 Master I/O Controller is an integrated SBus master device with built-in standard I/O capabilities for general purpose computing or embedded applications. The STP2000 directly interfaces the CPU through the system bus, SBus, to three major I/O channels for peripherals. The I/O channels include SCSI-II, ethernet and a parallel port. Together, with the STP2001 Slave I/O Controller, it provides a complete I/O subsystem. The STP2000 SBus interface is a 32-bit interface that supports both DMA and slave modes. There is data buffering and flow control on each of the I/O channels. Each channel has access to the SBus through the controller which is capable of DMA transfers of up to 32-byte bursts. The SBus slave port is used mostly for status and control. The STP2000 incorporates an ethernet controller, a Fast 8-bit SCSI-II controller, and a Centronics parallel port controller in a single package. The SCSI-II channel directly drives external peripherals. The ethernet channel can be connected to an external transceiver chip that supports twisted pair ethernet or AUI ethernet. The parallel port channel can be routed to external transceivers. Features Benefits • Single-chip solution to standard SPARC DVMA devices • Saves cost, power, board space, and weight • Compatible with microSPARC, SuperSPARC and any SBus based system • Standard low-cost solution • Supports concurrent 10 MByte/sec SCSI transfers, 1.25 MByte/sec Ethernet transfers, and 4 MByte/sec Parallel Port transfers • Improved system performance • Direct master/slave SBus interface • Improved system performance • JTAG internal and boundary SCAN logic • Improved chip and board level testability • 160-pin PQFP packaging • Cost effective packaging • IC is also available from NCR Corp. (PN - NCR89C100) • Second source 1 This Material Copyrighted by Its Respective Manufacturer STP2000.frm 2 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP BLOCK, APPLICATION, AND LOGIC DIAGRAMS SBus JTAG XTAL Osc. Control Data Address 14 32 10 6 5 Slave I/O Clocks and Interrupts SBUS DVMA Master 8 PROM CS ETHERNET® Controller (NCR92C990) Parallel Port 8 13 Data Control 5 SCSI Controller (NCR53C9x) 3 9 Data & Control CENTRONICS® Parallel Port 9 Data Ethernet Network Adaptor Control SCSI Bus Figure 1. STP2000 Block Diagram SCSI Connector 160-Pin I/O Connector SCSI Ethernet Parallel Video Floppy Key/Mouse Audio Serial 2 1 DRAM Banks 0 RAMDAC VRAM Bank 0 STP2000 Master I/O MicroSPARC CPU Frame Buffer SBUS Slot 1 STP2001 Slave I/O Slot 0 SBus Connectors Floppy Connector Internal EBus TOD/NVRA Boot PROM Figure 2. STP2000 Typical Application 2 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 3 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP SCSI_D[7:0] SCSI_DP SCSI_SEL SB_A26 593.51 lB*BT5.75 0 0 5.75241.09 588.67 SCSI_BSY TmCK[0-2:0] SB_RESET SCSI_REQ SB_LERR SCSI_ACK SB_CLK SCSI_MSG SB_RD SB_SEL SB_D_IRQ SCSI_CD SCSI_IO SCSI_ATN SB_E_IRQ SCSI_RST SB_P_IRQ SCSI_XTAL_IN SB_SIZ[2:0] SCSI_XTAL_OUT MACIO_SEL SB_PA_W P_DATA[0-7] SB_PA_X P_D_STRB SB_PA_Y P_BSY SB_PA[5:0] P_ACK SB_AS (ELP_PE) P_PE P_SLCT ENET_AUI ENET_TX ENET_TENA ENET_CLSN ENET_RX P_ERROR P_INIT P_SLCT_IN P_AFXN P_DS_DIR ENET_RENA P_BSY_DIR ENET_TCLK P_ACK_DIR ENET_RCLK P_D_DIR ID_CS SCC_20_IN SCC_20_OUT JTAG_TDO SCC_CLK20 JTAG_TDI FPY_24_IN JTAG_CLK FPY_24_OUT JTAG_TMS FPY_CLK24 JTAG_RST FPY_32_IN FPY_32_OUT VCC FPY_CLK32 GND Figure 3. STP2000 Logical Connections July 1997 This Material Copyrighted by Its Respective Manufacturer 3 STP2000.frm 4 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP SIGNAL DESCRIPTIONS SBus Interface Name SB_D[31:0] Type I/O SB_BR I/O SB_BG Input SB_ACK[2:0] I/O Description SBus Data Bus (MSB) SBus Bus Request SBus Bus Grant SBus Acknowledge SB_RESET Input SBus Reset SB_LERR Input SBus Late Error (INT15) SB_CLK Input SBus Clock Input SB_RD I/O SB_SEL Input SBus Read/Write SBus Select SB_D_IRQ Output SBus Interrupt for SCSI transfers (open-drain) SB_E_IRQ Output SBus Interrupt for ETHERNET transfers (open-drain) SB_P_IRQ Output SBus Interrupt for Parallel Port Transfers (open-drain) SB_SIZ[2:0] SB_AS I/O Input SBus Transfer Size SBus Address Strobe (address is valid) CHIP_SEL [1] Input High order physical address bit SB_PA[W] Input High order physical address bit SB_PA[X] Input High order physical address bit SB_PA[Y] Input High order physical address bit SB_PA[5:0] Input Low order physical address bits 1. The CHIP_SEL pin is an additional qualifier (active high) to the SB_SEL line. In some system configurations where the STP2000 (Master I/O Controller) and the STP2001 (Slave I/O Controller) share a single SBus select line, PA[27] can be used to select between the two. 4 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 5 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP Ethernet Interface Name Type ENET_AUI [1] Output Description Ethernet TP/AUI select ENET_TX Output Ethernet Transmit data ENET_TENA Output Ethernet Transmit enable ENET_CLSN Input Ethernet Collision detect ENET_RX Input Ethernet Receive data ENET_RENA Input Ethernet Receiver enable (carrier sense) ENET_TCLK Input Ethernet Transmit clock ENET_RCLK Input Ethernet Receive clock 1. Drives MIS input of the AT&T T7213 chip to select between twisted pair and AUI-type Ethernet interfaces, with ENET_AUI = 0 selecting AUI. SCSI Interface [1] Name Type Description SCSI_D[7:0] I/O SCSI Data SCSI_DP I/O SCSI Data Parity SCSI_SEL I/O SCSI Select SCSI_BSY I/O SCSI Busy SCSI_REQ I/O SCSI Request SCSI_ACK I/O SCSI Acknowledge SCSI_MSG I/O SCSI Message SCSI_CD I/O SCSI Command/Data SCSI_IO I/O SCSI Input/Output SCSI_ATN I/O SCSI Attention SCSI_RST SCSI_XTAL_IN SCSI_XTAL_OUT I/O Input Output SCSI Reset SCSI Clock Crystal In (can drive with external CMOS clock) SCSI Clock Crystal Out (must not connect to any external load) 1. All of the SCSI pads (except the crystal oscillator pads) are custom NCR 48 mA bidirectional open-drain pads with hysteresis on inputs. Parallel Port Interface Name Type Description P_DATA[7:0] 3-State Parallel Port Data Bus P_D_STRB I/O Parallel Port Data Strobe (25 µA pull-down) P_BSY I/O Parallel Port Busy (25 µA pull-up) July 1997 This Material Copyrighted by Its Respective Manufacturer 5 STP2000.frm 6 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP Parallel Port Interface Name Type Description P_ACK I/O Parallel Port Acknowledge (25 µA pull-down) (ELP_PE) P_PE I/O Parallel Port Paper Error P_SLCT P_ERROR I/O Parallel Port Select Input Parallel Port Error P_INIT Output Parallel Port Initialize P_SLCT_IN Output Parallel Port Select In P_AFXN Output Parallel Port Auto Feed P_DS_DIR [1] Output Parallel Port Data Strobe Direction [1] Output Parallel Port Busy Direction P_ACK_DIR [1] Output Parallel Port Acknowledge Direction P_BSY_DIR P_D_DIR [1] ID_CS Output Parallel Port Data Direction Output Secondary Device Select (boot prom) output; pull low to specify absence of external PROM 1. The Parallel Port control and data line direction bits, (for example, P_*_DIR), are gang programmed by the DIR bit of the Transfer Control Register. DIR=0 sets transfer direction away from the STP2000 (P_D_DIR=P_DS_DIR=1; P_BSY_DIR=P_ACK_DIR=0); DIR=1 sets transfer direction towards the STP2000 (P_D_DIR=P_DS_DIR=0; P_BSY_DIR=P_ACK_DIR=1). JTAG Interface Name Type Description JTAG_TDO Output JTAG_TDI Input JTAG Test Data Output JTAG Test Data Input (100 µA pull-up) JTAG_CLK Input JTAG Clock JTAG_TMS Input JTAG Test Mode Select (100 µA pull-up) JTAG_RST Input JTAG Reset (100 µA pull-up) Clock/Oscillator Interface [1] Name SCC_20_IN Type Input SCC_20_OUT Output SCC_CLK20 Output FPY_24_IN Input Description SCC Clock Crystal In (19.66 MHz) (can drive with external CMOS clock) SCC Clock Crystal Out (19.66 MHz) (must not connect to any external load) SCC Clock Out (19.66 MHz) Floppy Clock Crystal In (24 MHz) (can drive with external CMOS clock) FPY_24_OUT Output Floppy Clock Crystal Out (24 MHz) (must not connect to any external load) FPY_CLK24 Output Floppy Clock Out (24 MHz) 6 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 7 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP Clock/Oscillator Interface [1] (Continued) Name FPY_32_IN Type Input Description Floppy Clock Crystal In (32 MHz) (can drive with external CMOS clock) FPY_32_OUT Output Floppy Clock Crystal Out (32 MHz) (must not connect to any external load) FPY_CLK32 Output Floppy Clock Out (32 MHz) 1. In some system configurations, the STP2000 provides these three clocks to the STP2001 (Slave I/O Controller) (which is pin limited). These are really general-purpose 20-50 MHz crystal oscillator pads that can operate in both fundamental and overtone mode. July 1997 This Material Copyrighted by Its Respective Manufacturer 7 STP2000.frm 8 Mon Jul 7 08:11:43 1997 STP2000QFP Master I/O 32-bit SBus Master I/O Controller ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings [1] Symbol Parameter VCC Power supply voltage VIN Input voltage II Current Drain VCC and GND TL Lead temperature (less than 10 second soldering) TJ Operating temperature TS Storage temperature Rating Units 7.0 V VCC + 0.5 V 100 mA 250 °C 0 to +70 °C -55 to +150 °C 1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Symbol Parameter Min Typ Max 4.75 5.0 5.25 V Operating Temperature 0 25 70 °C Power consumption (@ 25 MHz SBus) – 750 1400 mW VCC Supply voltage TA PD Units Capacitance Typ Max Units CIN Symbol Input capacitance Parameter 6 – pF COUT Output capacitance 6 – pF CBI Bidirectional pin capacitance 6 – pF CSCSI SCSI pin capacitance – 10 pF 8 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 9 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP DC Characteristics Symbol Parameter VIH Input high voltage VIL Input Low voltage VOH High level output voltage VOL Low level output voltage IIN Input leakage current IOH High level source current (VOH = 2.4 V) IOL Low level sink current (VOL = 0.4 V) Min Typ Max Units 2.0 – – V – – 0.8 V 4.4 4.5 – V – 0 0.1 V -10 – 10 µA IOH = 2.0 mA 2 – – mA IOH = 4.0 mA 4 – – mA IOH = 8.0 mA 8 – – mA IOH = 16.0 mA 16 – – mA IOH = 24.0 mA 24 – – mA IOL = -2.0 mA 2 – – mA IOL = -4.0 mA 4 – – mA IOL = -8.0 mA 8 – – mA IOL = -16.0 mA 16 – – mA IOL = -24.0 mA 24 – – mA IOL = -48.0 mA 48 – – mA SCSIPAD (VOL = 0.5 V) 48 – – mA SCSIPADF (VOL = 0.5 V) 48 – – mA July 1997 This Material Copyrighted by Its Respective Manufacturer 9 STP2000.frm 10 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP AC Characteristics: SBus Timing Signal # Parameter Conditions Min Max Units 1 Clock Period 40.0 60.0 ns 2 Clock High 17.0 – ns 3 Clock Low 17.0 – ns 4 Hold wrt CLK Rising 0.0 – ns 5 Setup to CLK Rising 15.0 – ns 1.0 – ns 0.0 – ns Rising [1] 6 Hold wrt CLK 7 Hold wrt CLK Rising 8 CLK Rising to Output Valid 160 pF load 2.5 22.5 ns 9 CLK Rising to Output Invalid 160 pF load 2.5 20.0 ns 1. This is the only violation of SBus Specification B.0. No known implementation to date provides less than 1.0 ns hold time on these signals. AC Characteristics: Parallel Port Timing Signal # Parameter 10 CLK to P_D_STRB 11 P_D_STRB nominal width 12 P_DATA valid to P_D_STRB assert 13 P_DATA valid (nominal) 14 P_ACK, P_BSY setup to CLK 15 16 Conditions Min Max Units 75 pF – 35 ns DSW=0,1,2,3 3 – SB_CLK periods 75 pF 5 – ns DSS=0, DSN=3 6 – SB_CLK periods 5 – ns P_ACK, P_BSY input pulse width 3 – SB_CLK periods P_D_STRB setup to CLK 5 – ns 17 P_D_STRB input pulse width 3 – SB_CLK periods 18 P_DATA setup to P_D_STRB 36 – ns 19 P_DATA input hold from P_D_STRB 4 – SB_CLK periods 20 P_D_STRB to P_BSY valid 75 pF 2 3 + 26 ns SB_CLK periods 21 CLK to P_ACK, P_BSY 75 pF – 40 ns 22 P_ACK, P_BSY nominal pulse width 75 pF 3 – SB_CLK periods 23 CLK to output 75 pF – 35 ns 10 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 11 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP AC Characteristics: SCSI TIming Signal # Parameter Conditions Min Max Units 24 Clock period (tCP) 25 83.3 ns 25 Synchronization latency tCL tCL + tCP ns 12 25 MHz 20 25 MHz With FASTCLK bit reset asynchronous [1] 26 Clock frequency, 27 Clock frequency, synchronous [1] 28 Clock high 14.58 0.65 x tCP ns 29 Clock low (tCL) 14.58 0.65 x tCP ns With FASTCLK bit set 26 Clock frequency, asynchronous [1] 20 40 MHz 27 Clock frequency, synchronous [1] 38 40 MHz 28 Clock high 0.40 x tCP 0.60 x tCP ns 29 Clock low (tCL) 0.40 x tCP 0.60 x tCP ns Asynchronous SCSI 30 Data setup to SCSI_ACK/SCSI_REQ low 31 Data hold from SCSI_REQ high/SCSI_ACK low 32 SCSI_ACK low to SCSI_REQ high 33 SCSI_ACK high to SCSI_REQ low (data already setup) 34 SCSI_REQ high to SCSI_ACK high 35 SCSI_REQ low to SCSI_ACK low (data already setup) 36 Data setup to SCSI_REQ/SCSI_ACK low 0 – ns 37 Data hold from SCSI_REQ/SCSI_ACK low – 18 ns FIFO is not empty FIFO is not full. FIFO is not full. 60 – ns 5 – ns – 50 ns – 45 ns – 50 ns – 50 ns Synchronous SCSI - Normal SCSI 38 Data setup to SCSI_REQ/SCSI_ACK low 55 – ns 39 Data hold from SCSI_REQ/SCSI_ACK low 100 – ns 40 SCSI_REQ/SCSI_ACK assertion period 90 – ns 41 SCSI_REQ/SCSI_ACK negation period 90 – ns Synchronous SCSI - Fast SCSI 38 Data setup to SCSI_REQ/SCSI_ACK low 25 – ns 39 Data hold from SCSI_REQ/SCSI_ACK low 35 – ns 40 SCSI_REQ/SCSI_ACK assertion period 30 – ns 41 SCSI_REQ/SCSI_ACK negation period 30 – ns July 1997 This Material Copyrighted by Its Respective Manufacturer 11 STP2000.frm 12 Mon Jul 7 08:11:43 1997 STP2000QFP Master I/O 32-bit SBus Master I/O Controller AC Characteristics: SCSI TIming (Continued) Signal # Parameter Conditions Min Max Units Synchronous SCSI Input Cycle 42 Data setup to SCSI_REQ/SCSI_ACK low 5 – ns 43 Data hold from SCSI_REQ/SCSI_ACK low 15 – ns 44 SCSI_REQ assertion period 27 – ns 45 SCSI_REQ negation period 20 – ns 46 SCSI_ACK assertion period 20 – ns 47 SCSI_ACK negation period 20 – ns 1. These minimum numbers are required to comply with ANSI SCSI spec. For Synchronous SCSI data transfers and FASTCLK enabled, the clock inputs must also meet the following requirements: 2t CP + tCL> 97.92 ns and 2t CP + tCH > 97.92 ns. AC Characteristics: Ethernet Timing Signal # Min Max Units 48 ENET_TCLK period Parameter 99 101 ns 49 ENET_TCLK high pulse duration 45 – ns 50 ENET_TCLK low pulse duration 45 – ns 51 ENET_TCLK rise time – 8 ns 52 ENET_TCLK fall time – 8 ns 53 ENET_TENA propagation delay after rising edge of ENET_TCLK – 25 ns 54 ENET_TENA hold time after ENET_TCLK rising 7 – ns 55 ENET_TX propagation delay after ENET_TCLK rising – 32 ns 56 ENET_TX hold time after ENET_TCLK rising 7 – ns 57 ENET_RCLK period 85 118 ns 58 ENET_RCLK high pulse duration 38 – ns 59 ENET_RCLK low pulse duration 38 – ns 60 ENET_RCLK rise time – 8 ns 61 ENET_RCLK fall time – 8 ns 62 ENET_RX data rise time – 8 ns 63 ENET_RX data fall time – 8 ns 64 ENET_RX data hold time from ENET_RCLK rising 5 – ns 65 ENET_RX data setup time to ENET_RCLK rising 40 – ns 66 ENET_RENA low duration 120 – ns 67 ENET_CLSN high duration 110 – ns 68 ENET_RENA hold time after the rising edge of ENET_RCLK 1 – ns 69 ENET_RENA defer before ENET_TENA 356 – ns 70 ENET_RENA extended after ENET_RCLK last falling – 275 ns 12 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 13 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP TIMING DIAGRAMS 1 2 3 SB_CLK 4 5 4 5 SB_BG, SB_SEL 5 6 5 7 SB_PA[W, X, Y, 5:0] CHIP_SEL, SB_RD SB_AS, SB_D[31:0] SB_SIZ[2:0] SB_ACK[2:0] SB_LERR Figure 4. SBus Input Timing 1 2 3 SB_CLK 8 9 SB_RD, SB_D[31:0] SB_ACK[2:0] SB_SIZ[2:0] 8 8 SB_BR Figure 5. SBus Output Timing July 1997 This Material Copyrighted by Its Respective Manufacturer 13 STP2000.frm 14 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP SB_CLK 16 17 P_D_STRB(out) 18 19 P_DATA[7:0] (out) 21 20 22 P_ACK (in) 22 P_BSY (in) Figure 6. Parallel Port Input Timing SB_CLK 10 11 P_D_STRB(out) 12 13 P_DATA[7:0] (out) 14 15 P_ACK (in) 15 P_BSY (in) Figure 7. Parallel Port Output Timing SB_CLK 23 23 P_SLET_IN, P_AFXN, P_INIT, P_ACK_DIR, P_BSY_DIR P_DS_DIR, P_D_DIR Figure 8. Parallel Port Other Timing 14 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 15 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP 24 28 29 SCSI_STAL_IN Figure 9. SCSI Clock Timing SCSI_REQ (out) 32 33 34 35 SCSI_ACK (out) SCSI_REQ (in) SCSI_ACK (in) 36 37 SCSI_D Figure 10. SCSI Asynchronous Input Timing SCSI_REQ (out) 32 33 34 35 SCSI_ACK (out) SCSI_REQ (in) SCSI_ACK (in) 30 31 SCSI_D Figure 11. SCSI Asynchronous Output Timing July 1997 This Material Copyrighted by Its Respective Manufacturer 15 STP2000.frm 16 Mon Jul 7 08:11:43 1997 STP2000QFP Master I/O 32-bit SBus Master I/O Controller SCSI_REQ (in) 44 45 46 47 SCSI_ACK (in) 42 43 SCSI_D (in) Figure 12. SCSI Synchronous Input Timing SCSI_REQ (out) 40 41 40 41 SCSI_ACK (out) 38 39 SCSI_D (in) SCSI_D (out) Figure 13. SCSI Synchronous Output Timing 16 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 17 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller 49 48 50 51 STP2000QFP 52 ENET_TCLK 53 69 54 ENET_TENA 55 56 ENET_TX 58 57 59 60 61 ENET_RCLK 70 68 66 ENET_RENA 62 63 65 64 ENET_RX Figure 14. Ethernet Transmit/Receive Timing 67 ENET_CLSN Figure 15. Ethernet Collision Timing July 1997 This Material Copyrighted by Its Respective Manufacturer 17 STP2000.frm 18 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP PACKAGE INFORMATION 160-Pin PQFP Pin Assignment Pin 1 Name Pin Name Pin SB_D[22] 28 P_DATA[5] 55 Name GND Pin Name 82 SCSI_SEL Pin 109 Name SB_D[1] Pin 136 Name SB_AS 2 SB_D[23] 29 P_DATA[4] 56 ENET_AUI 83 SCSI_BSY 110 SB_D[2] 137 SB_ACK[0] 3 GND 30 GND 57 ENET_TX 84 SCSI_REQ 111 SB_D[3] 138 SB_SIZ[2] 4 SB_D[24] 31 P_DATA[3] 58 ENET_TENA 85 SCSI_ACK 112 GND 139 SB_SIZ[1] 5 SB_D[25] 32 P_DATA[2] 59 ENET_CLSN 86 GND 113 SB_D[4] 140 SB_SIZ[0] 6 SB_D[26] 33 VCC 60 ENET_RX 87 SCSI_MSG 114 VCC 141 VCC 7 VCC 34 P_DATA[1] 61 ENET_RENA 88 SCSI_CD 115 SB_D[5] 142 SB_CLK 8 SB_D[27] 35 P_DATA[0] 62 ENET_TCLK 89 SCSI_IO 116 SB_D[6] 143 GND 9 SB_D[28] 36 GND 63 ENET_RCLK 90 SCSI_ATN 117 GND 144 SB_PA_W 10 SB_D[29] 37 P_ERROR 64 JTAG_TDO 91 SCSI_RST 118 SB_D[7] 145 SB_PA_X SB_P_Y 11 SB_D[30] 38 P_SLCT 65 JTAG_CLK 92 GND 119 SB_D[8] 146 12 SB_D[31] 39 P_PE 66 JTAG_TDI 93 GND 120 SB_D[9] 147 SB_PA[4] 13 GND 40 P_SLCT_IN 67 JTAG_TMS 94 GND 121 SB_D[10] 148 SB_PA[3] 14 ID_CS 41 P_AFXN 68 JTAG_RST 95 SCSI_XTAL_OUT 122 SB_D[11] 149 SB_PA[2] 15 GND 42 P_INIT 69 GND 96 SCSI_XTAL_IN 123 SB_D[12] 150 SB_PA[1] 16 SB_RESET 43 P_ACK_DIR 70 GND 97 VCC 124 VCC 151 SB_PA[0] 17 VCC 44 P_BSY_DIR 71 SCSI_D[0] 98 VCC 125 SB_D[13] 152 SB_PA[5] 18 SB_P_IRQ 45 P_DS_DIR 72 SCSI_D[1] 99 SCC_20_IN 126 SB_D[14] 153 SB_D[16] 19 SB_E_IRQ 46 P_D_DIR 73 SCSI_D[2] 100 SCC_20_OUT 127 GND 154 SB_D[17] 20 GND 47 GND 74 SCSI_D[3] 101 SCC_CLK20 128 SB_D[15] 155 SB_D[18] 21 P_ACK 48 FPY_CLK24 75 GND 102 GND 129 SB_ACK[2] 156 VCC 22 P_BSY 49 FPY_24_OUT 76 SCSI_D[4] 103 GND 130 SB_ACK[1] 157 SB_D[19] 23 P_D_STRB 50 FPY_24_IN 77 SCSI_D[5] 104 SB_D_IRQ 131 SB_BR 158 GND 24 VCC 51 VCC 78 SCSI_D[6] 105 VCC 132 SB_BG 159 SB_D[20] 25 P_DATA[7] 52 FPY_32_IN 79 SCSI_D[7] 106 SB_RD 133 SB_LERR 160 SB_D[21] 26 P_DATA[6] 53 FPY_32_OUT 80 SCSI_DP 107 GND 134 CHIP_SEL 27 VCC 54 FPY_CLK32 81 GND 108 SB_D[0] 135 SB_SEL 18 This Material Copyrighted by Its Respective Manufacturer July 1997 STP2000.frm 19 Mon Jul 7 08:11:43 1997 Master I/O 32-bit SBus Master I/O Controller STP2000QFP 19 This Material Copyrighted by Its Respective Manufacturer STP2000.frm 20 Mon Jul 7 08:11:43 1997 STP2000QFP Master I/O 32-bit SBus Master I/O Controller ORDERING INFORMATION Part Number STP2000QFP Description 160-Pin Plastic Quad Flat Package (PQFP) Document Part Number: STP2000 20 This Material Copyrighted by Its Respective Manufacturer July 1997