WEDPN8M72V-XBX HI-RELIABILITY PRODUCT 8Mx72 Synchronous DRAM FEATURES GENERAL DESCRIPTION ■ High Frequency = 100, 125MHz The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic random-access ,memory using 5 chips containing 134,217,728 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. ■ Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm ■ Single 3.3V ±0.3V power supply ■ Fully Synchronous; all signals registered on positive edge of system clock cycle Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. ■ Internal pipelined operation; column address can be changed every clock cycle ■ Internal banks for hiding row access/precharge ■ Programmable Burst length 1,2,4,8 or full page ■ 4096 refresh cycles ■ Commercial, Industrial and Military Temperature Ranges ■ Organized as 8M x 72 The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. ■ Weight: WEDPN8M72V-XBX - 2.5 grams typical BENEFITS ■ 40% SPACE SAVINGS ■ Reduced part count ■ Reduced I/O count • 19% I/O Reduction ■ Lower inductance and capacitance for low noise performance ■ Suitable for hi-reliability applications ■ Upgradeable to 16M x 72 density (contact factory for information) * This product subject to change without notice. Discrete Approach 11.9 11.9 11.9 ACTUAL SIZE 11.9 11.9 25 22.3 32 Area I/O Count April 2001 Rev. 7 S A V I N G S 5 x 265mm 2 = 1328mm 2 800mm2 40% 5 x 54 pins = 270 pins 219 Balls 19% 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX FIG. 1 PIN CONFIGURATION TOP VIEW 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DQ0 DQ14 DQ15 VSS VSS A9 A10 A11 A8 VCC VCC DQ16 DQ17 DQ31 VSS B DQ1 DQ2 DQ12 DQ13 VSS VSS A0 A7 A6 A1 VCC VCC DQ18 DQ19 DQ29 DQ30 C DQ3 DQ4 DQ10 DQ11 VCC VCC A2 A5 A4 A3 VSS VSS DQ20 DQ21 DQ27 DQ28 D DQ6 DQ5 DQ8 DQ9 VCC VCC DNU A12 DNU DNU DNU VSS VSS DQ22 DQ23 DQ26 DQ25 E DQ7 DQML0 VCC DQMH0 NC NC NC BA0 BA1 NC NC NC DQML1 VSS NC DQ24 F CAS0 WE0 VCC CLK0 NC RAS1 WE1 VSS DQMH1 CLK1 G CS0 RAS0 VCC CKE0 NC CAS1 CS1 VSS NC CKE1 H VSS VSS VCC VCC VSS VCC VSS Vss VCC VCC J VSS VSS VCC VCC VSS VCC VSS VSS VCC VCC K NC CKE3 VCC CS3 NC NC CKE2 VSS VSS RAS2 CS2 L NC CLK3 VCC CAS3 RAS3 NC CLK2 VSS WE2 CAS2 M DQ56 DQMH3 VCC WE3 DQML3 CKE4 DQMH4 CLK4 CAS4 WE4 RAS4 CS4 DQMH2 VSS DQML2 DQ39 N DQ57 DQ58 DQ55 DQ54 NC NC DQ73 DQ72 DQ71 DQ70 DQML4 NC DQ41 DQ40 DQ37 DQ38 P DQ60 DQ59 DQ53 DQ52 VSS VSS DQ75 DQ74 DQ69 DQ68 VCC VCC DQ43 DQ42 DQ36 DQ35 R DQ62 DQ61 DQ51 DQ50 VCC VCC DQ77 DQ76 DQ67 DQ66 VSS VSS DQ45 DQ44 DQ34 DQ33 T Vss DQ63 DQ49 DQ48 VCC VCC DQ79 DQ78 DQ65 DQ64 VSS VSS DQ47 DQ46 DQ32 VCC WEDPN8M72VPC.eps NOTE: DNU = Do Not Use; to be left unconnected for future upgrades. NC = Not Connected Internally. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 2 WEDPN8M72V-XBX FIG. 2 FUNCTIONAL BLOCK DIAGRAM WE0 RAS 0 CAS 0 WE RAS CAS A0-11 DQ0 BA0-1 • A0-11 BA0-1 CLK0 CKE0 CS0 DQML0 DQMH0 CLK CKE CS DQML DQMH U0 DQ0 • • • • • • • • • • • DQ15 DQ15 WE1 RAS 1 CAS 1 WE RAS CAS A0-11 DQ0 BA0-1 • CLK1 CKE1 CS1 DQML1 DQMH1 CLK CKE CS DQML DQMH U1 DQ16 • • • • • • • • • • • DQ15 DQ31 WE2 RAS 2 CAS 2 WE RAS CAS A0-11 DQ0 BA0-1 • CLK2 CKE2 CS2 DQML2 DQMH2 CLK CKE CS DQML DQMH U2 DQ32 • • • • • • • • • • • DQ15 DQ47 WE3 RAS 3 CAS 3 WE RAS CAS A0-11 DQ0 BA0-1 • CLK3 CKE3 CS3 DQML3 DQMH3 CLK CKE CS DQML DQMH U3 DQ48 • • • • • • • • • • • DQ15 DQ63 WE4 RAS 4 CAS 4 WE RAS CAS A0-11 DQ0 BA0-1 • CLK4 CKE4 CS4 DQML4 DQMH4 CLK CKE CS DQML DQMH U4 3 DQ64 • • • • • • • • • • • DQ15 DQ79 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. FUNCTIONAL DESCRIPTION Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A 0-11 select the row). The address bits (A0-8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. INITIALIZATION SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-8 when the burst length is set to two; by A2-8 when the burst length is set to four; and by A3-8 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. REGISTER DEFINITION MODE REGISTER The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selec-tion of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 3. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 WEDPN8M72V-XBX TABLE 1 - BURST DEFINITION FIG. 3 MODE REGISTER DEFINITION Burst Length Starting Column Address 2 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 4 Mode Register (Mx) Reserved* WB Op Mode CAS Latency BT Burst Length *Should program M11, M10 = 0, 0 to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access 8 Full Page (y) A2 0 0 0 0 1 1 1 1 n A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A1 A0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 = A0-9/8/7 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... (location 0-y) …Cn - 1, Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported NOTES: 1. For full-page accesses: y = 512. 2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the starting column within the block. 4. For a burst length of eight, A3-8 select the block-of-eight burst; A 0-2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-8 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-8 select the unique column to be accessed, and Mode Register bit M3 is ignored. All other states reserved 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX FIG. 4 CAS LATENCY T0 T1 T2 T3 NOP NOP CLK COMMAND READ tLZ t OH DOUT I/O t AC CAS Latency = 2 T0 T1 T2 T3 T4 NOP NOP NOP CLK COMMAND READ tLZ t OH DOUT I/O t AC CAS Latency = 3 DON’T CARE UNDEFINED CAS Latency unknown operation or incompatibility with future versions may result. The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are singlelocation (nonburst) accesses. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. The I/ Os will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the I/Os will start driving after T1 and the data will be valid by T2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. TABLE 2 - CAS LATENCY SPEED Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode -100 ≤ 75 ≤ 100 -125 ≤ 100 ≤ 125 COMMANDS The normal operating mode is selected by setting M7and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. The Truth Table provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Test modes and reserved states should not be used because White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com ALLOWABLE OPERATING FREQUENCY (MHZ) CAS CAS LATENCY = 2 LATENCY = 3 6 WEDPN8M72V-XBX TRUTH TABLE - COMMANDS AND DQM OPERATION (Note 1) NAME (FUNCTION) CS RAS CAS WE DQM ADDR I/Os COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) ( 3) L L H H X Bank/Row X READ (Select bank and column, and start READ burst) (4) L H L H L/H 8 Bank/Col X WRITE (Select bank and column, and start WRITE burst) (4) L H L L L/H 8 Bank/Col Valid BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L X Code X AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X X X LOAD MODE REGISTER (2) L L L L X Op-Code X Write Enable/Output Enable (8) – – – – L – Active Write Inhibit/Output High-Z (8) – – – – H – High-Z NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-11 define the op-code written to the Mode Register. 3. A0-11 provide row address, and BA0, BA 1 determine which bank is made active. 4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA 0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay). COMMAND INHIBIT READ The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-8 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the I/Os subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding I/Os will be High-Z two clocks later; if the DQM signal was registered LOW, the I/Os will provide valid data. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER WRITE The Mode Register is loaded via inputs A0-11. See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-8 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the I/Os is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX PRECHARGE SELF REFRESH* The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA 1 select the bank. Otherwise BA0, BA 1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. AUTO PRECHARGE AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the fullpage burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for t XSR, because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time. * Self refresh available in commercial and industrial temperatures only. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixedlength or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. Each 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every refresh period (tREF). Providing a distributed AUTO REFRESH command will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every refresh period (tREF). White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8 WEDPN8M72V-XBX CAPACITANCE (Note 2) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on VDD, VDDQ Supply relative to Vss Voltage on NC or I/O pins relative to Vss Operating Temperature TA (Mil) Operating Temperature TA (Ind) Storage Temperature, Plastic Power Dissipation -1 to 4.6 -1 to 4.6 -55 to +125 -40 to +85 -55 to +150 5 Parameter Unit V V °C °C °C W Symbol Max Unit Input Capacitance: CLK CI1 10 pF Addresses, BA0-1 Input Capacitance CA 30 pF Input Capacitance: All other input-only pins CI2 10 pF Input/Output Capacitance: I/Os CIO 12 pF NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes 1, 6) (VCC = +3.3V ±0.3V; TA = -55°C to +125°C) Parameter/Condition Symbol Units Supply Voltage VCC Min 3 Max 3.6 Input High Voltage: Logic 1; All inputs (21) VIH 2 VCC + 0.3 V Input Low Voltage: Logic 0; All inputs (21) VIL -0.3 0.8 V V Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -5 5 µA Input Leakage Address Current (All other pins not under test = 0V) II -25 25 µA Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC IOZ -5 5 µA Output Levels: Output High Voltage (IOUT = -4mA) VOH 2.4 – V Output Low Voltage (IOUT = 4mA) VOL – 0.4 V ICC SPECIFICATIONS AND CONDITIONS (Notes 1,6,11,13) (VCC = +3.3V ±0.3V; TA = -55°C to +125°C) Parameter/Condition Symbol Max Units Operating Current: Active Mode; Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19) ICC1 750 mA Standby Current: Active Mode; CKE = HIGH; CS = HIGH; All banks active after tRCD met; No accesses in progress (3, 12, 19) ICC3 250 mA Operating Current: Burst Mode; Continuous burst; Read or Write; All banks active; CAS latency = 3 (3, 18, 19) ICC4 750 mA Self Refresh Current: CKE ≤ 0.2V (Commercial Temperature: 10°C to + 70°C) (27) ICC7 8 mA Self Refresh Current: CKE ≤ 0.2V (Industrial Temperature: (-40°C to + 85°C) (27) ICC7 10 mA 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS (Notes 5, 6, 8, 9, 11) Parameter Symbol -100 Min Access time from CLK (pos. edge) -125 Max Min Unit Max CL = 3 tAC 6 6 ns CL = 2 tAC 6 — ns Address hold time tAH 1 1 ns Address setup time tAS 2 2 ns CLK high-level width tCH 3 3 ns CLK low-level width tCL 3 3 ns CL = 3 tCK 8 8 ns CL = 2 tCK 10 — ns CKE hold time tCKH 1 1 ns CKE setup time tCKS 2 2 ns CS, RAS, CAS, WE, DQM hold time tCMH 1 1 ns CS, RAS, CAS, WE, DQM setup time tCMS 2 2 ns Data-in hold time tDH 1 1 ns Data-in setup time tDS 2 2 Clock cycle time (22) Data-out high-impedance time CL = 3 (10) tHZ CL = 2 (10) tHZ 6 7 ns 6 ns — ns Data-out low-impedance time tLZ 1 1 ns Data-out hold time (load) tOH 3 3 ns Data-out hold time (no load) (26) t OHN 1.8 1.8 ACTIVE to PRECHARGE command t RAS 50 ACTIVE to ACTIVE command period 120,000 45 tRC 70 68 ACTIVE to READ or WRITE delay tRCD 20 20 Refresh period (4,096 rows) – Commercial, Industrial tREF 64 ns ns ns 64 ms — ms Refresh period (4,096 rows) – Military tREF AUTO REFRESH period tRFC 70 — ns PRECHARGE command period tRP 20 20 ns ACTIVE bank A to ACTIVE bank B command tRRD 15 tT 0.3 Transition time (7) WRITE recovery time (23) (24) Exit SELF REFRESH to ACTIVE command White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 16 ns 120,000 tWR t XSR 10 16 1.2 0.3 ns 1.2 ns 1 CLK + 7ns 1 CLK + 7ns — 15 15 ns 80 78 ns WEDPN8M72V-XBX AC FUNCTIONAL CHARACTERISTICS (Notes 5,6,7,8,9,11) Parameter/Condition Symbol -100 -125 Units READ/WRITE command to READ/WRITE command (17) tCCD 1 1 tCK CKE to clock disable or power-down entry mode (14) tCKED 1 1 tCK CKE to clock enable or power-down exit setup mode (14) tPED 1 1 tCK DQM to input data delay (17) tDQD 0 0 tCK DQM to data mask during WRITEs tDQM 0 0 tCK DQM to data high-impedance during READs tDQZ 2 2 tCK WRITE command to input data delay (17) t DWD 0 0 tCK Data-in to ACTIVE command (15) tDAL 4 5 tCK Data-in to PRECHARGE command (16) tDPL 2 2 tCK Last data-in to burst STOP command (17) tBDL 1 1 tCK Last data-in to new READ/WRITE command (17) tCDL 1 1 tCK Last data-in to PRECHARGE command (16) tRDL 2 2 tCK LOAD MODE REGISTER command to ACTIVE or REFRESH command (25) tMRD 2 2 tCK CL = 3 tROH 3 3 tCK CL = 2 tROH 2 — tCK Data-out to high-impedance from PRECHARGE command (17) NOTES: 1. All voltages referenced to VSS. 2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C. 3. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100ms is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC must be powered up simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and V IL (or between V IL and V IH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. I CC specifications are tested after the device is properly initialized. 14. Timing actually specified by t CKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The I CC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. VIH overshoot: V IH (MAX) = V CC + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. V IL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 22. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR , and PRECHARGE commands). CKE may be used to reduce the data rate. 23. Auto precharge mode only. The precharge timing budget (tRP ) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 24. Precharge mode only. 25. JEDEC and PC100 specify three clocks. 26. Parameter guaranteed by design. 27. Self refresh available in commercial and industrial temperatures only. Q 50pF 10. t HZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or V OL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have V IL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPN8M72V-XBX PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA) BOTTOM VIEW 32.32 (1.272) MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A 1.27/2 19.05 (0.750) NOM 1.27 (0.050) BSC 25.25 (0.994) MAX 1.27/2 0.60 (0.024) ± 0.10 (0.004) 219 x ∅ 0.835 2.20 (0.087) MAX 19.05 (0.750) NOM ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION WED P N 8M 72 V - XXX B X DEVICE GRADE: M = Military -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: B = 219 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 125 = 125MHz 3.3V Power Supply CONFIGURATION, 8M x 72 SDRAM PLASTIC WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 12