Z84C90
KIO Serial/Parallel Counter
Timer
Product Specification
36
=L/2*:RUOGZLGH+HDGTXDUWHUV (+DPLOWRQ$YHQXH &DPSEHOO&$ 7HOHSKRQH )D[ KWWSZZZ=L/2*FRP
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or
to request copies of publications, contact:
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
E\=L/2*,QF$OOULJKWVUHVHUYHG,QIRUPDWLRQLQWKLVSXEOLFDWLRQFRQFHUQLQJWKHGHYLFHVDSSOLFDWLRQVRU
WHFKQRORJ\GHVFULEHGLVLQWHQGHGWRVXJJHVWSRVVLEOHXVHVDQGPD\EHVXSHUVHGHG=L/2*,1&'2(6127
$6680(/,$%,/,7<)25253529,'($5(35(6(17$7,212)$&&85$&<2)7+(,1)250$7,21'(9,&(6
257(&+12/2*<'(6&5,%(',17+,6'2&80(17=L/2*$/62'2(6127$6680(/,$%,/,7<)25
,17(//(&78$/3523(57<,1)5,1*(0(175(/$7(',1$1<0$11(57286(2),1)250$7,21'(9,&(6
257(&+12/2*<'(6&5,%('+(5(,12527+(5:,6('HYLFHVVROGE\=L/2*,QFDUHFRYHUHGE\ZDUUDQW\
DQGOLPLWDWLRQRIOLDELOLW\SURYLVLRQVDSSHDULQJLQWKH=L/2*,QF7HUPVDQG&RQGLWLRQVRI6DOH=L/2*,QFPDNHVQR
ZDUUDQW\RIPHUFKDQWDELOLW\RUILWQHVVIRUDQ\SXUSRVH([FHSWZLWKWKHH[SUHVVZULWWHQDSSURYDORI=L/2*XVHRI
LQIRUPDWLRQGHYLFHVRUWHFKQRORJ\DVFULWLFDOFRPSRQHQWVRIOLIHVXSSRUWV\VWHPVLVQRWDXWKRUL]HG1ROLFHQVHVDUH
FRQYH\HGLPSOLFLWO\RURWKHUZLVHE\WKLVGRFXPHQWXQGHUDQ\LQWHOOHFWXDOSURSHUW\ULJKWV
36
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
LLL
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Precautions & Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
36
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
LY
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
KIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Z84C90 84-Pin PLCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
100-Pin VQFP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PIA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Counter/Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Op Code Fetch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
36
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
Y
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Z84C90 KIO Serial/Parallel/Counter/TimerPackages . . . . . . . . . . . . . . . . . . 1
KIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Daisy Chain Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
36
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
Z84C90
KIO Serial/Parallel Counter/Timer
Product Specification
)HDWXUHV
7DEOH =&.,26HULDO3DUDOOHO&RXQWHU7LPHU3DFNDJHV
3DUW1XPEHU
3DFNDJH
=&$6&
SLQ94)3
=&;;;
SLQ3/&&
=&9(&
SLQ3/&&
=&96&
SLQ3/&&
*HQHUDO'HVFULSWLRQ
ZiLOG’s Z84C90 Serial/Parallel/Counter/Timer KIO is a multi-channel, multipurpose I/O
device designed to provide the end-user with a cost-effective and powerful solution to
meet peripheral needs. The Z84C90 combines the features of one Z84C30 CTC, one
Z84C20 PIO, a Z84C4x SIO, a 8-bit bit-programmable I/O port, and a crystal-oscillator
into a single package (84-pin PLCC or 100-pin VQFP). Using fifteen internal registers for
data and programming information, the KIO can easily be configured to any given system
environment. Although the optimum performance is obtained with a Z84C00 CPU, the
KIO can just as easily be used with any other CPU.
)HDWXUHV
36
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
3$ 3$
$5'<
3,2
$67%
3% 3%
%5'<
26&
;7$/
;7$/
2VFLOODWRU
3,$
08;
&/.287
' '
$ $
&6
0,
5'
,254
5(6(7
%67%
%XV
,QWHUIDFH
DQG
&RQWURO
6
8
%
$
7
$
'
6
8
%
/
2
5
7
1
2
&
6
8
%
7
3
8
5
5
(
7
1
,
/
2
5
7
1
2
&
0
(
'
2
0
3& 3&9
5;'$
5;&$
7;'$
7;&$
&76$
6,2
'&'$
5;'%
5;&%
7;'%
&/.
7;&%
&76%
'&'%
=&72
&/.75*
,17
,(
,(
,QWHUUXSW
&RQWURO
=&72
&7&
&/.75*
=&72
&/.75*
=&72
&/.75*
)LJXUH .,2%ORFN'LDJUDP
36
*HQHUDO'HVFULSWLRQ
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
$EVROXWH0D[LPXP5DWLQJV
9ROWDJHRQ9&&ZLWKUHVSHFWWR966
±9WR9
9ROWDJHVRQDOOLQSXWVZLWKUHVSHFWWR
966
±9WR9&&9
2SHUDWLQJ$PELHQW7HPSHUDWXUH
6HH2UGHULQJ
,QIRUPDWLRQ
6WRUDJH7HPSHUDWXUH
±&WR&
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This rating is a stress rating only. Operation of the device at any
condition above those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
36
$EVROXWH0D[LPXP5DWLQJV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
3&2:75'<%
*1'
&76$
'&'$
'&'%
&76%
7['%
7[&%
5[&%
5['%
$
$
$
$
&6
0
5'
9
,254
5(6(7
&/.75*
3LQ7\SHV
&
&
3LQ3/&&
&/.75*
&/.75*
&/.75*
'
'
'
'
*1'
9&&
'
'
'
'
9&&
;7$/
;7$/
*1'
&/2&.
&/.287
26&
,17
3&6<1&%
3&'75%
3&576%
7['$
7[&$
5[&$
5['$
3$
3$
3$
9&&
3$
*1'
3$
3$
3$
3$
3&576$
3&'75$
3&6<1&$
3&:75'<$
*1'
*1'
3%
3%
3%
3%
3%
3%
3%
3%
%5'<
%67%
$5'<
$67%
=&72
=&72
=&72
=&72
,(
,(
9
&
&
)LJXUH =&3LQ3/&&&RQILJXUDWLRQ
36
3LQ7\SHV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
&
1
&
1
%
&
1
<
6
&
3
%
5
7
'
&
3
%
6
7
5
&
3
1&
$
'
[
7
$
&
[
7
$
&
[
5
$
'
[
5
$
3
$
3
$
3
&
&
9
$
3
' 1 $
* 3
$
3
$
3
$
3
$
6
7
5
&
3
$
5
7
'
&
3
$
&
1
<
6
&
3
$
<
'
5
7
:
&
3
&
1
&
1
1&
1&
3&:75'<%
*1'
*1'
&67$
1&
*1'
3%
'&'$
3%
'&'%
3%
&76%
3%
7['%
7[&%
5[&%
3%
3%
5['%
$
$
3%
3LQ94)3
$
3%
%5'<
%67%
$5'<
$
$67%
&6
=&72
0
=&72
5'
&&
9
,254
=&72
=&72
5(6(7
,(
&&
&/.75*
9
1&
1&
,(
1&
&
1
&
1
* * * '
5 5 5
7
7
7
. . .
/ / /
& & &
'
'
'
&
&
'
1
9
*
'
'
'
'
&
&
9
/
$
7
;
/
$
7
;
' .
1 &
* 2
/
&
1&
7 & 7
8 6 1
,
2 2
.
/
&
&
1
&
1
)LJXUH 3LQ94)3&RQILJXUDWLRQ
3LQ'HVFULSWLRQV
A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle.
ARDY, BRDY. Port Ready (outputs, Active High). These signals indicate that the port is
ready for a data transfer. In Mode 0, the signal indicates that the port has data available to
the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data
from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for
the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB signal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.
36
3LQ'HVFULSWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
1RWH Port B does not support Mode 2 operation and can only be used in
Mode 3 when Port A is programmed for Mode 2. BRDY is not
associated with Port B when it is operating in Mode 3.
ASTB, BSTB. Port Strobe (inputs, Active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
1RWH Port B does not support Mode 2 operation, and can only be used in
Mode 3 when Port A is programmed for Mode 2. BSTB is not
associated with Port B when it is operating in Mode 3.
CLK/TRG0–CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable Active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
CS. Chip Select (input, Active Low). Used to activate the internal register decoding mechanism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB. Clear to Send (inputs, Active Low). These signals are modem control signals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D0–D7. Data Bus (bidirectional, Active High, 3-stated). Used for data exchanges between
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for RETI instructions to maintain its Interrupt Under Service (IUS) status.
DCDA, DCDB. Data Carrier Detect (inputs, Active Low). These signals are modem control signals for the serial channels. When programmed for Auto Enable, a Low on these
pins enables their respective receivers. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
DTRA, DTRB. Data Terminal Ready (outputs, Active Low). These signals are modem
control signals for the serial channels. They follow the state programmed into their respective serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
36
3LQ'HVFULSWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable
Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven
device. A High on this line indicates that no higher-priority device is requesting an interrupt.
IEO. Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higherpriority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ. Input/Output Request (input, Active Low). IORQ is used with RD, A0–A3, and CS
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,
the device selected by A0–A3 transfers data to the CPU. When IORQ and CS are Active
Low, but RD is Active High, the device selected by A0–A3 is written into by the CPU.
When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1. Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
OSC. Oscillator (output). This output is a reference clock for the oscillator.
PA0–PA7. Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA0 is
the least-significant bit of the bus.
PB0–PB7. Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB0 is
the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Darlington transistors.
PC0–PC7. Port C Bus (bidirectional, tristated). PC0 is the least-significant bit of the bus.
These pins are multiplexed between the 8-bit PIA and additional modem control signals
for the serial channels.
RD. Read (input, Active Low). When RD is active, a memory or I/O read operation is in
progress. RD is used with A0–A3, CS and IORQ to transfer data between the KIO and
CPU.
RESET. Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condition. This signal must be active for a minimum of three Clock cycles. The KIO resets so
that the PIO ports operate in Mode 1
36
With handshakes inactive and interrupts disabled
PIA port in Input mode and active
CTC channel counting terminated and interrupts disabled
3LQ'HVFULSWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
SIO channels disabled
Marking with interrupts disabled.
All control registers must be rewritten after a hardware reset.
RTSA, RTSB. Request to Send (outputs, Active Low). These signals are modem control
signals for their serial channels. They follow the inverse state programmed into their
respective serial channels, and are multiplexed with Port C, bits 4 and 3, respectively.
RxCA, RxCB. Receive Clock (inputs, Active Low). These clocks are used to assemble
the data in the receiver shift register for their serial channels. Data is sampled on the rising
edge of the clock.
RxDA, RxDB. Receive Data (inputs, Active High). These pins are the input data pins to
the receive shift register for their serial channels.
SYNCA, SYNCB. Synchronization (bidirectional, Active Low). In the Asynchronous
mode of operation, these pins act much like the CTS and DCD pins. Transitions affect the
Sync/Hunt status bit for their respective serial channels, but serve no other purpose. These
pins are multiplexed with Port C, bits 6 and 1, respectively.
TxCA, TxCB. Transmit Clock (inputs, Active Low). These clocks are used to transmit
data from the transmit shift register for their serial channels. Data is transmitted on the
falling edge of the clock.
TxDA, TxDB. Transmit Data (outputs, Active High). These pins are the output data pins
from the transmitter for their serial channels.
WT/RDYA, WT/RDYB. Wait/Ready (outputs, open-drain when programmed as Wait;
tristated when programmed as Ready). These pins may be programmed as Ready lines for
a DMA controller or Wait lines for interfacing to a CPU. As a Ready line, these pins indicate (when Active Low) that the transmitter or the receiver requests a transfer between the
serial channel and the DMA. As a Wait line, these pins dictate (when Low) that the CPU
must wait until the transmitter or receiver can complete the requested transaction. These
pins are multiplexed with Port C, bit 7 and 0, respectively.
XTALI. Crystal/Clock Connection. (input).
XTALO. Crystal Connection. (output).
ZC/TO0–ZC/TO3. Zero count/Timeout (outputs, Active High). These four pins are outputs from the four counter/timer channels of the KIO. Each pin pulses High when its corresponding downcounter reaches 0.
36
3LQ'HVFULSWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7DEOH .,25HJLVWHUV
$GGUHVV
$
$
$
$
5HJLVWHU3,23RUW$'DWD
5HJLVWHU3,23RUW$&RPPDQG
5HJLVWHU3,23RUW%'DWD
5HJLVWHU3,23RUW%&RPPDQG
5HJLVWHU&7&&KDQQHO
5HJLVWHU&7&&KDQQHO
5HJLVWHU
5HJLVWHU
5HJLVWHU6,23RUW$'DWD
5HJLVWHU6,23RUW$&RPPDQG6WDWXV
5HJLVWHU6,2&KDQQHO%'DWD
5HJLVWHU6,2&KDQQHO%&RPPDQG6WDWXV
5HJLVWHU3,$3RUW&'DWD
5HJLVWHU3,$3RUW&&RPPDQG
5HJLVWHU.,2&RPPDQG
5HJLVWHU5HVHUYHG
1RWH$GGLWLRQDOO\,254DQG&6PXVWEH/RZ5HJLVWHUVDUHZULWWHQWRRUUHDGIURPE\WKH&38
DSSO\LQJDRUDUHVSHFWLYHO\RQWKH5'SLQ
6WDQGDUG7HVW&RQGLWLRQV
The DC Characteristics and Capacitance sections below apply to the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into the referenced pin.
Available operating temperature ranges are:
S = 0° C to +70° C
E = –40° C to +100° C
Voltage Supply Range: +5.0V ± 10%
All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF
increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address
and control lines. AC timing measurements are referenced to 1.5 volts (except for
CLOCK, which is referenced to the 10% and 90% points.
36
6WDQGDUG7HVW&RQGLWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section. Refer to the Literature List for additional
documentation.
9
.
)URP2XWSXW
8QGHU7HVW
S)
m$
)LJXUH 7HVW/RDG'LDJUDP
,QWHUQDO
&RQWURO
/RJLF
3RUW$
,2
'DWD
&38
%XV,2
'DWDRU
&RQWURO
+DQGVKDNH
3HULSKHUDO
,QWHUIDFH
,QWHUQDO%XV
&RQWURO
3RUW%
,2
'DWDRU
&RQWURO
+DQGVKDNH
,QWHUUXSW
&RQWURO
,QWHUUXSW&RQWURO/LQHV
)LJXUH 3,2%ORFN'LDJUDP
36
6WDQGDUG7HVW&RQGLWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
3RUW&
3&C3&
'DWD%XV
'LU
&WUO
)LJXUH 3,$%ORFN'LDJUDP
,QWHUQDO
&RQWURO
/RJLF
'DWD
&38
%XV
,(
/RJLF
,2
&RQWURO
,17
,QWHUUXSW
,QWHUQDO%XV
,(
&RXQWHU
=&72
&/.75*
7LPHU
/RJLF
5HVHW
)LJXUH &7&%ORFN'LDJUDP
36
6WDQGDUG7HVW&RQGLWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
=7$/,
&U\VWDO
,QSXWV
&
&
;7$/2
)LJXUH &U\VWDO&RQQHFWLRQ
36
6WDQGDUG7HVW&RQGLWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
'DWD
&KDQQHO$
&RQWURO
DQG
6WDWXV
5HJLVWHUV
&KDQQHO$
6HULDO
'DWD
&KDQQHO
&ORFNV
6\QF
:DLW5HDG\
,QWHUQDO
&RQWURO
/RJLF
&KDQQHO$
&RQWURO
DQG
6WDWXV
0RGHPRU
2WKHU
&RQWURO
&KDQQHO%
&RQWURO
DQG
6WDWXV
0RGHPRU
2WKHU
&RQWURO
&KDQQHO%
6HULDO
'DWD
&KDQQHO
&ORFNV
6\QF
:DLW5HDG\
&38
%XV
,2
&RQWURO
,QWHUUXSW
&RQWURO
/LQHV
,QWHUUXSW
&RQWURO
/RJLF
,
Q
W
H
U
Q
D
O
%
X
V
&KDQQHO%
&RQWURO
DQG
6WDWXV
5HJLVWHUV
)LJXUH 6,2%ORFN'LDJUDP
36
6WDQGDUG7HVW&RQGLWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
'&&KDUDFWHULVWLFV
Vcc = 5.0V +/– 10% unless otherwise specified.
7DEOH '&&KDUDFWHULVWLFVRIWKH=&
6\PERO
,WHP
0LQ
0D[
8QLW
9,/&
&ORFN,QSXW/RZ9ROWDJH
±
9
9,+&
&ORFN,QSXW+LJK9ROWDJH
9&&± 9FF
9,/
,QSXW/RZ9ROWDJH
±
9
9,+
,QSXW+LJK9ROWDJH
9FF
9
92/
2XWSXW/RZ9ROWDJH
9
,2/ P$
92+
2XWSXW+LJK9ROWDJH
9
,2+ P$
92+
2XWSXW+LJK9ROWDJH
9&&±
9
,2+ P$
,/,
,QSXW/HDNDJH&XUUHQW
P$
9LQ a9FF
,2/
6WDWH/HDNDJH&XUUHQW
P$
9LQ a9FF
,/6<
6<1&3LQ/HDNDJH
±
P$
9LQ a9FF
,2+'
'DUOLQJWRQ'ULYH&XUUHQW
3RUW%DQG=&7a
±
P$
92+ 9
5(;7 2KPV
,&&
3RZHU6XSSO\&XUUHQW
0+]
0+]
0+]
P$
P$
9&& 9
9,+ 9FF±9
9,/ 9
&XUUHQW
&RQGLWLRQ
0HDVXUHPHQWPDGHZLWKRXWSXWIORDWLQJRYHUVSHFLILHGWHPSHUDWXUHDQGYROWDJHUDQJHV
7DEOH &DSDFLWDQFH
6\PERO
3DUDPHWHU
&&/2&.
&,1
&287
&ORFN&DSDFLWDQFH
,QSXW&DSDFLWDQFH
2XWSXW&DSDFLWDQFH
0LQLPXP 0D[LPXP 8QLW
F)
F)
F)
7$ &I 0+]
36
'&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
$&&KDUDFWHULVWLFV
7DEOH$&&KDUDFWHULVWLFVRIWKH=&
1R 6\PERO
3DUDPHWHU
=&
=&
=&
0LQ
0D[
0LQ
0D[
0LQ 0D[ 80
%XV,QWHUIDFH7LPLQJ
7F&
&ORFN&\FOH7LPH
'&
'&
'& QV
7Z&K
&ORFN3XOVH:LGWK+LJK
'&
'&
'& QV
7Z&O
&ORFN3XOVH:LGWK/RZ
'&
'&
'& QV
7I&
&ORFN)DOO7LPH
QV
7U&
&ORFN5LVH7LPH
QV
7V$5OI
$GGUHVV&66HWXSWR5',254
)DOO
QV
7V5O&U
5',254WR&ORFN 5LVH6HWXS
QV
7K
+ROG7LPHIRU6SHFLILHG6HWXS
QV
7G&U'2
&/2&.5LVHWR'DWD2XW'HOD\
QV
7G5OU'2]
5',2545LVHWR'DWD2XW)ORDW
'HOD\
QV
05',2545LVHWR'DWD)ORDW
QV
7V'&U
'DWDLQWR&ORFN5LVH6HWXS
QV
7G,2,'2
,254)DOOWR'DWD2XW'HOD\
,17$&.&\FOH
7K,2U'
,2545LVHWR'DWD)ORDW,17$&.
QV
7+,2U$
,2545LVHWR$GGUHVV+ROG
QV
7V0I&U
0)DOOWR&ORFN5LVH6HWXS
QV
7V0U&I
05LVHWR&ORFN)DOO6HWXS
0&\FOH
QV
7G0I,(2I
0)DOOWR,(2)DOO'HOD\,QWHUUXSW
,PPHGLDWHO\SUHFHGLQJ0)DOO
QV
7V,(,,2I
,(,WR,254)DOO6HWXS
QV
7G,(,I,(2I
,(,)DOOWR,(2)DOO'HOD\
QV
7G,(,I,(2U
,(,5LVHWR,(25LVH'HOD\
DIWHU(''HFRGH
QV
7K5'U'
36
QV
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7DEOH$&&KDUDFWHULVWLFVRIWKH=&&RQWLQXHG
=&
=&
=&
0LQ
0LQ
0LQ 0D[ 80
1R 6\PERO
3DUDPHWHU
0D[
7V,(,&I
,(,WR&ORFN)DOO6HWXSIRU'
'HFRGH
7V,2U&I
,2545LVHWR&ORFN)DOO6HWXS
WRDFWLYDWH5'<RQQH[WFORFN
0D[
QV
QV
3,27LPLQJ
7G&I5'<U
&ORFN)DOOWR5'<5LVH'HOD\
QV
7G&I5'<I
&ORFN )DOOWR5'< )DOO'HOD\
QV
7Z67%
67%3XOVH:LGWK
QV
7V67%U&I
67% 5LVHWR&ORFN )DOO6HWXS
WRDFWLYDWH5'<RQQH[WFORFN
F\FOH
QV
7G,2I3'
,254 )DOOWR3RUW'DWD9DOLG
0RGH
7V3'67%U
3RUW$%'DWDWR67%5LVH6HWXS
7LPH0RGH
7G67%,3'
67%)DOOWR3RUW$%'DWD9DOLG
'HOD\0RGH
QV
7G67%U3']
67%5LVHWR3RUW'DWD)ORDW'HOD\
0RGH
QV
7G3',17I
3RUW'DWD0DWFKWR,17)DOO'HOD\
0RGH
QV
7G67%U,17I
67%5LVHWR,17)DOO'HOD\
QV
7V3'5,I
3,$3RUW'DWDWR5',254)DOO
6HWXS
7G&U3'
&ORFN5LVHWR3RUW'DWD9DOLG'HOD\
7%'
QV
7%'
QV
±
QV
&7&7LPLQJ
7G&U,17I
&ORFN5LVHWR,175LVH'HOD\
7F&
7V&75U&UF
&/.75*5LVHWR&ORFN5LVH6HWXS
IRULPPHGLDWHFRXQW&RXQWHU
PRGH
QV
7V&75U&UW
&/.75*5LVHWR&ORFN5LVH6HWXS
IRUHQDEOLQJSUHVFDOHURQIROORZLQJ
&ORFN 5LVH7LPHUPRGH
QV
36
7F&
QV
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7DEOH$&&KDUDFWHULVWLFVRIWKH=&&RQWLQXHG
=&
=&
=&
0LQ
0LQ
0LQ 0D[ 80
1R 6\PERO
3DUDPHWHU
7G&75U,17I
&/.75*5LVHWR,17)DOO'HOD\
7F&75
&/.75*&\FOH7LPH
7F&
'&
7F&
'&
QV
7Z&75K
&/.75*:LGWK+LJK
'&
'&
QV
7Z&75,
&/.75*:LGWK/RZ
'&
'&
QV
7U&75
&/.75*5LVH7LPH
QV
7I&75
&/.75*)DOO7LPH
QV
7G&U=&U
&ORFN5LVHWR=&725LVH'HOD\
QV
7G&I=&I
&ORFN)DOOWR=&72)DOO'HOD\
QV
7G,2I:5I
,254)DOOWR:75'<)DOO'HOD\
:DLW0RGH
QV
7G&U:5I
&ORFN5LVHWR:75'<'HOD\
5HDG\0RGH
QV
7G&I:5]
&ORFN)DOOWR:75'<)ORDW'HOD\
:DLW0RGH
QV
7Z3K
3XOVH:LGWK+LJK
QV
7Z3,
3XOVH:LGWK/RZ
QV
7F7[&
7[&&\FOH7LPH
'&
'&
QV
7Z7[&K
7[&:LGWK+LJK
'&
'&
QV
7Z7[&O
7[&:LGWK/RZ
'&
'&
QV
7U7[&
7[&5LVH7LPH
QV
7I7[&
7[&)DOO7LPH
QV
7G7[&I7['
7[&)DOOWR7[''HOD\[PRGH
QV
7G7[&I:5I
7[&)DOOWR:75'<)DOO'HOD\
5HDG\0RGH
QV
7G7[&I,17I
7[&)DOOWR,17)DOO'HOD\
QV
7F5[&
5[&&\FOH7LPH
'&
'&
QV
7Z5[&K
5[&:LGWK+LJK
'&
'&
QV
7Z5[&O
5[&:LGWK/RZ
'&
'&
QV
7V&75U&UVDWLVILHG
7V&75U&UQRWVDWLVILHG
0D[
0D[
6,27LPLQJ
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7DEOH$&&KDUDFWHULVWLFVRIWKH=&&RQWLQXHG
=&
=&
=&
0LQ
0LQ
0LQ 0D[ 80
1R 6\PERO
3DUDPHWHU
0D[
0D[
7U5[&
5[&5LVH7LPH
QV
7I5[&
5[&)DOO7LPH
QV
7V5['5[&U
5['WR5[&5LVH6HWXS
ThRxCr(RxD)
RxC 5LVHto RxD Hold Time
QV
80
60
QV
67 7G5[&U:5I 5[&5LVHWR:5'<)DOO'HOD\
5HDG\0RGH
10
13
10
13
QV
68 7G5[&I,17I
5[&WR,17)DOO'HOD\
10
13
10
13
QV
69 7G5[&U
6<1&I
5[&5LVHWR6<1&)DOO'HOD\
2XWSXW0RGH
4
7
4
7
QV
70 7V6<1&I
5[&U
6<1&)DOOWR5[&5LVH6HWXS
([WHUQDO6\QF0RGH
-100
71 7G&I,(2U
&ORFN)DOOWR,(25LVH'HOD\
90
75
QV
72 7G&I,(2I
&ORFN)DOOWR,(2)DOO'HOD\
110
90
QV
73 7K',0U5GU 'DWD+ROG7LPHWR05LVHRU5'
5LVH
74 7V05'&
6HWXSWLPHIRU0DQG5'WRFORFN
5LVLQJZLWK'DWD9DOLG
QV
-100
0
0
20
20
QV
1RWHV
0D[LPXP6,2GDWDUDWHLVI&/2&.GLYLGHGE\
)RUD=&38DERYH0+]RQH:DLWVWDWHLVUHTXLUHGWRPHHWWKLVSDUDPHWHU
7KHVHGDLV\FKDLQSDUDPHWHUVLQFOXGHFRQWULEXWLRQVIURPWKH3,26,2DQG&7&FHOOVDQGYDU\VOLJKWO\
GHSHQGLQJRQKRZWKHVHDUHRUGHUHGE\WKH.,2FRPPDQGUHJLVWHU6HH7DEOH
&RXQWHUPRGHRQO\ZKHQXVLQJDF\FOHWLPHOHVVWKDQ7F&SDUDPHWHUPXVWEHPHW
XQLWVDUH7F&
7DEOH'DLV\&KDLQ3DUDPHWHUV
0+]
0D[
0LQ
0+]
1R 6\PERO
3DUDPHWHU
7G0,(2
3,2DW
QV
&7&DW
QV
6,2DW
QV
36
0LQ
0+]
0D[
0LQ
0D[ 80
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7DEOH'DLV\&KDLQ3DUDPHWHUV&RQWLQXHG
0+]
0D[
0LQ
0+]
1R 6\PERO
3DUDPHWHU
7V,(,,2
3,2DW
QV
&7&DW
QV
6,2DW
QV
0LQ
0+]
0D[
0LQ
0D[ 80
7G,(,,(2I
QV
7G,(,,(2U
QV
1RWHVWRFDOFXODWH=.,2GDLV\FKDLQWLPLQJXVHWKH=3,2&7&DQG6,2ZLWK,2EXIIHUVRQWKHFKDLQ7KH
IROORZLQJDUHFDOFXODWLRQIRUPXODV
3DUDPHWHU0IDOOLQJWR,(2GHOD\7G0,(2 7G0,27G,(,,(27G,(,,(22XWSXW%XIIHU
'HOD\
3DUDPHWHU,(,WR,254IDOOLQJVHWXSWLPH7V,(,,2 7G,(,,(27G,(,,(27G,(,,(2,QSXW
%XIIHU'HOD\
3DUDPHWHU,(,IDOOLQJGHOD\ 7G,(,,(2I7G,(,,(2I3,27G,(,,(2I&7&7G,(,,(2I6,2,QSXWEXIIHU
'HOD\2XWSXW%XIIHU'HOD\
3DUDPHWHU,(,ULVLQJWR,(2ULVLQJGHOD\DIWHU('GHFRGH7G,(,,(2U 7G,(,,(2U3,27G,(,,(2U&7&
7G,(,,(2U6,2,QSXWEXIIHU'HOD\2XWSXW%XIIHU'HOD\
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
&ORFN
$±$
&6
,254
5'
5HDG&\FOH
'±'
5'
:ULWH&\FOH
'±'
:75'<
:DLW0RGH
:75'<
5HDG\0RGH
)LJXUH ,25HDG:ULWH7LPLQJ0 36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
&76'&'
6<1&
7[&
7['
:75'<
,17
5[&
5['
:75'<
,17
6<1&
)LJXUH 6HULDO,27LPLQJ
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
&ORFN
&/.75*
&RXQWHU
&/.75*
7LPHU
=&72
,17
)LJXUH &RXQWHU7LPHU7LPLQJ
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
&ORFN
,254
5'
3RUW&
,QSXW
3RUW&
2XWSXW
5'<
67%
0RGH
0RGH
0RGH
0RGH
,17
)LJXUH 3RUW,25HDG:ULWH7LPLQJ
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
7
7
7ZR
7ZR
7
7
&ORFN
,17
0
,254
'±'
,(
,(
)LJXUH ,QWHUUXSW$FNQRZOHGJH&\FOH
&ORFN
0
5'
'±'
,(
,(
)LJXUH 2S&RGH)HWFK&\FOH
36
$&&KDUDFWHULVWLFV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
3UHFDXWLRQV/LPLWDWLRQV
The following describe the limitations of Revision A of the Z84C90 KIO.
3UREOHP
Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge
cycle, KIO misses the status of the IE1 pin. This produces vector contention if there is a
higher interrupting device. It works fine if only one device is in the system.
:RUN$URXQG
There is no problem if the application has only one peripheral in the daisy chain. For two
or more peripherals in the system, a “hardware workaround circuit” is needed. Please contact your local Zilog representatives to get more detailed information.
3UREOHP
Reset. KIO requires the M1 signal to exit from Reset state. If the M1 signal is not
received, the KIO can not be programmed. This is not a problem for users of the Z80
CPU.
:RUNDURXQG
If the CPU is other than a Z80, an M1 signal is needed to exit RESET status. Otherwise,
the KIO can not be programmed.
3UREOHP
Port C. When Port C is used as Parallel I/O (not as SIO’s modem signals) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
:RUN$URXQG
Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This
procedure avoids the problem.
3UREOHP
Interrupt Acknowledge cycle. The KIO modifies the contents of the KIO control register
(specifically, the KIO modifies the daisy-chain configuration) if the CE pin is active during the Interrupt Acknowledge cycle (with other conditions satisfied).
36
3UHFDXWLRQV/LPLWDWLRQV
=&
.,26HULDO3DUDOOHO&RXQWHU7LPHU
:RUN$URXQG
This problem could happen under the following narrowly defined conditions:
CE signal is active throughout the Interrupt Acknowledge cycle.
The address on the bus, A3–A0, is “110b”.
During this time, bit D3 is 1.
At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal.
At the time period of CE active, IORQ active, and M1 returns to the inactive state; all
during the rising edge of the clock.
This problem is not the case with the Z80 CPU. However, other CPUs could be affected.
One of the possible workarounds is to add the condition M1 not active to generate a CE
signal.
36
3UHFDXWLRQV/LPLWDWLRQV