Vortex86SX 32-BIT x86 Embedded SoC Brief Datasheet (v1.001) DMP Electronics INC www.vortex86sx.com Vortex86SX 32-Bit x86 Embedded SoC CONTENTS 1 Overview ............................................................................3 2 Features .............................................................................3 3 Block Diagram ....................................................................4 3.1 3.2 3.3 System Block Diagram ..................................................................... 4 Functions Block Diagram ................................................................. 5 PCI Device List ............................................................................... 5 4 PIN Function List ...............................................................6 4.1 4.2 BGA Ball Map .................................................................................. 6 Signal Description ........................................................................... 7 5 Rreference Design Schematic .......................................... 22 6 Package Information ........................................................ 31 2 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC 1 Overview Vortex86SX is the x86 SoC (System on Chip) with 0.13 micron process and ultra low power consumption design (less than 1 watt). This comprehensive SoC has been integrated with rich features, such as various I/O (RS-232, Parallel, USB and GPIO), BIOS, WatchDog Timer, Power Management, MTBF counter, LoC (LAN on Chip),JTAG etc., into a 27x27 mm, 581-pin BGA packing single chip. The Vortex86SX is compatible with Win CE, Linux and DOS. It integrates 32KB write through direct map L1 cache, 16-bit ISA bus, PCI Rev. 2.1 32-bit bus interface at 33 MHz, SDRAM, DDR2, ROM controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), 2 Features x86 Processor Core – SPI (Serial Peripheral Interface), Fast Ethernet MAC, FIFO UART, USB2.0 Host and IDE controller into a System-on-Chip (SoC) design. Furthermore, this outstanding Vortex86SX SoC can not only meet the requirements of embedded applications, such as Electronics Billboard, Firewall Router, Industrial Single-Board-Computers, Receipt Printer Controller, Thin Client PC, Auto Vehicle Locator, Finger Print Identification, Web Camera Thin Server, RS232-to-TCP Transmitter. but also can meet the critical temperature demand, spanning from -40 to +85 ℃. 6 stage pipe-line – – Embedded I/D Separated L1 Cache – 16K I-Cache, 16K D-Cache SDRAM/DDRII Control Interface – 16 bits data bus – Support DLL for clock phase auto-adjustion – SDRAM support up to 133MHz – SDRAM support up to 128Mbytes – DDRII support up to 166MHz – DDRII support up to 256Mbytes IDE Controller – Support 2 channels Ultra-DMA 100 (Disk x 4) – Support 2 programable registers to decode LPC address MAC Controller x 1 PCI Control Interface – – Up to 3 sets PCI master device 3.3V I/O ISA Bus Interface – – – AT clock programmable 8/16 Bit ISA device with Zero-Wait-State Generate refresh signals to ISA interface during DRAM refresh cycle DMA Controller Interrupt Controller – – – 2 sets of 8254 timer controller Timer output is 5V tolerance I/O on 2nd Timer MTBF Counter Real Time Clock – Below 2uA power comsuption on Internal Mode (Estimation Value) FIFO UART Port x 5 (5 sets COM Port) – – – – Compatible with 16C550/16C552 Default internal pull-up Supports the programmable baud rate generator with the data rate from 50 to 460.8K bps The character options are programmable for 1 start Vortex86SX Brief Datasheet Version 1.001 Support SPP/EPP/ECP mode General Chip Selector – – – – 2 sets extended Chip Selector I/O-map or Memory-map could be configurable I/O Addressing: From 2 byte to 64K byte Memory Address: From 512 byte to 4G Byte General Programmable I/O – – Supports 40 dedicated programmable I/O pins Each GPIO pin can be individually configured to be an input/output pin USB 2.0 Host Support – – Supports HS, FS and LS 4 port PS/2 Keyboard and Mouse Interface Support – Compatible with 8042 controller Redundant System Support Speaker out Embedded 256KB Flash – – For BIOS storage The Flash could be disable & use external Flash ROM JTAG Interface supported for S.W. debugging Input clock – – Counter/Timers Parallel Port x 1 LPC (Low Pin Count) Bus Interface bits; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits Support TXD_En Signal on COM1/COM2 Port 80h output data could be sent to COM1 by software programming 14.318MHz 32.768KHz Output clock – – 24 MHz 25 MHz Operating Voltage Range – – Core voltage: 1.2 V ~ 1.4V I/O voltage: 1.8V ± 5% , 3.3 V ± 10 % Operating temperature – -40℃ ~ 85℃ Package Type – 27x27mm, 581 ball BGA 3 Vortex86SX 32-Bit x86 Embedded SoC 3 Block Diagram 3.1 System Block Diagram 4 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC 3.2 Function Block Diagram (Internal) 3.3 PCI Device List Device# 0 1 2 3 4 IDSEL AD11 AD12 AD13 AD14 Function NB PCI PCI SLOT1 SLOT2 0 5 6 7 8 AD15 AD18 PCI PCI SB SLOT3 SLOT4 9 10 11 12 AD19 AD21 AD22 AD23 MAC USB0 USB1 IDE OHCI OHCI Function USB0 USB1 1 EHCI EHCI Vortex86SX Brief Datasheet Version 1.001 13 5 Vortex86SX 32-Bit x86 Embedded SoC BGA Ball Map 4.1 26 25 24 23 22 21 20 A AD25 AD26 AD27 AD28 AD29 PCICLK_2 B TRDY_ C AD31 AD21 AD19 AD17 FRAME_ IRDY_ AD24 CBE_3 CBE_2 AD16 AD18 AD20 AD30 D AD13 E F G AD3 H AD2 AD1 J PCI_Interface PCIRST_ AD4 M DP0 N AVSSPLL0 REXT0 P DM3 DP3 TOP VIEW DP1 AVDD2 AC Vss_io Vss_io PDD2 PDD6 PDD1 PDD8 PDD7 PDD11 Vdd_io Vss_core RI4/SA1 DTR4_/SA0 Vdd_io Vdd_io Vss_io Vss_io PDRQ PDACK_ PCBLID_ PDD4 PIOR_ PDD15 PCS0_ PDD14 AE GPIO_Interface AD W AB V AA U RTC_Xin Y DP2 AF 26 25 DCD2_/PWM0CLK DSR2_/PWM0GATE XOUT_14.318 POWER_GOOD CLK25MOUT CTS2_/PWM1GATE MTBF Vdd_pll_0 Vss_io Vss_io Vss_io 21 22 Vdd_io RTS1_/GPIO_42 RI1_/GPIO_43 SOUT1/GPIO_41 GPIO_P1_5 TXD_EN1 Vdd_io Vdd_io 24 XIN_14.318 Vdd_pll_1 Vdd_core RTS2_/PWM1OUT SIN2/PWM2CLK CLK24MOut DTR2_/PWM2OUT TXD_EN2/PWM2GATE AVDD3 SPEAKER Vss_pll_1 AVSS3 LAD3 SERIRQ RTC_Xout AVDDPLL1 LAD2 23 REXT1 AVDD33_1 LAD1 Vss_io PDD12 PDD5 PDD0 PDD13 DSR1_/GPIO_46 DCD1_/GPIO_40 RI2_/PWM1CLK Vss_pll_0 SOUT2/PWM0OUT AVSSPLL1 AVSS2 LAD0 E_SPI_DI/GPIOP_33 SYSFAILOut_ Ext_Switch_fail Vdd_core E_SPI_CLK/GPIOP_31 CTS1_/GPIO_47 DTR1_/GPIO_45 DM2 USB_Interface R T RXP DM1 AVSS1 AVDD1 RXN AVDD0 AVDD33_0 DM0 VSSABG AVDDPLL0 AVSS0 VCCA1 VSSA0 Link/Active VCCABG VSSA1 ETHERNET K L TXP TXN VCCA0 VSSAPLL Duplex RTC_IRQ8_/GPIO_34 RTC_RD_GPIO_36 RTC_PS GPIO_P1_2 RTC_AS_GPIO_37 VBat 20 GPIO_P1_3 RXC0 SIN1/GPIO_44 GPIO_P2_1/SA25 GPIO_P0_7 RXDV0 Vss_io LDRQ_ TXEN0 GPIO_P2_7/SA31 GPIO_P2_6/SA30 E_SPI_CS/GPIOP_30 Vdd_core VBatGnd RTC_WR_GPIO_35ExtSysFailIn_ EXT_GPCS_ E_SPI_DO/GPIOP_32 LFRAME_ LPC_Interface Vss_core 19 Vss_io GPIO_P1_0 Vss_io Vdd_io BA1 VCCK CAS_ VCCK PDD10 PIOW_ PDD3 GPIO_P1_4 GPIO_P2_4/SA28 GPIO_P2_2/SA26 GPIO_P2_5/SA29 Vdd_io GPIO_P1_6 INTD_ RXD0_3 GPIO_P1_7 GPIO_P2_0/SA24 PGNT2 RXD0_0 TXC0 AD6 VCCAPLL ISET AD7 AD8 AD12 INTA_ AD0 AD5 ROM_CS_ CBE_1 AD11 PAR AD9 INTC_ ATSTN ATSTP VCC_SPI CBE_0 AD10 AD22 TEST3 TEST1 TEST4 AD15 AD14 STOP_ DEVSEL_ TEST0 TEST2 GND_SPI AD23 INTB_ PGNT0 TXD0_0 PREQ2 PCICLK_0 TXD0_3 19 VCC3V 18 VCC3V GPIO_P0_3 PGNT1 GPIO_P0_1 GPIO_P2＿3/SA27 GPIO_P0_5 PREQ0 GPIO_P1_1 PREQ1 GPIO_P0_6 18 PCICLK_1 Vss_io 17 Vss_io GPIO_P0_2 Vss_core GPIO_P0_4 Vss_io GPIO_P0_0 Vss_io 16 Vdd_io SD14 RXD0_2 SD15 RXD0_1 GPCS1_ TXD0_1 GPCS0_ TXD0_2 MD14 IOR_ GND_R3 MD0 SD3 15 GNDK MD4 MSDATA DQM1 17 Vss_core Vss_core KBDATA/A20GATE_ SD12 14 Vss_core DRQ7 SD11 13 Vss_io LA19 LA21 DACK_2 Vdd_io Vss_io MSCLK GND_R3 LA23 SD6 SA5 12 VCC3V Vss_io Vss_core KBCLK_KBRST_ Vss_core Vss_core COL0 MD15 LA18 LA22 SA1 11 MDIO MD9 Vss_io Vss_core Vss_core MDC MD1 LA20 SD2 MEMW_ DRQ6 10 GND_R3 MD3 Vdd_io Vdd_core Vss_core Vdd_core DQS1 16 Vss_io Vdd_core Vdd_core Vss_io VCC3V Vss_io Vss_io Vdd_io GND_R3 VCC3V Vdd_io GND_R3 GND_R3 GND_R3 VCC3V VCC3V MD8 SBHE_ SD8 SD10 SYSCLK 9 VCC3V MD12 SA2 IRQ9 Vss_core DACK_6 SD9 MEMR_ 8 VCC3V MD11 SD4 Vss_core SD13 LA17 OSC14M 7 VCC3V MD7 IOCHCK_ DRQ0 Vss_core DACK_0 IOCHRDY_ DACK_7 6 GND_R3 MD2 RAM_Interface GNDK GNDK GND_R3 15 VCCK SA3 SA4 DRQ2 0WS_ IRQ7 REFRESH_ 5 Vdd_io MD10 DRQ5 DACK_5 IRQ12 IRQ5 IRQ10 TC 4 GND_R3 DQS0 SMEMR_ SA17 SA8 SA7 SA9 IRQ15 3 VCCK DQM0 GNDK GNDK GNDK VCCK GNDK GNDK GNDK CS_0 GNDK GNDK GNDK RAS_ MA13 GNDK MD5 SA19 AEN Vdd_core SA18 BALE IRQ11 2 VCC3V SMEMW_ SA10 Vdd_core DRQ1 IOCS16_ IRQ14 GND_R3 SD0 Vss_core Vdd_core SA11 IRQ3 VCCK Vdd_io Vss_core SA0 SA13 MEMCS16_ GND_R3 SD7 Vdd_io Vss_core SA6 IRQ4 VCCK DRQ3 Vdd_io DACK_1 IRQ6 AE GND_R3 SD5 SA16 SA14 AD VCCK DACK_3 SA12 RSET_DRV AC GND_R3 IOW_ SA15 AB 1 SD1 AA GND_R3 MD13 BA0 MA11 MA12 CS_1 BA2 MA9 GNDDLL0 MD6 MA6 MA7 VDLL0 14 MA10 MA5 MA4 GNDK ERR_/SDD14 PIORDY PA0 PRST_ W R V P U N T M AF Y VCC3V 12 MA1 MA3 GNDK PDD9 PA1 CTS4_/SIOW_ DCD4_/SA2 PINT SIN4 IDE_Interface/COM Port SOUT4 AFD_/SDD15 SLIN_/SDD12 L DSR4_/SCS1_ RTS4_/SINT TMS PE/SDD9 MA8 TCK SIN9 RTS3_/SRST_ TESTCLK K PCS1_ PD5/SDD5 BUSY/SDD10 SLCT/SDD8 PD7/SDD7 ACK_/SDD11 PD4/SDD4 SIN3 VPLL1 GNDPLL1 PD6/SDD6 SOUT9 GNDDLL1 GNDO TDO VDLL1 GNDK GNDO GNDO GNDPLL0 MA2 VCCO GNDO GNDO VCCK VCCO GNDO GNDO GNDK 7 VCCO GNDO VCCO WE_ 11 MA0 13 10 9 SDRAMCLKN SDRAMCLKP 6 VCCO 8 TDI 5 VCCK S2N PD3/SDD3 N2S J PD2/SDD2 PD1/SDD1 H STB_/SCS0_ GNTx_ G PA2 CTS3_/SIOR_ PD0/SDD0 DCD3_/SDRQ F DSR3_/SCBLID_ DTR3_/SDACK_ INIT_/SDD13 RI3/SIORDY SOUT3 E REQx_ VPLL0 GNDO D VCCO 3 Pin #1 Corner C VCCO B VCCO A 4 2 1 IS A _Interface Vortex86SX Brief Datasheet Version 1.001 6 PIN Function List 4 Vortex86SX 32-Bit x86 Embedded SoC 4.2 Signal Description This chapter provides a detailed description of Vortex86SX signals. A signal with the symbol ”_n” at the end of itself indicates that this pin is low active. Otherwise, it is high active. The following notations are used to describe the signal types: I Input pin O Output pin OD Output pin with open-drain I/O Bi-directional Input/Output pin z System (7 PINs) PIN No. z Symbol Type AA26 PWRGOOD I AB26 Y26 25MOUT XOUT_14.318 O O Y25 XIN_14.318 I AA25 AB25 MTBF CLK24MOUT O Y23 SPEAKER O Description Power-Good Input. This signal comes from Power Good of the power supply to indicate that the power is available. The Vortex86SX uses this signal to generate reset sequence for the system. 25MHz Clock output. Crystal-out. Frequency output from the inverting amplifier (oscillator). Crystal-in. 14.318MHz frequency input, within 100 ppm tolerance, to the amplifier (oscillator). MTBF Flag output. 24MHz Clock output Speaker Output. This pin is used to control the Speaker Output and should be connected to the Speaker SDRAM /DDRII Interface (44 PINs) PIN No. Symbol Type B9 SDRAMCLK O A9 SDRAMCLKN O D13 RAS_ O E12 CAS_ O C13 WE_ O B13, E13 CS_[1:0] O B14, D17 DQM[1:0] O E16, D14 DQS[1:0] I/O Vortex86SX Brief Datasheet Version 1.001 Description Clock output. This pin provides the fundamental timing for the SDRAM /DDR controller. Clock output. This pin provides the fundamental timing for the SDRAM /DDR controller. Row Address Strobe. When asserted, this signal latches row address on positive edge of the SDRAM/DDR clock. This signal also allows row access and pre-charge. Column Address Strobe. When asserted, this signal latches column address on the positive edge of the SDRAM/DDR clock. This signal also allows column access and pre-charge. Memory Write Enable. This pin is used as a write enable for the memory data bus. Chip Select CS[1:0]. These two pins activate the SDRAM devices. First Bank of SDRAM accepts any command when the CS0_n pin is active low. Second Bank of SDRAM accepts any command when the CS1_n pin is active low. For DDRII, only CS0_n activates the DDR device. Data Mask DQM[1:0]. These pins act as synchronized output enables during read cycles and byte masks during write cycles. Data Strobe DQS[1:0 for DDR only. Output with write data, input with the read data for source synchronous operation. 7 Vortex86SX 32-Bit x86 Embedded SoC Bank Address BA[1:0]. These pins are connected to SDRAM/DDR as bank address pins. Strap[17:16]. Memory Select, Default pull high. Strap[17] F12, D12 BA[1:0]/Strap[17:16] O C12 BA[2] O D16, C17, C14, D15, C15, E14, C16, E15, B15, A13, A14, A17, A16, A15, B16, B17 MD[15:0] I/O A10 MA[0] O A11 MA[1]/Strap[1] O C9 MA[2] O B10 MA[3] /Strap[3] O Strap[16] DRAM Select 0 0 SDRAM 0 1 Reserved 1 0 DDR 1 1 DDRII (Default) Bank Address [2]. These pins are connected to SDRAM/DDR as bank address pins. Memory Data MD[15:0]. These pins are connected to the SDRAM/DDR data bus. Memory Address MA[0]. Normally, these pins are used as the row and column address for SDRAM/DDR. Memory Address MA[1]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[1]. Pull it high to enable GPIO2. Default pull high. Pull it low to enable Address[31:24]. Memory Address MA[2]. Normally, these pins are used as the row and column address for SDRAM/DDR. Memory Address MA[3]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[3]. PLL_TEST_OUT_EN_, Default pull low. Pull it high to enable PLL_TEST_OUT_EN_. Pull it low to disable PLL_TEST_OUT_EN_. Memory Address MA[4]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[4]/[10]. SDRAM/DDR clock, Default pull high. C10 MA[4] /Strap[4] O C11,B12,B11 MA[7:5]/Strap[7:5] I/O F9 MA[8]/Strap[8] I/O Strap[10] Strap[4] SDRAM clock 0 0 100MHz 0 1 133MHz (Internal default) 1 0 166MHz 1 1 200MHz Memory Address MA[7:5]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[7:5] / CPU Clock 3b’000 / Bypass mode 3b’001 / SYN_DISABLE_ (CPU clock same to SDRAM Clock) 3b’010 / 233MHz 3b’011 / 266MHz 3b’100 / 300MHz (Internal default) 3b’101 / 333MHz 3b’110 / 366MHz 3b’111 / 400MHz Memory Address MA[8]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[8]. Pull it high to enable Vortex86SX JTAG. Default internal pull-high. 8 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC z z D11 MA[9]/Strap[9] I/O A12 MA[10]/Strap[10] I/O E11 MA[11]/Strap[11] I/O F11,F10 MA[13:12]/ Strap[13:12] I/O Memory Address MA[9]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[9]. Pulled low: 33 PINS is for IDE2. Pulled high: 33 PINS is for COM3/4 and Parallel Port. Default internal pull-high. Memory Address MA[10]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[4]/[10]. SDRAM/DDR clock, Default pull low. Strap[10] Strap[4] Memory clock 0 0 100MHz 0 1 133MHz (Internal default) 1 0 166MHz 1 1 200MHz Memory Address MA[11]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[11]. Pulled low is Internal RTC. Default internal pull-low. Pulled high is External RTC Memory Address MA[13:12]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[13:12]. 00 : flash-8bits 01 : flash-16bits 11 : Internal SPI. Default internal pull-high. USB 0, 1, 2, 3 (10 PINs) PIN No. Symbol Type N26 N25 USB0_DP USB0_DM I/O M26 M25 USB1_DP USB1_DM I/O T26 T25 USB2_DP USB2_DM I/O R26 R25 USB3_DP USB3_DM I/O P26 REXT[0]: I U26 REXT[1]: I Description Universal Serial Bus Controller 0 Port 0. These are the serial data pair for USB Port 0. 15kΩ pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 0 Port 1. These are the serial data pair for USB Port 1. 15kΩ pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 1 Port 0. These are the serial data pair for USB Port 2. 15kΩ pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 1 Port 1. These are the serial data pair for USB Port 3. 15kΩ pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 0 External Reference Resistance. 510Ω ±10% Universal Serial Bus Controller 1 External Reference Resistance. 510Ω ±10% PCI Bus Interface (56 PINs) PIN No. Symbol Type B19, B18, C18 PREQ_[2:0] I D19, D18 ,C19 PGNT_[2:0] O D26 PCIRST_ O A19 A18 A20 PCICLK_0 PCICLK_1 PCICLK_2 O Vortex86SX Brief Datasheet Version 1.001 Description PCI Bus Request. These signals are the PCI bus request signals used as inputs by the internal PCI arbiter. PCI Bus Grant. These signals are the PCI bus grant output signals generated by the internal PCI arbiter. PCI Reset. This pin is used to reset PCI devices. When it is asserted low, all the PCI devices will be reset. PCI Clock Output. This clock is used by all of the Vortex86SX logic that is in the PCI clock domain. 9 Vortex86SX 32-Bit x86 Embedded SoC C20, B20, A21 A22, A23, A24, A25, B26, D20, E20, C21, B21, C22, B22, C23, B23, E24, E25, E26, H22, G23, F26, F25, H21, G25, J22, G26, H25, H26, J25, J26, H24 AD[31:0] I/O B25, B24, G22, F24 CBE_[3:0] I/O C24 FRAME_ I/O C25 IRDY_ I/O C26 TRDY_ I/O D24 DEVSEL_ I/O D25 STOP_ I/O G24 PAR I/O H23 INTA_ I F19 INTB_ I F20 INTC_ I E19 INTD_ I PCI Address and Data. The standard PCI address and data lines. The address is driven with PCI Frame assertion and data is driven or received in the following clocks. Bus Command and Byte Enables. During the address phase, C/BE_n[3:0] define the Bus Command. During the data phase, C/BE[3:0]_n define the Byte Enables. PCI Frame. This pin is driven by a PCI master to indicate the beginning and duration of a PCI transaction. PCI Initiator Ready. This pin is asserted low by the master to indicate that it is able to transfer the current data transfer. A data was transferred if both IRDY_n and TRDY_n are asserted low during the rising edge of the PCI clock. PCI Target Ready. This pin is asserted low by the target to indicate that it is able to receive the current data transfer. A data was transferred if both IRDY_n and TRDY_n are asserted low during the rising edge of the PCI clock. Device Select. This pin is driven by the devices which have decoded the addresses belonging to them. PCI Stop. This pin is asserted low by the target to indicate that it is unable to receive the current data transfer. PCI Parity. This pin is driven to even parity by PCI master over the AD[31:0] and C/BE_n[3:0] bus during address and write data phases. It should be pulled high through a weak external pull-up resistor. The target drives parity during data read. PCI INTA_. PCI interrupt input A. It connects to PCI INTA_n when normal modes of PCI Interrupts are supported. PCI INTB_. PCI interrupt input B. It connects to PCI INTB_n when normal modes of PCI Interrupts are supported. PCI INTC_. PCI interrupt input C. It connects to PCI INTC_n when normal modes of PCI Interrupts are supported. PCI INTD_. PCI interrupt input D. It connects to PCI INTD_n when normal modes of PCI Interrupts are supported. EXTERNAL SPI/PORT[3-0] Interface (4 PINs) z PIN No. Symbol Type W21 E_SPI_CS_/GPIO_P3[0] I/O W22 E_SPI_CLK/GPIO_P3[1] I/O Y21 E_SPI_DO/GPIO_P3[2] I/O Y22 E_SPI_DI/GPIO_P3[3] I/O z Description External SPI Chip Select General-Purpose Input/Output P3[0] External SPI Clock General-Purpose Input/Output P3[1] External SPI Data Ouput General-Purpose Input/Output P3[2] External SPI Data Input General-Purpose Input/Output P3[3] ISA Bus Interface ( 87 PINs) PIN No. Symbol Type Description AA13 IOCHCK_ I I/O Channel Check. Provides the system board with parity (error) information about memory or devices on the I/O channel. AE16, AF16, AD10, AF15, AF14, AE11, AE10, AD12,Y6, AD14, Y4, AA14, SD[15:0] I/O ISA high and low byte slot data bus. These are the system data lines. These signals read data and vectors into CPU during memory or I/O read cycles or interrupt acknowledge cycles and outputs data from CPU during 10 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC AA16, AC14, Y1, AA7 memory or I/O write cycles. ISA system ready. This input signal is used to extend the ISA command width for the CPU and DMA cycles. ISA address enable. This active high output indicates that the system address is enabled during the DMA refresh cycles. AE8 IOCHRDY_ I AB8 AEN O AA3, AA1, AB2, AD2,AA2, AD3, AB7, AE5, AC7, AD6, AC2, AE13, AB11, AA12, AB13 AF12, AC3 SA[16:0] O AA9, AD5, AB9 SA[19:17] O AC13 SBHE_ O AC15, AD13, AE14, AA15, AD15, AB15, AE9 LA[23:17] O ISA latched address bus. These are input signal during ISA master cycle. MEMR_ MEMW_ RST_DRV O O O ISA memory read. This signal is an input during ISA master cycle. ISA memory write. This signal is an input during ISA master cycle. Driver Reset. This output signal is driven active during system power up. AF4, AF2, AC8, AF3, AE6, AB14, AE7, AC1, AD7, AD1, AE2 IRQ[7:3], IRQ[12:9], IRQ[15:14] I Interrupt request signals. These are interrupt request input signals. AE15, AF11, AA11, Y5, AC9, AD4, AB12 DRQ[7:5], DRQ[3:0] I DMA device request. These are DMA request input signals. AD8 0WS_ I AA10 SMEMR_ O AA8 SMEMW_ O Y2 AB16 IOW_ IOR_ O O AF7, AD11, AB10, Y3, AF13, AB3, AD9 DACK_[7:5], DACK_[3:0] O AF6 REFRESH_ O AF10 SYSCLK O AF5 TC O AE4 BALE O AE1 AE3 AF8 MEMCS16_ IOCS16_ OSC14M I I O Refresh cycle indicator. ISA master uses this signal to notify DRAM needs refresh. During the memory controller's self-acting refresh cycle, M6117D drives this signal to the I/O channels. System Clock Output. This signal clocks the ISA bus. DMA end of process. This is the DMA channel terminal count indicating signal. Bus address latch enable. BALE indicates the presence of a valid address at I/O slots. ISA 16-bit memory device select indicator signal. ISA 16-bit I/O device select indicator signal. 14.318MHz clock out Description AF9 AE12 z ISA slot address bus. These signals are high impedance during hold acknowledge. ISA slot address bus. ISA slot address bus for 62-pin slot. ISA Bus high enable. In master cycle, it is an input polarity signal and is driven by the master device. ISA zero wait state. This is the ISA device zero-wait state indicator signal. This signal terminates the CPU ISA command immediately. ISA system memory read. This signal indicates that the memory read cycle is for an address below 1M byte address. ISA system memory write. This signal indicates that the memory write cycle is for an address below 1M byte address. ISA I/O write. This signal is an input during ISA master cycle. ISA I/O read. This signal is an input during ISA master cycle. DMA device acknowledge signals. These are DMA acknowledge demultiplex select signals. Input function is for hardware setting. Chip Selection Interface (3 PINs) PIN No. Symbol Type AC16 GPCS0_ O ISA Bus Chip Select 0. This pin is the chip select for ISA bus. AD16 GPCS1_ O G21 ROMCS_/SPICS_ O ISA Bus Chip Select 1. This pin is the chip select for ISA bus. ROM Chip Select. This pin is used as a ROM chip select. SPI Chip Select. This pin is used as SPI flash chip select. Vortex86SX Brief Datasheet Version 1.001 11 Vortex86SX 32-Bit x86 Embedded SoC z z Redundant (4 PIN) PIN No. Symbol Type U21 U22 V22 V21 EXTSYSFAILIN_ SYSFAILOUT_ EXT_SWITCH_FAIL_ EXT_GPCS_ I O I I Symbol Description Type V13 KBCLK/KBRST I/O V16 KBDAT/A20GATE I/O V14 V15 MSCLK MSDAT I/O I/O Keyboard Clock. This pin is keyboard clock when used internal 8042. Keyboard Reset. This pin is Keyboard reset when used external 8042. Keyboard Data. This pin is keyboard data when used internal 8042. Address Bit 20 Mask. This pin is A20 mask when used external 8042. Mouse Clock. This pin is mouse clock when used internal 8042. Mouse Data. This pin is mouse data when used internal 8042. RTC/PORT3[7-4] Interface (7 PINs) PIN No. Symbol Type Description N21 RTC_AS /GPIO_P3[7] I/O RTC Address Strobe. This pin is used as the RTC Address Strobe and should be connected to the RTC. RTC_RD_ /GPIO_P3[6] I/O RTC Read Command. This pin is used as the RTC Read Command and should be connected to the RTC. RTC_WR_ /GPIO_P3[5] I/O RTC_IRQ8_ /GPIO_P3[4] I/O P22 T21 R22 z External system fail input. This pin is the system fail in for redundant. System fail output. This pin is the system fail out for redundant. External switch fail. This pin is the switch input for redundant. External GPCS input. This pin is the GPCS in for redundant. KBD/MOUSE Interface (4 PINs) PIN No. z Description General-Purpose Input/Output GPIO P3[7]. General-Purpose Input/Output GPIO P3[6]. RTC Write Command. This pin is used as the RTC Write Command and should be connected to the RTC. General-Purpose Input/Output GPIO P3[5]. RTC Interrupt Input. This pin is used as the RTC Interrupt input. General-Purpose Input/Output GPIO P3[4]. T22 RTC_PS I RTC Battery Power Sense. V25 RTC_XOUT O V26 RTC_XIN I Crystal-out. Crystal-in. COM1/PORT4 Interface (9 PINs) PIN No. Symbol Type Description Receive Data. FIFO UART receiver serial data input signal. AE21 SIN1/GPIO_P4[4] I/O General-Purpose Input/Output GPIO port4 [4]. Transmit Data. FIFO UART transmitter serial data output from the serial port. AE22 AF22 12 SOUT1/GPIO_P4[1] RTS1/GPIO_P4[2] I/O I/O General-Purpose Input/Output GPIO port4 [1]. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. General-Purpose Input/Output GPIO port4 [2]. Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC AE23 AF23 AF24 AD22 CTS1/GPIO_P4[7] DSR1/GPIO_P4[6] DCD1/GPIO_P4[0] RI1/GPIO_P4[3] I/O I/O I/O I/O AD23 DTR1/GPIO_P4[5] I/O AD21 TXD_EN1 I/O Vortex86SX Brief Datasheet Version 1.001 Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. General-Purpose Input/Output GPIO port4 [7]. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. General-Purpose Input/Output GPIO port4 [6]. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. General-Purpose Input/Output GPIO port4 [0]. Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. General-Purpose Input/Output GPIO port4 [3]. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. General-Purpose Input/Output GPIO port4 [5]. COM1 TX Status. This pin will be high when COM1 is trnamitting. 13 Vortex86SX 32-Bit x86 Embedded SoC z COM2/PWM Interface (9 PINs) PIN No. Symbol Type Description COM2 Receive Data. FIFO UART receiver serial data input signal. AF25 SIN2/PWM2CLK I AE24 SOUT2/PWM0OUT O AD25 AD26 AE26 AC26 RTS2/PWM1OUT CTS2/PWM1GATE DSR2/PWM0GATE DCD2/PWM0CLK O I I I PWM Timer2 Clock. This pin is PWM timer2 external clock input when SB register C0h bit2 is 1 (PINs for PWM). COM2 Transmit Data. FIFO UART transmitter serial data output from the serial port. PWM Timer0 Output. This pin is PWM timer0 output when SB register C0h bit2 is 1 (PINs for PWM). Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. PWM Timer1 Output. This pin is PWM timer1 output when SB register C0h bit2 is 1 (PINs for PWM). Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. PWM Timer1 Gate. This pin is PWM timer1 gate mask when SB register C0h bit2 is 1 (PINs for PWM). Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. PWM Timer0 Gate. This pin is PWM timer0 gate mask when SB register C0h bit2 is 1 (PINs for PWM). Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. PWM Timer0 Clock. This pin is PWM timer0 external clock input when SB register C0h bit2 is 1 (PINs for PWM). 14 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC AD24 AC25 RI2/PWM1CLK I DTR2/PWM2OUT O Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. PWM Timer1 Clock. This pin is PWM timer1 external clock input when SB register C0h bit2 is 1 (PINs for PWM). Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. PWM Timer1 Output. This pin is PWM timer1 output when SB register C0h bit2 is 1 (PINs for PWM). COM2 TX Status. This pin will be high when COM2 is trnamitting. AE25 z z TXD_EN2/PWM2GATE I/O PWM Timer2 Gate. This pin is PWM timer2 gate mask when SB register C0h bit2 is 1 (PINs for PWM). COM3, 4, 9 (6 PIN) Description PIN No. Symbol Type G3 SIN3 I COM3 Receive Data. FIFO UART receiver serial data input signal. G2 SOUT3 O COM3 Transmit Data. FIFO UART transmitter serial data output from the serial port. N6 SIN4 I COM4 Receive Data. FIFO UART receiver serial data input signal. M6 SOUT4 O COM4 Transmit Data. FIFO UART transmitter serial data output from the serial port. K6 SIN9 I COM9 Receive Data. FIFO UART receiver serial data input signal. J6 SOUT9 O COM9 Transmit Data. FIFO UART transmitter serial data output from the serial port. IDE 0, 1/COM3,4,PRINT1 Interface (58 PINs) PIN No. Symbol K4, K5, L5, M4, K3, M2, L2, K2 PD[7:0]/SDD[7:0] N5 SLCT/SDD8 L6 M5 PE/SDD9 BUSY/SDD10 Type I/O Description Parallel port data bus bit . Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. I/O IDE Secondary Channel Data Bus. SLCT. An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. I/O IDE Secondary Channel Data Bus. PE. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. I/O IDE Secondary Channel Data Bus. BUSY. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. Vortex86SX Brief Datasheet Version 1.001 15 Vortex86SX 32-Bit x86 Embedded SoC L4 ACK_/SDD11 M3 SLIN_/SDD12 J1 INIT_/SDD13 N4 ERR_/SDD14 L3 AFD_/SDD15 I/O IDE Secondary Channel Data Bus. SLIN_. Output line for detection of printer selection. Refer to the description of SLIN_: OD the parallel port for the definition of this pin in ECP and EPP mode. SDD12: I/O IDE Secondary Channel Data Bus. INIT_. Output line for the printer initialization. Refer to the description of the INIT_: OD parallel port for the definition of this pin in ECP and EPP mode. SDD13: I/O IDE Secondary Channel Data Bus. ERR_. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for I/O the definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. AFD_. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel AFD_: OD port for the definition of this pin in ECP and EPP mode. SDD15: I/O H3 RTS3_/SRST_ O J2 DCD3_/SDRQ I P6 CTS4_/SIOW_ I/O H2 CTS3_/SIOR_ ACK_. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. I/O IDE Secondary Channel Data Bus. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. IDE Secondary Channel Reset. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. IDE Secondary Channel DMA Request. Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. IDE Secondary Channel IO Write Strobe. Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. IDE Secondary Channel IO Read Strobe. 16 Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC G1 F1 U6 V5 H1 V6 R6 RI3/SIORDY DTR3_/SDACK_ RTS4_/SINT RI4/SA1 DSR3_/SCBLID_ DTR4_/SA0 DCD4_/SA2 I O I/O I/O I O I Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. IDE Secondary Channel IO Channel Ready. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. IDE Secondary Channel DMA Acknowledge. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. IDE Secondary Channel Interrupt. Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. IDE Secondary Channel Device Address. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. IDE Secondary Channel Cable Assembly Type Identifier. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. IDE Secondary Channel Device Address. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. IDE Secondary Channel Device Address. Vortex86SX Brief Datasheet Version 1.001 17 Vortex86SX 32-Bit x86 Embedded SoC L1 T6 STB_/SCS_0 DSR4_/SCS1_ STB_. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP STB_: OD and EPP mode. SCC_0: I IDE Secondary Channel Chip Select. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a “1”. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. I IDE Secondary Channel Chip Select. M1 PRST_ O IDE Primary Channel Reset. V2, W2, P1, P5, U5, P4, N3, U3, U4 T4, R4, U2, N1, R5, T5, T3 PDD[15:0] I/O IDE Primary Channel Data Bus. R1 PDRQ I IDE Primary Channel DMA Request. R3 PIOW_ O IDE Primary Channel IO Write Strobe. V1 PIOR_ O IDE Primary Channel IO Read Strobe. P3 PIORDY I IDE Primary Channel IO Channel Ready. T1 PDACK_ O IDE Primary Channel DMA Acknowledge. N2 PINT I IDE Primary Channel Interrupt. K1, P2, R2 PA[2:0] O IDE Primary Channel Device Address U1 PCBLID_ I IDE Primary Channel Cable Assembly Type Identifier. W1 PCS0_ O IDE Primary Channel Chip Select. T2 PCS1_ O IDE Primary Channel Chip Select. LPC Bus Interface (7 PINs) z PIN No. Symbol Type W24 SERIRQ I/O W23, V23, U23, T23 LAD[3:0] I/O U18 LFRAME_ O V18 LDRQ_ I 18 Description Serial Interrupt Request. This pin is used to support the serial interrupt protocol of common architecture. LPC Command, Address and Data LAD[3:0]. These pins are used to be command/address/data pins of Low-Pin-Count Function. Low Pin Count FRAME_n Signal. This signal is used as a frame signal of low pin count protocol.. Low Pin Count DMA Request Signal. This signal is used as a DMA request signal of low pin count protocol. Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC z GPIO Interface (24 PINs) PIN No. Symbol Type Description AA18, AA17, AE18, AE17, AF18, AF17, AC17, AD17, AA19, AC19, AD19, AE19, AB18, AC18, AB17, AF19 GPIO_P0[7:0] GPIO_P1[7:0] I/O General-Purpose Input/Output P0[7-0] and P1[7-0]. Those pins can be programmed input or output individually. AA20, AB20, AD20, GPIO_P2[7:0]/Addre AE20, AD18, AF20, ss[31:24] AF21, AB19 z z General-Purpose Input/Output P2[7-0] . Those pins can be programmed input or output individually. I/O Address[31:24]. Ethernet Interface (24 PINs) PIN No. Symbol L22 K22 J24 F22 F21 K25 K26 L25 L26 Link/Active Duplex ISET ATSTP ATSTN TXN TXP RXN RXP J16 MDC O K16 MDIO I/O L16 COL0 I M21 RXC0 I M18, M17, L17, L18 RXD0_[3:0] I L21 RXDV0 I J21 TXC0 I J18, J17, K17, K18 TXD0_[3:0] O K21 TXEN0 O Description Type Link/Active: Link/active status Duplex: Duplex status ISET: External resistor connecting pin for BIAS ATSTP: VGA and ADC testing pin for input and output (positive) ATSTN: VGA and ADC testing pin for input and output (negative) TXN: 10B-T/100BT transmitting output pin/ reveiving input pin (positive) TXP: 10B-T/100BT transmitting output pin/ reveiving input pin (negative) RXN: 10B-T/100BT reveiving input pin/ transmitting output pin (positive) RXP: 10B-T/100BT reveiving input pin/ transmitting output pin (negative) MDC: MII management data clock is sourced by the Vortex86SX to the external PHY devices as a timing reference for the transfer of information on the MDIO signal. MDIO: MII management data input/output transfers control information and status between the external PHY and the Vortex86SX. COL0: This pin functions as the collision detection. When the external physical layer protocol (PHY) device detects a collision, it asserts this pin. RXC0: Supports the receive clock supplied by the external PMD device. This clock should always be active. RXD0_[3:0]: Four parallel receiving data lines. This data is driven by an external PHY attached to the media and should be synchronized with the RXC signal. RXDV0: Data valid is asserted by an external PHY when the received data is present on the RXD[3:0] lines and is de-asserted at the end of the packet. This signal should be synchronized with the RXC signal. TXC0: Supports the transmit clock supplied by the external PMD device. This clock should always be active. TXD0_[3:0]: Four parallel transmit data lines. This data is synchronized to the assertion of the TXC signal and is latched by the external PHY on the rising edge of the TXC signal. TXEN0: This pin functions as Transmit Enable. It indicates that a transmission to an external PHY device is active on the MII port. JTAG Interface (4 PINs) Description PIN No. Symbol Type G6 TDO O TDO: JTAG Test Data Output pin. J9 G7 H6 TMS TCK TDI I I I TMS: JTAG Test Mode Select pin. Vortex86SX Brief Datasheet Version 1.001 TCK: JTAG Test Clock Input pin. TDI: JTAG Test Data Input pin. 19 Vortex86SX 32-Bit x86 Embedded SoC TEST PIN (10 PIN) z Description PIN No. Symbol Type J3 E23, E21, D22, E22, D23, F2, F3, E2, E3 TESTCLK I/O For Testing used TEST[8:0] I/O For Testing used. Test 3 and Test 4 must pull high to 3.3V. 1.2V POWER (14 PINs) z Description PIN No. Symbol Type D9, D10 VDDLL (2 PINs) I DLL power E9, E10 GNDDLL (2 PINs) I DLL ground VCCK (10 PINs) I Core power GNDK (17 PINs) I Code ground F8,F13,F14,G4, J14,K14,L14,N9 ,M14,P9 E7,E8,E17,J10, J11,J12,K9, K10,K11,K12, L9,L10,L11, L12,M9,M10, M11 1.8V POWER (57 PINs) z PIN No. Type VCCO (8 PINs) I SDR/DDRII power (3.3V/1.8V) GNDO (9 PINs) I SDR/DDRII gound Vdd_core (10 PINs) I Core power Vss_core (18 PINs) I Core ground AVDD[3:0] I Analog power AVSS[3:0] I Analog gound V24, N23 AVDDPLL[1:0] I USB PLL power U25, P25 AVSSPLL[1:0] I USB PLL ground C4,C5,C6,C7, D4,D7,D8,E4 D5,D6,E5,E6, F4,F5,F6,F7, G5 AA21,AA22, AA23,AC4, AC5,AC6,T11, T12,U10,V10 T16, T17, T18, U11, U12, U13, U14, U15, U16, V4, V11, V12, AB4, AB5, AB6, AC10, AC1, AC12 N22, R24, R23, W26 N24, P23, T24, W25 z 20 Description Symbol Battery POWER (2 PIN) PIN No. Symbol Type P21 R21 VBat VBatGnd I I Description Battery power for RTC Battery gound for RTC Vortex86SX Brief Datasheet Version 1.001 Vortex86SX 32-Bit x86 Embedded SoC z 3.3V Power (87 PINs) Description PIN No. Symbol Type H4, J4 VPLL (2 PINs) I Analog power H5, J5 GNDPLL (2 PINs) I Analog gound AA24, AB24 Vdd_pll (2 PINs) I Analog power Y24, AC24 Vss_pll (2 PINs) I Analog gound VCC3V (12 PINs) I Analog power GND_R3 (15 PINs) I Analog gound Vdd_io (17 PINs) I IO power Vss_io (23 PINs) I IO gound K23 VSSAPLL I Analog ground J23 VCCAPLL I Analog power M22 VSSABG I Analog gound M23 VCCABG I Analog power K24 VCCA0 I Analog power L23 VSSA0 I Analog gound L24 VCCA1 I Analog power M24 VSSA1 I Analog gound P24 AVDD33_0 I Analog power U24 AVDD33_1 I Analog power F23 VCC_SPI I SPI flash power D21 GND_SPI (2 PINs) I SPI flash ground E18, F18, J15, K15, L15, M15, M16, P10, P11, P12, P13, P14 F15, F16, F17, J13, K13, L13, M12, M13, N10, N11, N12, N13, N14, N15, N16 AA4, AA5, AA6, AC21, AC22, AC23, N17, N18, P15, P16, R9, R10, R13, R14, V3, W3, W4 P17, P18, R11, R12, R15, R16, R17, R18,T9, T10, T13, T14, T15, U9, U17, V9, V17, W5, W6, AB21, AB22, AB23, AC20 Vortex86SX Brief Datasheet Version 1.001 21 A B C D IOCHRDY IOCHCK AEN SBHE MEMR MEMW RSTDRV OWS SMEMR SMEMW IOW IOR REFRESH MEMCS16 IOCS16 OSC BALE TC SYSCLK 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 8 8 8 8 8 8 8 8 8 8 8 5 AE2 AD1 AD7 AC1 AE7 AB14 AE6 AF3 AC8 AF2 AF4 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 REFRESH AF6 MEMCS16 AE1 IOCS16 AE3 R22 22 AF8 BALE AE4 TC AF5 R23 22 AF10 IOCHRDY AE8 IOCHCK AA13 AEN AB8 SBHE AC13 MEMR AF9 MEMW AE12 RSTDRV AB1 OWS AD8 SMEMR AA10 SMEMW AA8 IOW Y2 IOR AB16 AA7 Y1 AC14 AA16 AA14 Y4 AD14 Y6 AD12 AE10 AE11 AF14 AF15 AD10 AF16 AE16 -REFRESH -MEMCS16 -IOCS16 OSC14M BALE TC SYSCLK -IOCHRDY -IOCHCK AEN -SBHE -MEMR -MEMW RSET_DRV -0WS -SMEMR -SMEMW -IOW -IOR IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ09 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 SD00 SD01 SD02 SD03 SD04 SD05 SD06 SD07 SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 Vortex86SX U1B SD[0..15] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD[0..15] 8 8 -GPCS0 -GPCS1 -ROMCS DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 LA17 LA18 LA19 LA20 LA21 LA22 LA23 SA00 SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 4 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 GPCS0 GPCS1 AD9 AB3 AF13 Y3 AB10 AD11 AF7 AC16 AD16 G21 LA17 LA18 LA19 LA20 LA21 LA22 LA23 AE9 AB15 AD15 AA15 AE14 AD13 AC15 AB12 AD4 AC9 Y5 AA11 AF11 AE15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA[0..19] AC3 AF12 AB13 AA12 AB11 AE13 AC2 AD6 AC7 AE5 AB7 AD3 AA2 AD2 AB2 AA1 AA3 AB9 AD5 AA9 SA[0..19] ISA BUS 4 TP1 GPCS0 GPCS1 DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 LA17 LA18 LA19 LA20 LA21 LA22 LA23 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 3 3 8 PCICLK1 PCICLK1 FRAMEIRDYTRDYDEVSELSTOPPAR 8 8 8 8 8 8 INT-A INT-B INT-C INT-D PCIRST- 8 8 8 8 8 F24 G22 B24 B25 CBE-0 CBE-1 CBE-2 CBE-3 2 C19 D18 D19 PGNT-0 H23 F19 F20 E19 C24 C25 C26 D24 D25 G24 FRAMEIRDYTRDYDEVSELSTOPPAR INT-A INT-B INT-C INT-D D26 PCIRST- A20 A18 A19 C18 B18 B19 PREQ-0 PCICLK1R CBE-0 CBE-1 CBE-2 CBE-3 8 8 8 8 22 PGNT-0 8 R21 PREQ-0 8 2 -INTA -INTB -INTC -INTD -FRAME -IRDY -TRDY -DEVSEL -STOP PAR -PCIRST PCICLK2 PCICLK1 PCICLK0 CBE0 CBE1 CBE2 CBE3 PGNT0 PGNT1 PGNT2 PREQ0 PREQ1 PREQ2 Vortex86SX H24 J26 J25 H26 H25 G26 J22 G25 H21 F25 F26 G23 H22 E26 E25 E24 B23 C23 B22 C22 B21 C21 E20 D20 B26 A25 A24 A23 A22 A21 B20 C20 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD[0..31] Monday, January 29, 2007 Date: Vortex86SX PCI/ISA BUS Document Number Vortex86SX SOC Reference Design Size Title DMP ELECTRONICS INC. AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 U1C PCI BUS 1 2 AD[0..31] Sheet 1 of 8 8 Rev 1.1 A B C D A B C D VCC3 VCC3 VCC3 L11 L8 L5 5 103 104 C19 103 C18 104 VCCA0 C8 C7 BEAD VCCA0 K21 J21 K18 K17 J17 J18 K16 J16 F22 F21 VCC1.8 VCC1.8 L12 L9 104 104 C20 BEAD 104 C9 BEAD REXT0 REXT1 DP3 DM3 DP2 DM2 DP1 DM1 DP0 DM0 U1F 103 C21 AVDD3 103 C10 AVDD1 103 C4 AVDD0 AVDD33_1 AVDD33_0 AVSSPLL1 AVDDPLL1 AVSSPLL0 AVDDPLL0 AVSS3 AVDD3 AVSS2 AVDD2 AVSS1 AVDD1 AVSS0 AVDD0 CLK25MOUT C3 BEAD VSSA1 VCCA1 VSSA0 VCCA0 VSSABG VCCABG VSSAPLL VCCAPLL COL0 RXC0 RXDV0 RXD00 RXD01 RXD02 RXD03 TXEN0 TXC0 TXD00 TXD01 TXD02 TXD03 MDIO MDC ATSTP ATSTN Link/Active Duplex ISET RXP RXN TXP TXN Vortex86SX L6 M24 L24 L23 K24 M22 M23 K23 J23 L16 M21 L21 L18 L17 M17 M18 VCC1.8 VCCABG VCCAPLL VCCABG 103 BEAD C2 104 L26 L25 K26 K25 LINK/ACTIVE L22 DUPLEX K22 R24 6.19K 1% J24 RXIN+ RXIN- TXD+ TXD- VCCAPLL C1 BEAD LAN 5 M26 M25 P24 U24 P25 N23 U25 V24 N24 N22 P23 R24 T24 R23 W25 W26 AB26 4 VCC3 VCC1.8 VCC1.8 AVDD33 L13 L10 L7 AVDDPLL1 AVDDPLL0 AVDD3 AVDD1 AVDD0 510 510 USBD3+ USBD3- U26 R25 P26 R26 USBD2+ USBD2- USBD1+ USBD1- USBD0+ USBD0- N26 N25 R26 R25 T26 T25 4 104 C22 BEAD 104 C11 BEAD 104 C5 BEAD 103 C23 AVDD33 103 C12 AVDDPLL1 103 C6 AVDDPLL0 USBx4 3 3 4 TXD+ TXD- C14 R32 50 104 50 50 104 50 C15 104 104 2 TX+ CMT TX- RX- CT RX+ 2 16 15 14 9 10 11 U5 U6 U7 U8 H3 H4 2 4 6 8 10 75 R33 75 R34 GGND 75 R35 75 R36 L2 L7 L8 L1 L6 L5 L4 L3 L10 L12 Monday, January 29, 2007 Date: Vortex86SX LAN/USB Document Number Vortex86SX SOC Reference Design 102/3KV C17 1 Sheet UL-2 TDNC NC TD+ RONC NC RO+ PLED0 PLED1 Size Title 1K R28 3 HOLE HOLE VCC VCC 1K R27 1 USB1B1 VCC GGND LUSBD0LUSBD0+ LUSBD3LUSBD3+ VCC U1 U2 U3 U4 H5 H6 VCC DUPLEX LINK/ACTIVE HEADER 5X2/BOX 1 3 5 7 9 J2 LP-ISM110 0805 TX/RX LINK F2 UL-1 VCC -DATA +DATA GND HOLE HOLE VCC -DATA +DATA GND HOLE HOLE LP-ISM110 0805 USB1A1 F1 DMP ELECTRONICS INC. ATX+ CCMT ATX- ARX- CCT ARX+ GGND LUSBD2LUSBD2+ GGND LUSBD1LUSBD1+ TS6121A TD+ CT TD- CT RD- RD+ U3 C16 1 2 3 7 8 R31 LUSBD3+ LUSBD3- LUSBD0+ LUSBD0- RXIN- C13 1 3 SF2012900YSB R30 2 L4 3 SF2012900YSB 1 USBD2+ USBD2- USBD1+ USBD1- 6 R29 USBD3+ 4 4 USBD0+ USBD3- 2 USBD0- L3 LUSBD2+ 1 2 SF2012900YSB LUSBD2- 4 SF2012900YSB LUSBD1+ 3 L2 2 1 LUSBD1- L1 RXIN+ LAN 3 of H1 H2 8 GGND Rev 1.1 RJ45 L9 L11 USBx2 USBx2 A B C D A B C VCC3 CR2354 C FM160 C 1N4148 1M 22pF BT1 330 D2 A R42 D1 A C29 C28 R40 22pF C27 R39 22pF Y25 V26 XY1 5 104 C30 VBAT VCC3 VCC3 R21 F2 E2 E3 F3 P21 V25 VCC1.2 XY2 32.768KHz Y2 Y26 XX2 14.318MHz Y1 XX1 Y23 SPEAKER 1M 22pF C26 AA25 U21 U22 V22 V21 K6 J6 V13 V16 V14 V15 AA26 MTBF-OUT SYS-FAIL-IN SYS-FAIL-OUT SYS-SW-IN SYS-GPCS-IN RXD9\ TXD9\ KBCLK KBDATA MSCLK MSDATA 5 L20 L19 L18 VBatGnd -REQx -GNTx N2S S2N VBat RTC_Xout RTC_Xin 103 104 103 104 C41 103 C40 104 BEAD C39 C38 BEAD C37 E10 D10 E9 D9 J5 J4 H5 H4 Y24 AA24 AC24 AB24 D23 E22 D22 E21 E23 J3 G6 H6 G7 J9 AB25 T23 U23 V23 W23 U18 V18 W24 VDLL0 VPLL0 VDDPLL0 GNDDLL0 VDLL0 GNDDLL1 VDLL1 GNDPLL1 VPLL1 GNDPLL0 VPLL0 Vss_pll_1 Vdd_pll_1 Vss_pll_0 Vdd_pll_0 TEST0 TEST1 TEST2 TEST3 TEST4 TESTCLK TDO TDI TCK TMS CLK24MOut LAD0 LAD1 LAD2 LAD3 -LFRAME -LDRQ SERIRQ U1G C36 BEAD XOUT_14318 XIN_14318 SPEAKER MTBF -ExtSysFailIn -SYSFAILOut Ext_Switch_fail EXT_GPCS SIN9 SOUT9 KBCLK/-KBRST KBDATA/-A20GATE MSCLK MSDATA POWER_GOOD Vortex86SX VCC3 VDLL0 VPLL0 VDDPLL0 TDO TDI TCK TMS 4 4 JTAG LPC BUS 2 2 SPEAKER GPCS0 GPCS1 10pF C24 MTBF-OUT R44 GPCS0 GPCS1 3 1 2 3 4 5 J3 HEADER 5-1.25mm RN19 10Kx4 104 C35 LED2 A LED3 LED-SMD C A MTBF LED LED-SMD C POWER LED 3904 Q1 R43 SPEAKER 4.7K 2 4 6 8 10 R46 R45 22 HEADER 5X2-2.0mm 1 3 5 7 9 J6 REDUNDANCY SYS-FAIL-OUT TXD9\ TCK TDO TDI TMS VCC3 3 7 5 3 1 8 6 4 2 PWRGD 2 1 2 1 D + - VCC 1K 1K BUZZER SP1 RXD9\ R41 SYS-FAIL-IN SYS-GPCS-IN SYS-SW-IN JTAG VCC VCC 4.7K VCC 2 2 1 2 MSDATA MSCLK KBDATA KBCLK VCC HEADER 2 J4 47pF C31 47pF C33 F3 V 47pF C34 L16 L17 L14 L15 BEAD BEAD BEAD BEAD LP-ISM110 0805 104 C25 1K VCC GND -RST G Date: Size Title Vortex86SX KBD/MS/LPC/JTAG Monday, January 29, 2007 Document Number Vortex86SX SOC Reference Design 1K PWRGD Sheet 1 4 17 16 15 14 13 of MOUSE KBD PS/2 KB/MS 7 8 9 10 11 12 1 2 3 4 5 6 J5 8 KBD/MOUSE R PWRGD R38 R37 U4 MAX809S VCC3 Rev 1.1 GGND 6 POWER GOOD 1 VCC3 DMP ELECTRONICS INC. 47pF C32 RN20 10Kx4 VCC 1 3 5 7 2 4 6 8 A B C D A 5 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 AB19 AF21 AF20 AD18 AE20 AD20 AB20 AA20 GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 B AF19 AB17 AC18 AB18 AE19 AD19 AC19 AA19 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 U1E -DCD2/PWM0CLK SOUT2/PWM0OUT -RTS2/PWM1OUT -RI2/PWM1CLK SIN2/PWM2CLK DTR2_/PWM2OUT -DSR2/PWM0GATE -CTS2/PWM1GATE TXD_EN2/PWM2GATE -DCD1/GPIO40 SOUT1/GPIO41 -RTS1/GPIO42 -RI1/GPIO43 SIN1/GPIO44 -DTR1/GPIO45 -DSR1/GPIO46 -CTS1/GPIO47 TXD_EN1 RTC_IRQ8/GPIO34 -RTC_WR/GPIO35 -RTC_RD/GPIO36 RTC_AS/GPIO37 RTC_PS -E_SPI_CS/GPIO30 E_SPI_CLK/GPIO31 E_SPI_DO/GPIO32 E_SPI_DI/GPIO33 HEADER 10X2/BOX 2 4 6 8 10 12 14 16 18 20 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 VCC 2 4 6 8 10 12 14 16 18 20 VCC HEADER 10X2/BOX 1 3 5 7 9 11 13 15 17 19 J12 SPICS SPICLK SPIDO SPIDI GP34 GP35 GP36 GP37 GPIO PORT 2/3 VCC 1 3 5 7 9 11 13 15 17 19 J9 VCC GPIO PORT 0/1 GPIO_P20/SA24 GPIO_P21/SA25 GPIO_P22/SA26 GPIO_P23/SA27 GPIO_P24/SA28 GPIO_P25/SA29 GPIO_P26/SA30 GPIO_P27/SA31 GPIO_P10 GPIO_P11 GPIO_P12 GPIO_P13 GPIO_P14 GPIO_P15 GPIO_P16 GPIO_P17 GPIO_P00 GPIO_P01 GPIO_P02 GPIO_P03 GPIO_P04 GPIO_P05 GPIO_P06 GPIO_P07 Vortex86SX GP00 GP01 GP02 GP03 GP04 GP05 GP06 GP07 C D AD17 AC17 AF17 AF18 AE17 AE18 AA17 AA18 GP00 GP01 GP02 GP03 GP04 GP05 GP06 GP07 5 DCD1\ TXD1\ RTS1\ RI1\ RXD1\ DTR1\ DSR1\ CTS1\ TXDEN1 DCD2\ TXD2\ RTS2\ RI2\ RXD2\ DTR2\ DSR2\ CTS2\ TXDEN2 AC26 AE24 AD25 AD24 AF25 AC25 AE26 AD26 AE25 GP34 GP35 GP36 GP37 R22 T21 P22 N21 T22 AF24 AE22 AF22 AD22 AE21 AD23 AF23 AE23 AD21 SPICS SPICLK SPIDO SPIDI W21 W22 Y21 Y22 4 4 1uF C42 1K R47 VBAT VCC3 R49 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MAX213 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- U7 T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ RS232 MAX213 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- U5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 104 C49 RI2 DTR2 CTS2 TXD2 RTS2 104 C45 RI1 DTR1 CTS1 TXD1 RTS1 1 2 3 4 2MB SPI ROM 3 CS# VCC SO HOLD# WP#/ACC SCLK GND SI U9 8 7 6 5 R48 DCD2 DSR2 RXD2 DCD1 DSR1 RXD1 VCC3 Option 104 C50 VCC 104 C46 VCC 1K SPICLK SPIDI VCC3 External SPI FLASH 104 SPICS SPIDO 1K 104 C47 C48 104 104 VCC C44 DCD2\ RTS2\ DSR2\ RXD2_A CTS2\ TXD2\ DTR2\ RI2\ VCC C43 VCC CTS1\ TXD1\ DTR1\ RI1\ DCD1\ RTS1\ DSR1\ RXD1_A RS232 3 TXD2\ RXD2_B TXDEN2 RXD2_A RXD2\ RXD2_B TXD1\ RXD1_B TXDEN1 RXD1_A RXD1\ RXD1_B 1 2 3 4 1 2 3 4 U6 VCC DA+ DBGND U8 2 ADM483 DO DO_E DI_E DI 1-RS485+ 1-RS485- VCC DA+ DBGND 8 6 7 5 2-RS485+ 2-RS485- RI2 DTR2 CTS2 TXD2 RTS2 RXD2 DSR2 DCD2 RI1 DTR1 CTS1 TXD1 RTS1 RXD1 DSR1 DCD1 L29 L30 L31 L32 L33 L34 L35 L36 L21 L22 L23 L24 L25 L26 L27 L28 Monday, January 29, 2007 Date: Vortex86SX GPIO/COM/PWM Document Number Vortex86SX SOC Reference Design 1 Sheet 2-RS485+ 2-RS485- BEAD BEAD BEAD BEAD BEAD BEAD BEAD BEAD 1-RS485+ 1-RS485- Size Title 1 BEAD BEAD BEAD BEAD BEAD BEAD BEAD BEAD DMP ELECTRONICS INC. VCC RS232/RS485 SEL 1-2:COM2 RS232 2-3:RS485 8 6 7 5 HEADER 3 1 2 3 J10 RS485 ADM483 DO DO_E DI_E DI VCC RS232/RS485 SEL 1-2:COM1 RS232 2-3:RS485 HEADER 3 1 2 3 J7 RS485 2 J45A1 GGND H1 H2 H3 H4 GGND DCON9MX2 J45B1 5 of 8 Rev 1.1 HEADER 3-2.54mm/BOX 1 2 3 J11 RS485-2 14 18 13 17 12 16 11 15 10 COM2 HEADER 3-2.54mm/BOX 1 2 3 J8 RS485-1 DCON9MX2 5 9 4 8 3 7 2 6 1 COM1 A B C D A B C F8 F13 F14 J14 K14 L14 M14 N9 P9 G4 F23 VCC1.2 VCC3 5 N17 N18 P15 P16 R9 R10 R13 R14 V3 W3 W4 AA4 AA5 AA6 AC21 AC22 AC23 VCC3 D21 E18 F18 J15 K15 L15 M15 M16 P10 P11 P12 P13 P14 VCC3 V12 V11 V4 U16 U15 U14 U13 U12 U11 T18 T17 T16 AB4 AB5 AB6 AC10 AC11 AC12 GND_SPI VCC_SPI VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V Vortex86SX U1H Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io J13 F17 F16 F15 N16 N15 N13 N12 N11 N10 N14 M13 M12 L13 K13 E7 E8 E17 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 P17 P18 R11 R12 R15 R16 R17 R18 T9 T10 T13 T14 T15 U9 U17 V9 V17 W5 W6 AB21 AB22 AB23 AC20 VCC 4 C96 VCC VCC 104 C109 47uF C97 VCC 3.3V C116 47uF 47uF 3 ADJ 1 R2 R1 R1 R2 OUT 2 SOT223 VIN + - 3 R51 330 1% R50 200 1% C99 104 C98 47uF R57 R55 10K 10K C113 220pF C112 220pF 8 7 5 6 4 2 3 SENSE2- PLLLPF VFB2 ITH2 SGND ITH1 VFB1 SENSE1- 3 0.8*(1+78.7K/150K)=1.2197V R61 78.7K/1% R59 150K/1% R54 121K/1% 1 U11 104 104 104 C53 104 C54 VCC3 104 C55 VCC3 104 C56 VCC3 104 C57 VCC3 C65 47uF C64 47uF C63 47uF 47uF 47uF 47uF 104 104 VCC3 C62 VCC3 C61 VCC3 C60 VCC3 C59 VCC3 C58 VCC3 VCC3 VCC3 104 104 104 C83 VCC 104 C68 104 C84 VCC 104 C69 104 C85 VCC 104 C70 104 C86 VCC 104 C71 104 C87 VCC 104 C72 VIN SENSE2+ EXTCLK PGOOD PGATE2 PGND PGATE1 9 10 11 12 13 14 15 16 R58 R56 104 C102 0.03/1206 R60 0 0 0.03/1206 R53 104 104 VCC C101 C100 104 C104 2 R62 0 1 2 5 6 Q3 FDC638P 4 Q2 FDC638P 6 4 5 2 1 104 C103 C95 47uF C94 47uF 47uF 47uF 47uF 47uF 104 104 C110 VCC1.2 4 C111 VCC1.8 C115 VCC1.2 47uF Monday, January 29, 2007 Date: Vortex86SX POWER Document Number Vortex86SX SOC Reference Design Size Title 1 Sheet 47uF DMP ELECTRONICS INC. PWRGD 47uF C114 47uF VCC1.8 47uF 47uF 47uF 4.7uH/07x07 VCC C93 47uF L38 VCC C92 C108 D4 1N5820 VCC C91 C107 D3 1N5820 VCC C90 C106 4.7uH/07x07 VCC C89 C105 L37 VCC C88 VCC 47uF 47uF 47uF 47uF 47uF 47uF 104 104 VCC C80 C79 C78 C77 C76 C75 C74 C73 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 C82 C81 VCC 104 104 VCC C67 C66 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 C52 C51 SENSE+ LTC3701 VCC3 0.8*(1+150K/121K)=1.791735V R52 150K/1% IN VOUT VOUT 2 4 HEADER 2-5.0mm 1 2 J13 U10 AIC1086-SOT223 VCC VCC3 + 1 2 + 1 2 + 1 2 T11 T12 U10 V10 AA21 AA22 AA23 AC4 AC5 AC6 VCC3 VCC3 + 1 2 + 1 D VCC1.8 1 1 + 1 2 + 1 2 + 1 2 POWER CONNECTOR 1 2 + 1 2 + 1 2 + 1 6 of 8 VCC 1.2V VCC 1.8V BYPASS 2 U1I Vortex86SX + 1 2 ADJ 2 + 1 2 3 + 1 2 1 + 1 2 + 1 2 + 1 2 4 Rev 1.1 2 5 1 2 1 + 2 C AA C 3 3 + 1 2 1 2 2 1 + 2 + 1 2 + 1 2 + 1 2 + 1 2 1 2 + 1 + + + 2 + + A B C D A B C D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RXD4\ TXD4\ RTS4\ DCD4\ CTS4\ RI4\ DTR4\ DSR4\ RXD3\ TXD3\ RTS3\ DCD3\ CTS3\ RI3\ DTR3\ DSR3\ 5 RXD4\ TXD4\ RTS4\ DCD4\ CTS4\ RI4\ DTR4\ DSR4\ RXD3\ TXD3\ RTS3\ DCD3\ CTS3\ RI3\ DTR3\ DSR3\ PRINT1/COM3/COM4 5 104 104 C139 104 C138 104 VCC CTS4\ TXD4\ DTR4\ RI4\ DCD4\ RTS4\ DSR4\ RXD4\ VCC C126 VCC C125 VCC CTS3\ TXD3\ DTR3\ RI3\ DCD3\ RTS3\ DSR3\ RXD3\ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ MAX213 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- U13 T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ RS232 MAX213 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- U12 RS232 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 4 104 C140 RI4 DTR4 CTS4 TXD4 RTS4 104 C127 RI3 DTR3 CTS3 TXD3 RTS3 4 DCD3 DSR3 DCD4 DSR4 RXD4 104 C141 VCC 104 C128 VCC RXD3 RTS4 RI4 DCD4 TXD4 RTS3 RI3 DCD3 TXD3 2 4 6 8 10 2 4 6 8 10 HEADER 5X2/BOX 1 3 5 7 9 J16 COM4 HEADER 5X2/BOX 1 3 5 7 9 J14 COM3 3 3 RXD4 DTR4 DSR4 CTS4 RXD3 DTR3 DSR3 CTS3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PERROR- PPD1 PPD0 PAFDPSTBPSLCT PPE PBUSY PACK- PPD4 PPD5 PPD6 PPD7 PSLINPPD3 PPD2 PINIT22x4 RN23 R63 2 RN25 7 5 3 1 7 5 3 1 RN27 22x4 2 4 6 8 8 6 4 2 RN21 1 3 5 7 7 5 3 1 2 22 22x4 8 6 4 2 8 6 4 2 22x4 ERR- PD1 PD0 AFDSTBSLCT PE BUSY ACK- PD4 PD5 PD6 PD7 SLINPD3 PD2 INIT- RN22 1 3 5 7 7 5 3 1 1Kx4 2 4 6 8 8 6 4 2 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 DB25A J15 28 27 26 GGND Monday, January 29, 2007 Date: Vortex86SX PRN1/COM3/4 Document Number Vortex86SX SOC Reference Design Size Title DMP ELECTRONICS INC. PD3 SLINPD2 INITPD1 ERRPD0 AFDSTB- PD4 PD5 PD6 PD7 ACK- BUSY PE SLCT 1 Sheet 7 PRINT1 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF of VCC 8 1N4148 D5 RN28 1Kx4 R64 1K RN26 1Kx4 7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2 C129 C130 C131 C132 C133 C134 C135 C136 C137 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF C117 C118 C119 C120 C121 C122 C123 C124 RN24 1Kx4 1 Rev 1.1 A B C D A B C D C143 104 104 +12V C142 -5V 104 C144 -12V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 VCC SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE VCC OSC RSTDRV VCC IRQ9 -5V DRQ2 -12V OWS +12V 4.7K 2 4 6 8 2 4 6 8 4.7K MASTER MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 RN29 1 3 5 7 1 3 5 7 RN31 VCC 4.7K R65 OSC SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE OWS DRQ2 IRQ9 RSTDRV 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VCC HEADER 20X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J19 HEADER 32X2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 J18 4 IOCHRDY MEMCS16 IOCS16 SMEMW SMEMR IOW IOR SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 R70 R71 R73 RN30 1 3 5 7 330 330 330 2 2 2 2 2 2 2 2 2 SA[0..19] 2 2 SD[0..15] VCC VCC SD[0..15] MEMR MEMW 4.7K 2 4 6 8 SA[0..19] IOCHRDY AEN SD[0..15] IOCHCK SD[0..15] PC-104 / Full 16Bit ISA BUS 4 2 2 2 2 2 3 3 INT-A INT-B INT-C INT-D FRAMEIRDYTRDYDEVSELSTOPPAR 2 2 2 2 PCIRST- 2 PCICLK1 2 2 2 2 2 2 2 CBE-0 CBE-1 CBE-2 CBE-3 PGNT-0 PREQ-0 AD[0..31] 2 2 2 2 2 2 2 VCC3 VCC3 VCC3 INT-A INT-B INT-C INT-D FRAMEIRDYTRDYDEVSELSTOPPAR PCIRST- PCICLK1 CBE-0 CBE-1 CBE-2 CBE-3 PGNT-0 PREQ-0 AD[0..31] PCI BUS R72 R69 R68 4.7K 4.7K 4.7K VCC 4.7K SERR- PERR- PLOCK- R66 AD1 AD5 AD3 AD8 AD7 AD12 AD10 CBE-1 AD14 SERR- PLOCKPERR- DEVSEL- IRDY- AD17 CBE-2 AD21 AD19 CBE-3 AD23 AD27 AD25 AD31 AD29 PREQ-0 PCICLK1 INT-B INT-D 2 VCC3 -12V VCC 2 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 J17 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 +12V R67 VCC3 VCC Monday, January 29, 2007 Date: Vortex86SX PC104/PCI SLOT Document Number Vortex86SX SOC Reference Design Size Title 4.7K 1 Sheet AD2 AD0 AD6 AD4 CBE-0 AD9 AD13 AD11 PAR AD15 STOP- TRDY- FRAME- AD18 AD16 AD22 AD20 AD24 AD12 AD28 AD26 AD30 PGNT-0 8 VCC VCC3 PCIRST- INT-A INT-C DMP ELECTRONICS INC. C/BE0 +3.3V AD6 AD4 GND AD2 AD0 +5V REQ64 +5V +5V TRST +12V TMS TDI +5V INTA INTC +5V RESERVED3 +5V RESERVED4 GND GND 3.3V_AUX RST +5V GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V SDONE SBO GND PAR AD15 +3.3V AD13 AD11 GND AD9 PCI-5V_SLOT_120P AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64 +5V +5V -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 RESERVED1 PRSNT2 GND GND RESERVED2 GND CLK GND REQ +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 GND PCI SLOT 1 of 8 Rev 1.1 A B C D