ETC 24LCS21P

24LCS21
1K 2.5V Dual Mode I2C™ Serial EEPROM
FEATURES
The Microchip Technology Inc. 24LCS21 is a
128 x 8-bit dual-mode Electrically Erasable PROM.
This device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: Transmit Only Mode and bi-directional
Mode. Upon power-up, the device will be in the
Transmit Only Mode, sending a serial bit stream of the
entire memory array contents, clocked by the VCLK
pin. A valid high to low transition on the SCL pin will
cause the device to enter the bi-directional Mode, with
byte selectable read/write capability of the memory
array in standard I2C protocol.
The 24LCS21 also enables the user to write-protect the
entire memory contents using its write-protect pin. The
24LCS21 is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.
NC
1
8
VCC
NC
2
7
VCLK
WP
3
6
SCL
VSS
4
5
SDA
NC
1
8
VCC
NC
2
7
VCLK
WP
3
6
SCL
VSS
4
5
SDA
SOIC
24LCS21
DESCRIPTION
PDIP
24LCS21
• Completely implements DDC1/DDC2
interface for monitor identification
• Hardware write-protect pin
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C compatible
(SCL)
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
(SCL)
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial
0°C to +70°C
(C):
- Industrial (I)
-40°C to +85°C
PACKAGE TYPES
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA SCL
YDEC
VCLK
SENSE AMP
R/W CONTROL
VCC
VSS
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
DS21127D-page 1
24LCS21
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
TABLE 1-1:
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied.................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins ..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
PIN FUNCTION TABLE
Name
Function
WP
VSS
SDA
SCL
VCLK
VCC
NC
Write Protect (active low)
Ground
Serial Address/Data I/O
Serial Clock (Bi-directional Mode)
Serial Clock (Transmit-Only Mode)
+2.5V to 5.5V Power Supply
No Connection
DC CHARACTERISTICS
VCC = +2.5V to 5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I):
Tamb = -40°C to +85°C
Parameter
SCL and SDA pins:
High level input voltage
Low level input voltage
Input levels on VCLK pin:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs
Low level output voltage
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Symbol
Min
VIH
VIL
0.7 VCC
VIH
VIL
VHYS
VOL1
VOL2
ILI
ILO
CINT
2.0
ICC Write
ICC Read
ICCS
.05 VCC
-10
-10
—
—
—
Max
Units
0.3 VCC
V
V
0.8
0.2 VCC
—
0.4
0.6
10
10
10
V
V
V
V
V
µA
µA
pF
3
1
30
100
mA
mA
µA
µA
Conditions
VCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
(Note)
IOL = 3 mA, VCC = 2.5V (Note 1)
IOL = 6 mA, VCC = 2.5V
VIN = 0.1V to VCC
VOUT = 0.1V to VCC
VCC = 5.0V (Note1),
Tamb = 25°C, FCLK = 1 MHz
VCC = 5.5V, SCL = 400 kHz
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note: This parameter is periodically sampled and not 100% tested.
DS21127D-page 2
This Material Copyrighted by Its Respective Manufacturer
 1999 Microchip Technology Inc.
24LCS21
TABLE 1-3:
AC CHARACTERISTICS
Vcc= 2.5-5.5V
Parameter
Vcc= 4.5 - 5.5V
Symbol
Units
Min
Max
Min
Max
Remarks
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
FCLK
THIGH
TLOW
TR
TF
THD:STA
0
4000
4700
—
—
4000
100
—
—
1000
300
—
0
600
1300
—
—
600
400
—
—
300
300
—
kHz
ns
ns
ns
ns
ns
START condition setup time
TSU:STA
4700
—
600
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
0
250
4000
—
4700
—
—
—
3500
—
0
100
600
—
1300
—
—
—
900
—
ns
ns
ns
ns
ns
Output fall time from VIH
minimum to VIL maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
TOF
—
250
250
ns
TSP
—
100
20 + 0.1
CB
—
(Note 2)
Time the bus must be free
before a new transmission can
start
(Note 1), CB ≤ 100 pF
50
ns
(Note 3)
TWR
—
10
—
10
ms
Byte or Page mode
TVAA
TVHIGH
TVLOW
TVHST
TSPVL
TVHZ
TVPU
TSPV
—
4000
4700
0
4000
—
0
—
2000
—
—
—
—
500
—
100
—
600
1300
0
600
—
0
—
1000
—
—
—
—
500
—
100
ns
ns
ns
ns
ns
ns
ns
ns
—
1M
—
1M
—
cycles
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
VCLK setup time
VCLK hold time
Mode transition time
Transmit-Only power up time
Input filter spike suppression
(VCLK pin)
Endurance
25°C, VCC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
DS21127D-page 3
24LCS21
2.0
FUNCTIONAL DESCRIPTION
The 24LCS21 operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate two wire protocol to support each mode,
each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the VCLK pin. The device will remain in
this mode until a valid high to low transition is placed on
the SCL input. When a valid transition on SCL is recognized, the device will switch into the bi-directional
Mode. The only way to switch the device back to the
Transmit-Only Mode is to remove power from the
device.
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional two
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the
Transmit-Only Mode (see Initialization Procedure,
below). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth, null
bit (Figure 2-1). The clock source for the Transmit-Only
Mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each
byte are transmitted most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal address pointers will wrap around to the
first memory location (00H) and continue. The bi-directional Mode Clock (SCL) pin must be held high for the
device to remain in the Transmit-Only Mode.
2.2
Initialization Procedure
After VCC has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK
pin must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
00h. (Figure 2-2).
FIGURE 2-1: TRANSMIT ONLY MODE
SCL
TVAA
TVAA
SDA
Null Bit
Bit 1 (LSB)
Bit 1 (MSB)
Bit 7
VCLK
TVHIGH
TVLOW
FIGURE 2-2: DEVICE INITIALIZATION
Vcc
SCL
SDA
TVAA
High Impedance for 9 clock cycles
TVAA
Bit 8
Bit 7
TVPU
VCLK
1
DS21127D-page 4
This Material Copyrighted by Its Respective Manufacturer
2
8
9
10
11
 1999 Microchip Technology Inc.
24LCS21
3.0
BI-DIRECTIONAL MODE
3.1 Bi-directional Mode Bus Characteristics
The 24LCS21 can be switched into the bi-directional
Mode (Figure 3-1) by applying a valid high to low
transition on the bi-directional Mode Clock (SCL).
When the device has been switched into the bi-directional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire
bi-directional data transmission protocol (I2C). In this
protocol, a device that sends data on the bus is defined
to be the transmitter, and a device that receives data
from the bus is defined to be the receiver. The bus must
be controlled by a master device that generates the
bi-directional Mode Clock (SCL), controls access to the
bus and generates the START and STOP conditions,
while the 24LCS21 acts as the slave. Both master and
slave can operate as transmitter or receiver, but the
master device determines which mode is activated.
In this mode, the 24LCS21 only responds to
commands for device 1010 000X.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-2).
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: MODE TRANSITION
Transmit Only Mode
Bi-directional Mode
SCL
TVHZ
SDA
VCLK
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(D)
(C)
(A)
SCL
SDA
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21127D-page 5
24LCS21
3.1.4
3.1.5
DATA VALID (D)
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Note:
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
Note:
ACKNOWLEDGE
The 24LCS21 does not generate any
acknowledge
bits
if
an
internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Once switched into bi-directional Mode,
the 24LCS21 will remain in that mode until
power goes away. Removing power is the
only way to reset the 24LCS21 into the
Transmit-only mode.
FIGURE 3-3: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
START
STOP
FIGURE 3-4: BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
THD:STA
SDA
IN
TSP
TSU:STO
TBUF
TAA
TAA
SDA
OUT
DS21127D-page 6
This Material Copyrighted by Its Respective Manufacturer
 1999 Microchip Technology Inc.
24LCS21
3.1.6
SLAVE ADDRESS
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21.
The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
Slave Address
R/W
Read
1010000
1
Write
1010000
0
FIGURE 3-5: CONTROL BYTE ALLOCATION
START
1
0
1
0
0
R/W
0
4.1
Byte Write
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
READ/WRITE
SLAVE ADDRESS
WRITE OPERATION
Following the start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LCS21. After receiving another acknowledge signal from the 24LCS21 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS21
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and during this time the 24LCS21 will not generate acknowledge signals (Figure 4-1).
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21
(Figure 3-5).
Operation
4.0
A
0
FIGURE 4-1: BYTE WRITE
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
WORD
ADDRESS
CONTROL
BYTE
S
T
O
P
DATA
S
P
A
C
K
A
C
K
BUS ACTIVITY:
A
C
K
VCLK
FIGURE 4-2: VCLK WRITE ENABLE TIMING
SCL
THD:STA
SDA
IN
TSU:STO
VCLK
TVHST
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
TSPVL
DS21127D-page 7
24LCS21
4.2
5.0
Page Write
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a start condition followed by the control byte for
a write command (R/W = 0). If the device is still busy
with the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.
The write control byte, word address and the first data
byte are transmitted to the 24LCS21 in the same way
as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LCS21 which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 5-2).
FIGURE 5-1: ACKNOWLEDGE POLLING FLOW
Send
Write Command
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
Note:
ACKNOWLEDGE POLLING
Send Stop
Condition to
Initiate Write Cycle
Page write operations are limited to writing
bytes within a single physical page, regardless of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or Ôpage sizeÕ) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore necessary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
FIGURE 5-2: PAGE WRITE
S
T
BUS
A
ACTIVITY: R
MASTER T
WORD
ADDRESS
CONTROL
BYTE
S
T
O
P
DATA n + 7
DATA n + 1
DATA (n)
P
SDA LINE S
BUS
ACTIVITY:
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
VCLK
DS21127D-page 8
This Material Copyrighted by Its Respective Manufacturer
 1999 Microchip Technology Inc.
24LCS21
6.0
WRITE PROTECTION
7.1
When using the 24LCS21 in the bi-directional Mode,
the VCLK pin operates as the write protect control pin.
Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LCS21 to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only Mode.
Additionally, Pin 3 performs a flexible write protect
function. The 24LCS21 contains a write-protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in DDC applications) sets the fuse which
enables the WP pin. Until this fuse is set, the 24LCS21
is always write enabled (if VCLK = 1). After the fuse is
set, the write capability of the 24LCS21 is determined
by WP (Figure 6-1).
The 24LCS21 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LCS21
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LCS21
discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
FIGURE 6-1: WRITE PROTECT TRUTH
TABLE
S
T
A
R
T
CONTROL
BYTE
WP
Add. 7Fh
Written
Mode
0
1
1
1
X
X
1/open
0
X
No
Yes
Yes
Read Only
R/W
R/W
Read Only
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.2
S
T
O
P
DATA n
S10100001
P
N
O
A
C
K
A
C
K
BUS ACTIVITY
VCLK
7.0
Current Address Read
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS21 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LCS21 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LCS21
discontinues transmission (Figure 7-2).
FIGURE 7-2: RANDOM READ
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S
T
A
R
T
WORD
ADDRESS
S 1 0 1 0 0 0 0 0
BUS ACTIVITY
CONTROL
BYTE
S
T
O
P
DATA n
S 1 0 1 0 0 0 0 1
A
C
K
A
C
K
P
A
C
K
N
O
A
C
K
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
DS21127D-page 9
24LCS21
7.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LCS21 transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LCS21 to transmit the next sequentially
addressed 8-bit word (Figure 8-1).
PIN DESCRIPTIONS
8.1
SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the bi-directional Mode. In the Transmit-Only Mode, which only
allows data to be read from the device, data is also
transferred on the SDA pin. This pin is an open drain
terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10 KΩ for 100 kHz, 2 KΩ for
400 kHz).
To provide sequential reads the 24LCS21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4
8.0
For normal data transfer in the bi-directional Mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for indicating
the START and STOP conditions.
Noise Protection
The 24LCS21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
8.2
SCL
This pin is the clock input for the bi-directional Mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit Only Mode to the bi-directional Mode. It must remain high for the chip to continue
operation in the Transmit Only Mode.
The SDA, SCL and VCLK inputs have Schmitt trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
8.3
VCLK
This pin is the clock input for the Transmit Only Mode
(DDC1). In the Transmit Only Mode, each bit is clocked
out on the rising edge of this signal. In the bi-directional
Mode, a high logic level is required on this pin to enable
write capability.
8.4
WP
This pin is used for flexible write protection of the
24LCS21. When the last memory location (7Fh) is
written with any data, this pin is enabled and
determines the write capability of the 24LCS21
(Figure 6-1).
The WP pin has an internal pull up resistor which will
allow write capability (assuming VCLK = 1) at all times
if this pin is floated.
FIGURE 8-1: SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n+2
DATA n+1
S
T
O
P
DATA n+X
P
SDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS21127D-page 10
This Material Copyrighted by Its Respective Manufacturer
 1999 Microchip Technology Inc.
24LCS21
24LCS21 Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
24LCS21
–
/P
Package:
Temperature
Range:
Device:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Blank = 0˚C to +70˚C
I = -40˚C to +85˚C
24LCS21
24LCS21T
Dual Mode I2C Serial EEPROM
Dual Mode I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended
workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer
DS21127D-page 11
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
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ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
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Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
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logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
 1999 Microchip Technology Inc.
This Material Copyrighted by Its Respective Manufacturer