AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM Features (Preliminary) General Description - Single supply with operation down to 2.5V - Completely implements DDC1/DDC2 interface for monitor identification, including recovery to DDC1 - Low power CMOS technology - 1 mA typical active current - 10 uA standby current typical at 5.5V - 2-wire serial interface bus, I2C compatible - 100Khz (2.5V) and 400Khz (5V) compatibility - Self-timed write cycle (including auto-erase) - Hardware write-protect pin - Page-write buffer for up to eight bytes - 1,000,000 erase/write cycles - Data retention > 40 years - 8-pin PDIP and SOP packages - Available for extended temperature ranges Commercial (C): 0°C to +70°C Industrial (I): -40°C to +85°C The AM24LC21 is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: transmit only mode and bi-directional mode. Upon power-up, the device will be in the transmit only mode, sending a serial bit stream of the memory array contents, clocked by the VCLK pin. A valid high to low transition on the SCL pin will cause the device to enter the bi-directional mode, with byte selectable read/write capability of the memory array. The AM24LC21 is available in a standard 8-pin PDIP and SOP package in both commercial and industrial temperature ranges. Pin Assignments Pin Descriptions (Top View) (Top View) NC 1 8 VCC NC 2 7 VCLK WP 3 6 SCL 4 5 SDA NC 1 8 VCC NC 2 7 VCLK WP 3 6 SCL VSS 4 5 SDA VSS PDIP Package Name NC VSS SDA VCLK VCC SCL SOP Package WP Description No connection Ground Serial address/data I/O Serial clock (transmit only mode) Power supply Serial clock (bi-directional mode) Write protect (active low) Note. See pin description (continued) for more detailed Ordering Information AM24LC 21 X X X Operating Voltage LC : 2.5V~5.5V,CMOS Temp. grade Package Packing Blank : 0o C ~ +70 o C S : SOP-8L N : PDIP-8L Blank : Tube A : Taping Type 1K Dual Mode I o o : −40 C ~ +85 C This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 0.0 Aug 10, 2002 1/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Block Diagram SDA SCL I/O control logic HV generator VCLK XDec WP Memory control logic EEPROM Array Page latches VCC YDec VSS Sense AMP R/W* control Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 2/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Absolute Maximum Ratings (Note) Symbol Parameter Rating VCC Voltage with respect to ground VSS All inputs and outputs w.r.t. TOP Operating temperature TSTG Storage temperature Unit 7 V -0.6V to Vcc+1 0 to + 70 (commercial) -40 to +85 (industrial) -65 to +125 V DC Electrical Characteristics ( Vcc=2.5V to 5.5V, T °C °C =0oC ~ +70oC, TAI= -40oC ~ +85oC) AC Symbol VOL1 Parameter SCL and SDA pins: High level input voltage SCL and SDA pins: Low level input voltage VCLK pin input level: High level input voltage VCLK pin input levels: Low level input voltage Hysteresis of Schmitt inputs Low level output voltage VOL2 Low level output voltage VIH VIL VIH VIL VHYS trigger Conditions Min. Max. Unit − 0.7Vcc − V − − 0.3Vcc V VCC ≥2.7V (Note) 2 − V VCC <2.7V (Note) − 0.2Vcc V 0.05Vcc − V IOL=3mA, VCC=2.5V (Note) − 0.4 V IOL=6mA, VCC=2.5V − 0.6 V (Note) ILI Input leakage current VIN = 0.1V to VCC -10 10 uA ILO Output leakage current VOUT = 0.1V to VCC -10 10 uA ICC(Write) Operating current VCC = 5.5V, SCL=400Khz − 3 mA ICC(Read) Operating current VCC = 5.5V, SCL=400Khz VCC = 3V, SDA=SCL= VCC VCC = 5.5V, SDA=SCL= VCC, VCLK=VSS − 1 mA − − 30 100 uA ICCS standby current Note : This parameter is periodically sampled and not 100% tested Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 3/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) AC Electrical Characteristics Symbol FCLK TH TL Parameter TAA Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock TBUF Bus free time TR TF THD(ST) TSU(ST) THD(DI) TSU(DI) TSU(STP) TOF TSP TWR TVAA TVH TVL TVHZ TVPU − Output fall time from VIH(min) to VIL(max) Input filter spike suppression (SDA and SCL pins) Write cycle time Vcc=4.5V~5.5V Fast mode Min Max 400 − 0.6 − 1.3 − Standard Mode Unit Remarks Khz us us − − − 0.3 us (Note1) − 0.3 us (Note1) − 0.6 − us 4.7 − 0.6 − us 0 − 0 − us After this period the first clock pulse is generated Only relevant for repeated start condition (Note 2) 0.25 − 0.1 − us − 4 − 0.6 − us − − 3.5 − 0.9 us (Note 2) 4.7 − 1.3 − us Time the bus must be free before a new transmission can start − 0.25 20+0.1CB 0.25 us (Note 1), CB≤100pF − 0.05 − 0.05 us (Note 3) − 10 − 10 ms Min − 4 4.7 Max 100 − − − 1 − − 0.3 4 Byte or page mode Output valid from VCLK VCLK high time VCLK low time Mode transition time Transmit only power up time − 2 − 1 − 4 4.7 − − − 0.5 0.6 1.3 − − − 0.5 − − − 0 − 0 − Endurance 1M − 1M − − 0 cycles 25 C, VCC=5V, Block mode (Note 4) Note 1. Not 100% tested. CB=total capacitance of one bus line in pF. Note 2. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unitended generation of start or stop conditions Note 3. The combined TSP and Vhys specifications are due to new schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Tl specification for standard operation. Note 4. This parameter is not tested but ensured by characterization. Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 4/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Functional description below). In this mode, data is transmitted on the SDA pin in 8 bit bytes, each followed by a ninth, null bit (see Figure 2-1). The clock source for the transmit-only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted most significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The bi-directional mode clock (SCL) pin must be held high for the device to remain in the transmit-only mode. 1.0 Overview The AM24LC21 operates in two modes, the transmit-only mode and the bi-directional mode. There is a separate two wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high to low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the bi-directional mode. The only way to switch the device back to the transmit-only mode is to remove power from the device. 2.2 Initialization procedure After VCC has stabilized, the device will be in the transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. The device will power up at an indeterminate byte address. (Figure 2-2). 2.1 Transmit-only mode The device will power up in the transmit-only mode. This mode supports a unidirectional two wire protocol for trans-mission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the transmit-only mode (see Initialization Procedure, SCL TVAA TVAA SDA NULL BIT BIT1(LSB) BIT8(MSB) BIT7 VCLK TVLOW TVHIGH Figure 2-1. Transmit only mode VCC TVAA SCL SDA HIGH IMPEDANCE FOR 9 CLOCK CYCLES TVAA BIT8 BIT7 TVPU VCLK 1 2 8 9 10 11 Figure 2-2. Device initialization Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 5/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM 3.0 Bi-directional mode The AM24LC21 can be switched into the bi-directional mode (see Figure 3-1) by applying a valid high to low transition on the bi-directional mode clock (SCL). When the device has been switched into the bi-directional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two wire bi-directional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be con-trolled by a master device that generates the bi-directional mode clock (SCL), controls access to the bus and generates the START and STOP conditions, while the AM24LC21 acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Any high to low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-Only Mode, and transmit its contents starting with the most significant bit in address 00h.(see Figure 3-1, 3-2) MODE Transmit Only (Preliminary) 3.1 Bi-directional mode bus characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (see Figure 3-3). 3.1.1 Bus not busy (A) Both data and clock lines remain HIGH. 3.1.2 Start data transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.1.3 STOP data transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. Bi-directional Recovery to Transmit-Only Mode TVHZ SCL (MSB of data in 00h) Bit8 SDA VCLK count = 1 2 3 4 127 128 VCLK Figure 3-1. Mode transition MODE Transmit Only Mode Bi-directional permanently Transition Mode with possibility to return to Transmit-Only Mode SCL S SDA VCLK count = 1 2 n 1 0 1 0 0 0 0 0 ACK 0 VCLK n < 128 Figure 3-2. Successful Mode transition This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 0.0 Aug 10, 2002 6/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (A) (B) (Preliminary) (D) (D) (C) (A) SCL SDA START Condition Data allowed to change Address or acknowledge valid STOP condition Figure 3-3. Data transfer sequence on the serial bus extra clock pulse which is associated with this acknowledge bit. 3.1.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. Note: The AM24LC21 does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 3.1.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an VHYS SCL TSU:STO THD:STA TSU:STA SDA START STOP Figure 3-4. Bus timing start/stop Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 7/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM TF (Preliminary) TR THIGH TLOW SCL TSU:STA THD:DAT THD:STA SDA IN TSU:DAT TSU:STO TSP TAA TAA THD:STA TBUF SDA OUT Figure 3-5. Bus timing data Following the start signal from the master, the slave address (4 bits), 000 (3 bits) and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will fol-low after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmit-ted by the master is the word address and will be written into the address pointer of the AM24LC21. After receiving another acknowledge signal from the AM24LC21 the master device will transmit the data word to be writ-ten into the addressed memory location. The AM24LC21 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the AM24LC21 will not generate acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. 3.1.6 Slave address After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (1010) for the AM24LC21, followed by three 000 3 bits. The eighth bit of slave address determines if the master device wants to read or write to the AM24LC21 (Figure 3-6). The AM24LC21 monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. Operation Read Write Control code Chip select 1010 000 1010 000 START R/W 1 0 READ/WRITE R/W A Slave address 1 0 1 0 0 0 0 4.1 Byte Write Figure 3-6. Control byte allocation If the 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the AM24LC21 in the same way as in a byte write. But instead of generating a stop condition the master transmits up to eight data bytes to the AM24LC21 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 4-2). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 8/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write Bus activity Master S T A R T (Preliminary) Control Byte Word Address S T O P Data S P SDA Line A C K A C K Bus activity A C K VCLK Figure 4-1. Byte write Bus activity Master S T A R T Control Byte Word Address S T O P Data(n+7) Data(n+1) Data(n) P S SDA Line Bus activity A C K A C K A C K A C K A C K VCLK Figure 4-2. Page write 5.0 Acknowledge polling Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for the flow diagram. 6.0 Write protection When using the AM24LC21 in the bi-directional Mode, the VCLK pin operates as the write protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the AM24LC21 to operate as a serial ROM, although this configuration would prevent using the device in the transmit-only mode. Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 9/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the AM24LC21 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a ‘1’. The AM24LC21 will then issue an acknowledge and transmits the eight bit data word.The master will not acknowledge the transfer but does generate a stop condition and the AM24LC21 discontinues transmission (Figure 7-2). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Die Device Acknowledg (ACK = 0)? (Preliminary) No YES Next Operation Figure 5-1: Acknowledge polling flow 7.0 Read operation Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 7.1 Current address read The AM24LC21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the AM24LC21 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the AM24LC21 discontinues transmission (Figure 7-1). Bus activity Master S T A R T 7.3 Sequential Read Sequential reads are initiated in the same way as a ran-dom read except that after the AM24LC21 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the AM24LC21 to transmit the next sequentially addressed 8-bit word (see Figure 7-3). To provide sequential reads the AM24LC21 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise protection The AM24LC21 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. Control Byte S T O P Data(n) S P SDA Line Bus activity A C K N O A C K Figure 7-1. Current address read This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 0.0 Aug 10, 2002 10/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM S T A R T Bus activity Master Control Byte S T A R T Word address S Control Byte (Preliminary) S T O P Data(n) S P SDA Line A C K A C K Bus activity A C K N O A C K Figure 7-2. Random read Bus activity Master Contro Byte Data(n) Data(n+1) S T O P Data(n+X) Data(n+2) P SDA Line Bus activity A C K A C K A C K A C K N O A C K Figure 7-3. Sequential read Pin Descriptions (Continued) SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the bi-directional mode. In the transmit-only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10k for 100 Khz, 1k for 400 Khz). For normal data transfer in the bi-directional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. VCLK This pin is the clock input for the transmit only mode. In the transmit only mode, each bit is clocked out on the rising edge of this signal. In the bi-directional mode, a high logic level is required on this pin to enable write capability. WP When using the AM24LC21 in the bi-directional Mode, the VCLK pin operates as the write protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the AM24LC21 to operate as a serial ROM, although this configuration would prevent using the device in the transmit-only mode. If WP is connected to GND, PROGRAM operation onto the whole memory will not be executed. READ operation are possible. If WP is connected to Vcc, normal memory operation is enabled, SCL This pin is the clock input for the bi-directional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the transmit only mode to the bi-directional mode. It must remain high for the chip to continue operation in the transmit only mode. READ/ WRITE over the entire memory is possible. Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 11/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Package Information (1) Package Type: PDIP-8L D E1 E-PIN O0.118 NOTE 9 PIN #1 INDENT O0.025 DEEP 0.006-0.008 E 7 (4X) A1 L A A2 15 (4X) B S Symbol A A1 A2 B B1 B2 C D E E1 e L eB S e B1 B2 C eB Dimensions In Millimeters Min. Nom. Max. － － 5.33 － － 0.38 3.25 3.30 3.45 0.36 0.46 0.56 1.14 1.27 1.52 0.18 0.99 1.17 0.20 0.25 0.33 9.12 9.30 9.53 － 7.62 8.26 6.20 6.35 6.60 － － 2.54 － － 3.18 － 8.38 9.40 0.71 0.84 0.97 Anachip Corp. www.anachip.com.tw Dimensions In Inches Min. Nom. Max. － － 0.210 － － 0.015 0.128 0.130 0.136 0.014 0.018 0.022 0.045 0.050 0.060 0.032 0.039 0.046 0.008 0.010 0.013 0.359 0.366 0.375 － 0.300 0.325 0.244 0.250 0.260 － － 0.100 － － 0.125 － 0.330 0.370 0.028 0.033 0.038 Rev 0.0 Aug 10, 2002 12/13 AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) E H (2) Package Type: SOP-8L L VIEW "A" D 0.015x45 7 (4X) C A A2 7 (4X) e VIEW "A" A1 B y Symbol A A1 A2 Dimensions In Millimeters Min. Nom. Max. 1.47 1.60 1.73 － 0.10 0.25 1.45 － Dimensions In Inches Min. Nom. Max. 0.058 0.063 0.068 － 0.004 0.010 － － 0.057 － B 0.33 0.41 0.51 0.013 0.016 0.020 C 0.19 0.20 0.25 0.0075 0.008 0.0098 D 4.80 4.85 4.95 0.189 0.191 0.195 E 3.91 1.27 3.99 － 0.150 － 0.154 e 3.81 － 0.050 0.157 － H 5.79 5.99 6.20 0.228 0.236 0.244 L 0.38 － 0.71 － 1.27 0.015 － 0.028 － 0.050 0.10 0 － 8 0 － 8O y θ O O O 0.004 Marking Information 8 Logo 7 6 5 AC 24LC21X YYWWX Part Number & grade X=Blank (00 C to + 700 C) X=I (−40 0 C to + 85 0 C) 1 2 3 Date Code YY: Year WW: Nth week X: Internal code 4 PDIP/SOP/ Package Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 13/13