74ACT16374 16-BIT D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 120MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT16374 is an advanced high-speed CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. This 16 bit D-Type Flip-Flop is controlled by two clock inputs (CK) and two output enable inputs (OE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. April 2001 TSSOP ORDER CODES PACKAGE TSSOP TUBE T &R 74ACT16374TTR PIN CONNECTION 1/9 74ACT16374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 1OE 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 1Q0 to 1Q7 2Q0 to 2Q7 2OE *IEC LOGIC SYMBOLS NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs 3-State Outputs 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 V CC Positive Supply Voltage TRUTH TABLE INPUTS OE CK D H X Q X Z L X NO CHANGE* L L L L H H X : Don‘t Care Z : High Impedance 2/9 OUTPUT 74ACT16374 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. 3/9 74ACT16374 RECOMMENDED OPERATING CONDITIONS Symbol Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage Top Operating Temperature V CC dt/dv Parameter Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 0 to VCC V -55 to 125 °C 8 ns/V 1) VIN from 0.8V to 2.0V DC SPECIFICATIONS Test Condition Symbol Parameter 4.5 V IL Low Level Input Voltage 4.5 VOH High Level Output Voltage VOL II I OZ ICCT Low Level Output Voltage Input Leakage Current High Impedance Output Leakege Current Max ICC/Input TA = 25°C VCC (V) High Level Input Voltage VIH 5.5 VO = 0.1 V or VCC-0.1V 5.5 VO = 0.1 V or VCC-0.1V 4.5 IO=-50 µA Max. -55 to 125°C Min. Min. Typ. 2.0 1.5 2.0 2.0 1.5 2.0 1.5 0.8 1.5 0.8 4.49 5.5 IO=-50 µA 5.4 5.49 4.5 IO =-24 mA 3.86 4.86 Max. Unit Max. 2.0 2.0 0.8 V 0.8 0.8 0.8 4.4 4.4 5.4 5.4 3.76 3.7 V 5.5 IO =-24 mA 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 4.5 IO =24 mA 0.36 0.44 0.5 5.5 IO =24 mA 0.36 0.44 0.5 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 5.5 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 1.5 1.6 mA 80 80 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA 5.5 VI = VCC - 2.1V Quiescent Supply Current 5.5 VI = VCC or GND IOLD Dynamic Output Current (note 1, 2) 5.5 4.76 0.6 8 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω 4/9 -40 to 85°C Min. 4.4 ICC IOHD Value 4.7 V 74ACT16374 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ tW ts th fMAX Parameter TA = 25°C VCC (V) Propagation Delay Time CK to Q 5.0 (*) Output Enable Time 5.0 (*) Output Disable Time 5.0 (*) CLOCK Pulse Width HIGH or LOW Setup Time D to CK, HIGH or LOW Hold Time D to CK, HIGH or LOW 5.0 (*) Maximum Clock Frequency Value Min. -40 to 85°C -55 to 125°C Min. Min. Typ. Max. Max. 4.3 6.3 12.4 13.2 4.5 6.7 12.2 13.1 5.7 8.5 13.4 14.3 4.8 7.2 11.9 12.7 5.5 8.0 9.8 10.2 4.7 6.7 10.4 10.9 Unit Max. ns ns ns 2.5 1.9 2.9 2.9 ns 5.0 (*) 1.6 <1.0 1.8 1.8 ns 5.0 (*) 0.3 -0.8 1.0 1.0 ns 5.0 (*) 100 120 60 60 MHz (*) Voltage range is 5.0V ± 0.5V CAPACITIVE CHARACTERISTICS Test Condition Symbol CIN C OUT C PD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Value TA = 25°C VCC (V) Min. Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 5.0 3.6 pF 5.0 11 pF 25 pF 5.0 fIN = 10MHz 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) 5/9 74ACT16374 TEST CIRCUIT Test Switch tPLH, tPHL Open tPZL, tPLZ 2VCC tPZH, tPHZ GND C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/9 74ACT16374 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: CLOCK PULSE WIDTHS (f=1MHz; 50% duty cycle) 7/9 74ACT16374 TSSOP48 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. 1.1 MAX. 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 12.4 12.5 12.6 0.408 0.492 0.496 E 7.95 8.1 8.25 0.313 0.319 0.325 E1 6.0 6.1 6.2 0.236 0.240 0.244 e 0.5 BSC 0.0197 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 8/9 TYP. 74ACT16374 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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