ETC AS5SS256K36ADQ

SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
256K x 36 SSRAM
PIN ASSIGNMENT
(Top View)
Synchronous Burst SRAM
FEATURES
l
l
l
l
l
l
l
l
l
l
l
OPTIONS
MARKING
l
-8.5
-10
DQPb
DQb
DQb
V DDQ
Vss
DQb
DQb
DQb
DQb
Vss
V DDQ
DQb
DQb
Vss
NC
V DD
ZZ
DQa
DQa
V DDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
100-pin TQFP (DQ)
(3-chip enable version, no indicator)
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
VDD
CE2\
BWa\
BWb\
BWc\
BWd\
CE2
CE\
SA
SA
A
no indicator
GENERAL DESCRIPTION
The AS5SS256K36 employs high-speed, low-power CMOS
designs that are fabricated using an advanced CMOS process.
This 8Mb Synchronous Burst SRAM integrates a 256K x
36 SRAM core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, active LOW chip enable (CE\), two additional chip
enables for easy depth expansion (CE2\, CE2), burst control
inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and
global write (GW\). Note that CE2\ is not available on the A
version.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
SA
SA
SA
SA
SA
SA
SA
SA
NF
VDD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
For more products and information
please visit our web site at
www.austinsemiconductor.com
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18
19
20
21
22
23
24
25
26
27
28
29
30
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DQPc
DQc
DQc
VDD Q
Vss
DQc
DQc
DQc
DQc
Vss
VDD Q
DQc
DQc
Vss
V DD
NC
Vss
DQd
DQd
VDD Q
Vss
DQd
DQd
DQd
DQd
Vss
VDD Q
DQd
DQd
DQPd
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
XT
IT
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80
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78
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71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA
SA
SA
SA
SA
SA
SA
NF
NF
VDD
Vss
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
DQ No. 1001
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
1
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3
4
5
6
7
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22
23
24
25
26
27
28
29
30
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Timing
8.5ns/10ns/100MHz
10ns/15ns/66MHz
l Packages
100-pin TQFP (2-chip enable)
l Pinout
2-chip Enables
3-chip Enables
l Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
Vss
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
l
SA
SA
ADV\
ADSP\
ADSC\
OE\
BWE\
GW\
CLK
Vss
VDD
SA
BWa\
B W b\
BWc\
B W d\
CE2
CE\
SA
SA
l
100-pin TQFP (DQ)
(2-chip enable version, “A” indicator)
Organized 256K x 36
Fast Clock and OE\ access times
Single +3.3V +0.3V/-0.165V power supply (VDD)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL WRITE
Three chip enables for simple depth expansion and address
pipelining
Clock-controlled and registered addresses, data I/Os and
control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down for portable applications
100-lead TQFP package for high density, high speed
Low capacitive bus loading
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SSRAM
Austin Semiconductor, Inc.
AS5SS256K36 &
AS5SS256K36A
simplify WRITE cycles. This allows self-timed WRITE cycles.
Individual byte enables allow individual bytes to be written.
During WRITE cycles on the x18 device, BWa\ controls DQa’s
and DQPa; BWb\ controls DQb’s and DQPb; BWc\ controls
DQc’s and DQPc; BWd\ controls DQd’s and DQPd. GW\ LOW
causes all bytes to be written. Parity bits are also featured on
this device.
This 8Mb Synchronous Burst SRAM operates from a
+3.3V VDD power supply, and all inputs and outputs are TTLcompatible. The device is ideally suited for 486, Pentium©, 680x0
and PowerPCTM systems and those systems that benefit from a
wide synchronous data bus.
GENERAL DESCRIPTION (continued)
Asynchronous inputs include the output enable (OE\),
clock (CLK) and snooze enable (ZZ). There is also a burst
mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also
asynchronous. WRITE cycles can be from one to four bytes
wide as controlled by the write control inputs.
Burst operation can be initiated with either address
status processor (ADSP\) or address status controller (ADSC\)
inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\).
Address and write control are registered on-chip to
FUNCTIONAL BLOCK DIAGRAM
18
SA0, SA1, SAs
MODE
ADV\
CLK
18
ADDRESS
REGISTER
16
18
SA0-SA1
Q1
BINARY
COUNTER
AND LOGIC
CL
SA1'
Q0
SA0'
ADSC\
ADSP\
BWd\
BYTE "d"
WRITE REGISTER
BYTE "d"
WRITE DRIVER
BWc\
BYTE "c"
WRITE REGISTER
BYTE "c"
WRITE DRIVER
BWb\
BYTE "b"
WRITE REGISTER
BYTE "b"
WRITE DRIVER
BWa\
BWE\
GW\
BYTE "a"
WRITE REGISTER
BYTE "a"
WRITE DRIVER
CE\
CE2
CE2\
OE\
256K x 9 x 4
(x36)
MEMORY
ARRAY
DQs
SENSE
AMPS
DQPa
OUTPUT
BUFFERS
DQPb
DQPc
DQPd
INPUT
REGISTERS
ENABLE
REGISTER
4
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and time diagrams for detailed
information.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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2
SSRAM
Austin Semiconductor, Inc.
AS5SS256K36 &
AS5SS256K36A
PIN DESCRIPTION
Pin Number
SYMBOL TYPE
DESCRIPTION
37
36
32-35, 44-50,
SA0
Synchronous Address Inputs: These inputs are registered and must
81, 82, 99,
SA1
Input meet the setup and hold times around the rising edge of CLK. Two
100
SA
different pinouts are available for the TQFP packages.
92 (A version)
43 (3 CE version)
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold times
BWa\
93
around the rising edge of CLK. A byte write enable is LOW for a WRITE
94
BWb\
Input cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa;
BWc\
95
Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc;
BWd\
96
Bwd\ controls DQd pins and DQPd. Parity bits are featured on this
device.
Byte Write Enable: This active LOW input permits BYTE WRITE
87
BWE\
Input operations and must meet the setup and hold items around the rising
edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
88
GW\
Input independent of the BWE\ and BWx\ lines and must meet the setup and
hold times around the rising edge of CLK.
Clock: CLK registers address, data, chip enable, byte write enables and
89
CLK
Input burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the
98
CE\
Input device and conditions the internal use of ADSP\. CE\ is sampled only
when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the
92
CE2\
Input device and is sampled only when a new external address is loaded.
(3 CE version)
CE2\ is only available on the 3 CE version.
97
CE2
86
OE\
83
ADV\
85
ADSC\
Input
Synchronous Chip Enable: This active HIGH input is used to enable the
device and is sampled only when a new external address is loaded.
Output Enable: This active LOW, asynchronous input enables the data
I/O output drivers.
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
Input
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV\ must be HIGH at the rising edge of
the first clock after an ADSP\ cycle is initiated.
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
Input registered. A READ or WRITE is performed using the new address if
CE\ is LOW. ADSC\ is also used to place the chip into power-down state
when CE\ is HIGH.
Input
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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3
SSRAM
Austin Semiconductor, Inc.
AS5SS256K36 &
AS5SS256K36A
PIN DESCRIPTION (continued)
Pin Number
SYMBOL TYPE
84
ASDP\
31
MODE
64
ZZ
(a) 52, 53, 56-59,
62, 63
(b) 68, 69, 72-75,
78, 79
(c) 2, 3, 6-9, 12,
13
(d) 18, 19, 22-25,
28, 29
51
80
1
30
DQa
DQb
DQc
DQd
DESCRIPTION
Synchronous Address Status Processor: This active LOW inputs
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address, independent of
Input
the byte write enables and ADSC\, but dependent upon CE\, CE2 and
CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if
CE2 is LOW or CE2\ is HIGH.
MODE: This inputs selects the burst sequence. A LOW on this pin
Input select "linear burst." NC or HIGH on this pin selects "interleaved burst."
Do not alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
Input
memory array is retained. When ZZ is active, all other inputs are
ignored.
SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is
Input/
DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold
Output
times around the rising edge of CLK.
NC/DQPa
NC/DQPb
Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte
NC/ I/O
NC/DQPc
"c" parity is DQPc; Byte "d" parity is DQPd.
NC/DQPd
Power Supply: See DC Electrical Characteristics and Operating
Supply
15, 41, 65, 91
VDD
Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and
4, 11, 20, 27, 54,
VDDQ
Supply
Operating Conditions for range.
51, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
Vss
Supply Ground: GND
71, 76, 90
Do Not Use: These signals may either be unconnected or wired to GND
38, 39
DNU
--to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
16, 66
NC
--connected to GND to improve package heat dissipation.
No Function: These pins are internally connected to the die and have
42
the capacitance of an input pin. It is allowable to leave these pins
NF
--43 (A version)
unconnected or driven by signals. On the 3 CE version, pin 42 is
reserved as an address upgrade pin for the 16Mb Synchronous Burst.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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4
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE All Bytes
WRITE All Bytes
GW\
H
H
H
H
L
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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BWE\
H
L
L
L
X
BWa\
X
H
L
L
X
BWb\
X
H
H
L
X
BWc\
X
H
H
L
X
BWd\
X
H
H
L
X
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
TRUTH TABLE
OPERATION
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
CE\ CE2\ CE2
USED
None
H
X
X
None
L
X
L
None
L
H
X
None
L
X
L
None
L
H
X
None
X
X
X
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
External
L
L
H
Next
X
X
X
Next
X
X
X
Next
H
X
X
Next
H
X
X
Next
X
X
X
Next
H
X
X
Current
X
X
X
Current
X
X
X
Current
H
X
X
Current
H
X
X
Current
X
X
X
Current
H
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP\ ADSC\
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV\
WRITE\
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE\ CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTE:
1. X means “Don’t Care.” \ means active LOW. H Means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\, BWc\, or BWd\) and BWE\ are LOW or
GW\ is LOW. WRITE\ = H for all BWx\, BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQa pins, DQPa. BWb\ enables WRITEs to DQb pins, DQPb. BWc\ enables WRITEs to DQc
pins, DQPc. BWd\ enables WRITEs to DQd pins, DQPd.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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6
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature (Plastics) ...........................-55°C to +150°C
Storage Temperature (Ceramics) .........................-55°C to +125°C
Short Circuit Output Current (per I/O)…............................100mA
Voltage on any Pin Relative to Vss........................-0.5V to +4.6 V
Max Junction Temperature**..............................................+150°C
VIN (DQx) .........................................................-0.5V to VDDQ +0.5V
VIN (inputs) ................................................... ....-0.5V to VDD +0.5V
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humidity.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(-55oC to +125oC or -40oC to +85oC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
PARAMETER
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
CONDITION
OV < VIN < Vcc
Output(s) disabled, OV < VOUT < Vcc
IOH = -4.0 mA
IOL = 8.0 mA
Isolated Output Buffer Supply
SYMBOL
VIH
VIL
ILI
ILO
VOH
VOL
VDD
VDDQ
MIN
2.2
-0.3
-2
-2
2.4
--3.135
3.135
MAX
VCC +0.3
0.8
2
2
-0.4
3.6
3.6
UNITS
V
V
µΑ
µΑ
V
V
V
V
NOTES
1, 2
1, 2
3
1, 4
1, 4
1
1, 5
THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
CONDITIONS
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
1-layer
SYM
TYP
UNITS NOTES
θJA
40
o
6
θJC
8
o
6
C/W
C/W
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH < +4.6V for t<tKC/2 for I < 20mA
Undershoot: VIL > -0.7V for t<tKC/2 for I < 20mA
Power-up: VIH < +3.6V and VDD < 3.135V for t < 200ms
3. MODE and ZZ pins have internal pull-up resistors, and input leakage = +10µA
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the stated DC values.
AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
6. This parameter is sampled.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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7
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(-55oC to +125oC or -40oC to +85oC)
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CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
CONDITIONS
SYM
CI
MAX
4
UNITS
pF
NOTES
4
TA = 25oC; f = 1MHz;
VDD = 3.3V
CO
5
pF
4
CA
3.5
pF
4
CCK
3.5
pF
4
Clock Capacitance
NOTES:
1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device
is active (not in power-down mode).
3. A typical value is measured at 3.3V, 25oC and 15ns cycle time.
4. This parameter is sampled.
AS5SS256K36 &
AS5SS256K36A
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SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (-55oC to +125oC or -40oC to +85oC)
DESCRIPTION
SYMBOL
-8.5
MIN
MAX
MIN
-10
MAX
UNITS
NOTES
CLOCK
Clock cycle time
tKC
Clock frequency
tKF
Clock HIGH time
tKH
3.0
4.0
ns
2
Clock LOW time
OUTPUT TIMES
Clock to output valid
tKL
3.0
4.0
ns
2
tKQ
Clock to output invalid
tKQX
3.0
3.0
ns
3
Clock to output in Low-Z
tKQLZ
3.0
3.0
ns
3, 4, 5, 6,
Clock to output in High-Z
tKQHZ
5.0
5.0
ns
3, 4, 5, 6,
OE\ to output valid
tOEQ
5.0
5.0
ns
7
OE\ to output in Low-Z
tOELZ
ns
3, 4, 5, 6,
OE\ to output in High-Z
SETUP TIMES
Address
tOEHZ
ns
3, 4, 5, 6,
tAS
1.8
2.0
ns
8, 9
Address status (ADSC\, ADSP\)
tADSS
1.8
2.0
ns
8, 9
Address advance (ADV\)
tAAS
1.8
2.0
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWS
1.8
2.0
ns
8, 9
Data-in
tDS
1.8
2.0
ns
8, 9
Chip enable (CE\)
HOLD TIMES
Address
tCES
1.8
2.0
ns
8, 9
tAH
0.5
0.5
ns
8, 9
Address status (ADSC\, ADSP\)
tADSH
0.5
0.5
ns
8, 9
Address advance (ADV\)
tAAH
0.5
0.5
ns
8, 9
Byte write enables (BWa\ - BWd\, GW\, BWE\)
tWH
0.5
0.5
ns
8, 9
Data-in
tDH
0.5
0.5
ns
8, 9
Chip enable (CE\)
tCEH
0.5
0.5
ns
8, 9
10.0
15.0
100
8.5
0
ns
66
10.0
0
5.0
5.0
MHz
ns
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
at
9.
Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
Measured as HIGH above VIH and LOW below VIL.
This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
This parameter is sampled.
Transition is measured +500mV from steady state voltage.
Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these
parameters.
OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by
least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or
ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges
of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to
remain enabled.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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9
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input Pulse Levels..................VIH = (VDD/2.2) +1.5V
..................VIL = (VDD/2.2) -1.5V
Input rise and fall times..........................................1ns
Input timing reference levels............................VDD/2.2
Output reference levels................................VDDQ/2.2
Output load.................................See Figures 1 and 2
OUTPUT LOADS
+3.3v
317Ω
DQ
DQ
Z0=50Ω
351Ω
50Ω
5 pF
Vt = 1.5V
Fig. 1 3.3V I/O OUTPUT LOAD EQUIVALENT
Fig. 2 3.3V I/O OUTPUT LOAD EQUIVALENT
NOTE: SRAM timing is dependent upon the capacitive loading on the outputs.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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10
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down” mode in
which the device is deselected and current is reduced to ISB2Z.
The duration of SNOOZE MODE is dictated by the length of
time ZZ is in a HIGH state. After the device enters SNOOZE
MODE, all inputs except ZZ become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that causes the
device to enter SNOOZE MODE. When ZZ becomes a logic
HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any
READ or WRITE operation pending when the device enters
SNOOZE MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until valid
pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
! NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t
t
ZZ
RZZ
ZZ
t
ZZI
ISUPPLY
t
SB2
t
ALL INPUTS*
*Except ZZ
12345
1123456789
12345
1RZZI
12345
123456789
1
12345
11
12345
1123456789
12345
12345
1123456789
12345
1
1234
1234
1234
Don’t Care
1234
1234
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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11
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
t
READ TIMING3
KC
t
KL
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
○
Deselect Cycle
(note 4)
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
12345
12345
12345
12345
12345
12345
12345
12345
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
1234567890123
12345678
1
1234567890123
12345678
1
12345678
1234567890123
1
1234567890123
1
12345678
1234567890123
1
12345678
1234567890123
12345678
1
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
Burst wraps around to
its initial state
○
○
1234
1234
1234
1234 Undefined
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123
123
12 Q(A2+1) 123
123
1 Q(A2+2)
123
123
○
Q(A2)
○
○
○
○
○
○
○
BURST READ
1234
1234
1234
1234 Don’t Care
○
○
○
○
○
○
○
○
○
12
12
12
○
Q(A2+3)
○
○
○
○
12
12
12
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
SINGLE READ
○
○
○
○
○
○
○
○
○
○
○
Q(A2+2)
○
○
12
12
12
(Note 1)
Q(A2+1)
tKQHZ
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123
1234
123
1234
123 Q(A2) 1234
○
○
t KQ
tKQX
○
○
t KQ
t OELZ
○
○
○
○
○
○
○
○
High-Z
○
Q
t OEHZ
1234
1234
1234
1234 Q(A1)
○
KQLZ
OEQ
○
○
○
○
t
t
○
○
○
○
○
○
○
○
○
○
○
○
○
OE\
○
○
○
○
○
ADV\ suspends burst.
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
1234567
1234567
1234567
1234567
1234567
1234567
○
○
○
○
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
tAAS
tAAH
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
12345
12345
12345
12345
12345
12345
12345
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
1234567890123456789012345678901212345678901234567890123456789012123456789012345678
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
123456
123456
123456
123456
123456
123456
123456
123456
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
12345678901234
○
1234567890123456789012
123456
1
1234567890123456789012
123456
1
1234567890123456789012
123456
1
123456
1
ADV\ 1234567890123456789012
123456
1
1234567890123456789012
1234567890123456789012
123456
1
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
CEH
○
○
○
○
○
○
○
○
○
t
WS
12345
1234
1234567890
1234
1234
12345
1234567890
1234
1234567890
1234
12345
1234
1234
12345
1234567890
1234
1234
12345
1234567890
1234
1234
12345
1234567890
1234
1234
○
○
○
○
○
○
○
WH
123456
123456
123456
123456
123456
123456
123456
123456
○
t
○
t
CES
123456
123456789012
12
123456
123456789012
12
123456789012
12
CE\ 123456
123456
123456789012
12
123456
123456789012
12
123456789012
12
(Note 2) 123456
○
○
○
○
t
○
○
t
AH
123456
123456
123456
123456
123456
123456
123456
123456
12345678
123456789012345678901234567890121234567890123456789012345678901212345678901234567890
1
12345678
123456789012345678901234567890121234567890123456789012345678901212345678901234567890
1
12345678
1
12345678
1123456789012345678901234567890121234567890123456789012345678901212345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890
12345678
1
12345678
1123456789012345678901234567890121234567890123456789012345678901212345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890
A2
○
○
○
○
○
○
○
A1
1234567890123456789012
123456
1
1234567890123456789012
123456
1
1234567890123456789012
123456
1
123456
1
BWE\, GW\, 1234567890123456789012
1234567890123456789012
123456
1
1234567890123456789012
123456
1
1234567890123456789012
123456
1
BWa\ - BWd\
123456
123456
123456
123456
123456
123456
○
○
12345678
12345678
123
12345678
12345678
123
123
12345678
12345678
12345678
123
12345678
12345678
123
12345678
12345678
123
12345678
123456
123456
123456
123456
123456
123456
123456
123456
○
t
ADSH
○
○
tAS
○
1234567
1234567
12
1234567
1234567
12
1234567
1234567
12
1234567
1234567
12
ADDRESS 1234567
1234567
12
1234567
1234567
12
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
○
○
○
○
○
t
ADSS
○
○
○
○
○
○
○
t
ADSH
12345
123456789
12345
1234
12345
123456789
12345
1234
12345
123456789
12345
1234
12345
123456789
12345
1234
12345
123456789
12345
1234
12345
12345
1234
123456789
KH
123456
123456
123456
123456
123456
123456
123456
123456
○
1234
1234
1234
ADSC\ 1234
1234
1234
t
○
○
123456
123456
123456
123456
123456
123456
○
123456
123456
123456
123456
123456
○
○
t
ADSS
123456
○
1234
1234
1234
1234
ADSP\ 1234
1234
○
○
○
○
○
○
CLK
READ/WRITE TIMING PARAMETERS
-8.5
SYMBOL
MIN
tKC
10.0
tKF
MIN
-10
-8.5
MAX
15
100
UNITS
SYMBOL
MIN
tAS
1.8
2.0
ns
MHz
tADSS
1.8
2.0
ns
ns
66
MAX
MIN
MAX
UNITS
tKH
3.0
4.0
ns
tAAS
1.8
2.0
ns
tKL
3.0
4.0
ns
tWS
1.8
2.0
ns
ns
tCES
1.8
2.0
ns
tKQ
8.5
10.0
tKQX
3.0
3.0
ns
tAH
0.5
0.5
ns
tKQLZ
3.0
3.0
ns
tADSH
0.5
0.5
ns
tKQHZ
5.0
5.0
ns
tAAH
0.5
0.5
ns
tOEQ
5.0
5.0
ns
tWH
0.5
0.5
ns
ns
tCEH
0.5
0.5
ns
tOELZ
tOEHZ
NOTE:
-10
MAX
0
0
5.0
5.0
ns
1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is
HIGH, CE2\ is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled tKQHZ after deselect.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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12
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
t
KC
t
WRITE TIMING
KL
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
1234567890
1234567890
1234567890
1234567890
1234567890
1234567890
123456
123456
123456
123456
123456
123456
123456
○
12345
12345
12345
12345
12345
12345
12345
○
○
○
○
○
○
○
123456
123456
123456
123456
123456
123456
123456
123456
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
1234567890
1234567890
1234567890
1234567890
1234567890
1234567890
○
○
○
○
○
○
○
○
○
○
○
t
12345
12345
12345
12345
12345
12345
12345
12345
○
○
○
○
12345
123456789
12345
12345
123456789
12345
12345
12345
123456789
12345
12345
123456789
12345
12345
123456789
12345
12345
123456789
ADV\ suspends burst.
AAH
○
○
○
○
12
12
12
12
12
12 D(A3+2) 12
12
○
○
○
○
○
○
○
○
12
12
12
12 D(A3+1)
○
○
○
○
D(A3)
○
○
12
12
○
○
○
○
12
12
○
○
12
12
D(A2+1) 12
12 D(A2+2) 12
12 D(A2+3) 12
12
○
○
○
○
○
Single WRITE
○
○
○
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1234
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12
1234
12
12
12
12
12
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1234
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12 D(A2) 12
12
12
1234
D(A1) 1234
1234
12
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12
12 D(A2+1) 12
12
t OEHZ
(Note 1)
○
○
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○
○
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12
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12
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123456
12
1234567890123456789012345
t AAS
○
○
○
123456
123456
123456
123456
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123456
○
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○
○
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○
t WH
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t WS
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A3
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t
ADSH
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12
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12
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12
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12
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○
○
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tDS tDH
BURST READ
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(Note 4)
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Q 12
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(Note 3)
○
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D
○
○
○
t WH
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ADSC\ extends burst.
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12345
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○
CEH
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
123456789012345678
○
○
○
○
○
○
○
○
○
○
t WS
(Note 5)
○
○
○
12345
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ADV\ 12345
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○
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t CES
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12
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CE\ 1234567
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12
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12
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(See Note) 1234567
123456
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BYTE WRITE signals are
ignored
when ADSP\
is LOW. 12345
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○
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○
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○
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CLK
BURST WRITE
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12345
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12345Don’t Care
Extended BURST WRITE
1234
1234
1234
1234Undefined
WRITE TIMING PARAMETERS
-8.5
SYMBOL
MIN
tKC
10.0
tKF
MIN
-10
-8.5
MAX
15
100
66
UNITS
SYMBOL
MIN
MAX
MIN
ns
tDS
1.8
2.0
MAX
UNITS
ns
MHz
tCES
1.8
2.0
ns
tKH
3.0
4.0
ns
tAH
0.5
0.5
ns
tKL
3.0
4.0
ns
tADSH
0.5
0.5
ns
ns
tAAH
0.5
0.5
ns
tOEHZ
NOTE:
-10
MAX
5.0
5.0
tAS
1.8
2.0
ns
tWH
0.5
0.5
ns
tADSS
1.8
2.0
ns
tDH
tAAS
0.5
0.5
ns
1.8
2.0
ns
tWS
tCEH
0.5
0.5
ns
1.8
2.0
ns
1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable
inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
t
KC
t
READ/WRITE TIMING3
KL
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ADV\ 1234567890123456789012345678901212345678901
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123456789
12345
○
○
○
○
○
○
○
CES
123456
123456
123456
123456
123456
123456
123456
○
123456
123456
123456
123456
123456
123456
123456
○
123456
123456
123456
123456
123456
123456
123456
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○
○
○
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○
○
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○
○
123456
123456
123456
123456
123456
123456
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○
123456
123456
123456
123456
123456
123456
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○
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○
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○
○
○
○
1234567
1234567
1234567
1234567
1234567
1234567
A3
○
○
○
○
○
12345678
12345678901
12
123456
12
12345678
12345678901
12
123456
12
12345678
12345678901
12
123456
12
12345678
12345678901
12
123456
12
12345678
12345678901
12
123456
12
12345678
12345678901
12
123456
12
12345678
12345678901
123456
12
t
123456
123456
123456
123456
123456
123456
123456
○
t
AH
○
○
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○
○
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A2
○
CE\
(See
Note)
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123
12345678
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123
12345678
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123
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123
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123
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123
○
tAS
○
○
A1
○
WEH\, WEL\,
BWE\, GW\
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123
123
123
123
123
123
○
ADDRESS
123456
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○
tADSH
123456
123456
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○
12345
12345
12345
ADSC\ 12345
12345
12345
tKH
○
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○
○
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○
tADSS
123456
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12345
12345
12345
12345
ADSP\ 12345
12345
○
○
CLK
D(A3)
D(A5)
○
○
t
OEHZ
SINGLE WRITE
Back-to-Back
READs
(Note 5)
D(A6)
KQ
○
1234
1234 Q(A1) 123
123 Q(A2)
1234
123
t
12
12
12
Q(A4)
12(Note 1)12
12
12 Q(A4+1) 12
12
Q(A4+2)
12
112
12
Q(A4+3)
BURST READ
1234
12345
1234
12345
1234
12345
12345Don’t Care
1234 Undefined
Back-to-Back
WRITEs
WRITE TIMING PARAMETERS
-8.5
SYMBOL
tKC
MIN
10.0
tKF
tKH
tKL
tOELZ
1.
2.
3.
4.
5.
MAX
15
3.0
66
4.0
3.0
4.0
8.5
0
tOEHZ
NOTE:
MIN
100
tKQ
-8.5
-10
MAX
10.0
0
5.0
5.0
-10
SYMBOL
MIN
ns
tWS
1.8
2.0
ns
MHz
tDS
1.8
2.0
ns
ns
tCES
1.8
2.0
ns
ns
tAH
0.5
0.5
ns
ns
tADSH
0.5
0.5
ns
ns
tWH
0.5
0.5
ns
ns
tDH
0.5
0.5
ns
tCEH
0.5
0.5
ns
UNITS
tAS
1.8
2.0
ns
tADSS
1.8
2.0
ns
MAX
MIN
MAX
UNITS
Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4.
CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\, ADSC\ or ADV\ cycle is performed.
GW\ is HIGH.
Back-to-back READs may be controlled by either ADSP\ or ADSC\.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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14
SSRAM
AS5SS256K36 &
AS5SS256K36A
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS
ASI Case #1001 (Package Designator DQ)
16.00 + 0.10
14.00 + 0.10
22.00 + 0.10
20.00 + 0.10
1.40 + 0.05
1.60 Max
NOTE: All dimensions in Millimeters.
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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0.65 Basic
0.30 + 0.08
0.60 + 0.15
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
SSRAM
Austin Semiconductor, Inc.
AS5SS256K36 &
AS5SS256K36A
ORDERING INFORMATION
EXAMPLE: AS5SS256K36ADQ-8.5/IT
Package
Speed ns Process
Device Number
Options**
Type
AS5SS256K36
A
DQ
-8.5
/*
AS5SS256K36
A
DQ
-10
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
**DEFINITION OF OPTIONS
2-Chip Enable Pinout
3-Chip Enable Pinout
AS5SS256K36 &
AS5SS256K36A
Rev. 1.5 5/00
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-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
A
no indicator
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16