COTS PEM SSRAM AS5SP256K36 • 81 82 84 83 87 85 86 89 88 91 90 92 95 93 94 96 97 98 99 100 80 2 79 3 78 4 77 5 76 DQc DQc 6 75 7 74 DQc DQc 8 73 9 72 VSSQ VDDQ 10 71 11 70 DQc 12 69 DQc NC VDD 13 68 NC VSS DQd 16 65 17 64 18 63 DQd 19 62 VDDQ VSSQ 20 61 21 60 DQd 22 59 DQd DQd 23 58 24 57 VSSQ DQa DQa DQa DQd VSSQ VDDQ DQd DQd DQPd 25 56 DQa 26 55 27 54 28 53 29 52 VSSQ VDD DQa DQa 30 51 DQP 14 67 VDD VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDD 50 49 48 47 46 45 44 43 42 41 66 DQP DQb DQb VDD NC* A A A A A A A A 40 39 38 37 35 34 33 36 SSRAM [SPB] 15 32 • • • • • • • Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges RoHs compliant options available 1 DQc DQc VDDQ VSSQ 31 FEATURES • Synchronous Operation in relation to the input Clock • 2 Stage Registers resulting in Pipeline operation • On chip address counter (base +3) for Burst operations • Self-Timed Write Cycles • On-Chip Address and Control Registers • Byte Write support • Global Write support • On-Chip low power mode [powerdown] via ZZ pin • Interleaved or Linear Burst support via Mode pin • Three Chip Enables for ease of depth expansion without DQPc MODE A A A A A1 A0 NC* NC* VSS 9.0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Plastic Encapsulated Microcircuit FAST ACCESS TIMES Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns GENERAL DESCRIPTION The AS5SP256K36 is a 9.0Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 256K x 36. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. BLOCK DIAGRAM OE\ ZZ CLK CE1\ CE2 I/O Gating and Control CE3\ BWE\ BWx\ CONTROL BLOCK GW\ ADV\ ADSC\ ADSP\ MODE A0-Ax AS5SP256K36 Rev. 2.2 10/13 BURST CNTL. Address Registers Row Decode Memory Array x36 SBP ❑ Synchronous Pipeline Burst ❋ Two (2) cycle load ❋ One (1) cycle de-select ❋ One (1) cycle latency on Mode change Output Register Output Driver DQx, DQP Input Register Column Decode The AS5SP256K36 includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV\, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Strobe Processor (ADSP\) or Address Strobe controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance (ADV\) control input. Micross Components reserves the right to change products or specifications without notice. 1 COTS PEM SSRAM AS5SP256K36 PIN DESCRIPTION / ASSIGNMENT TABLE Signal Name Clock Symbol CLK Type Input Address A0, A1 Input Address A Input(s) Chip Enable Chip Enable Global Write Enable Byte Enables Input Input Input Input Byte Write Enable Output Enable Address Strobe Controller CE1\, CE3\ CE2 GW\ BWa\, BWb\, BWc\, BWd\ BWE\ OE\ ADSC\ Input Input Input 87 86 85 Address Strobe from Processor ADSP\ Input 84 Address Advance ADV\ Input 83 Power-Down ZZ Input 64 Data Parity Input/Outputs DQPa, DQPb DQPc, DQPd Input/ Output Data Input/Outputs DQa, DQb, DQc Input/ DQd Output Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O MODE VDD VSS VDDQ Input Supply Supply Supply I/O Ground VSSQ Supply No Connection(s) NC NA AS5SP256K36 Rev. 2.2 10/13 Pin Description This input captures all synchronous inputs to the device as well as synchronizes the burst control functions. 37, 36 Low order, Synchronous Address Inputs and Burst counter address inputs 35, 34, 33, 32, 31, 100, Synchronous Address Inputs 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 98, 92 Active Low True Chip Enables 97 Active High True Chip Enable 88 Active Low True Global Write enable. Write to all bits 93, 94, 95, 96 Active Low True Byte Write enables. Write to byte segments 89 51, 80, 1, 30 Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Bur When ADSP\ and ADSC are both asserted, only ADSP is recognized Address Strobe from Processor. When asserted LOW, Address is captured in the Address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH Advance input Address. When asserted LOW, address in burst counter is incremented. Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. Bidirectional I/O Parity lines. As inputs they reach the memory array via data register, that is triggered on the rising edge of clock. As an output, the line delivers the valid data stored in the array via an output register and output driver. The data delievered is from the previous clock period of the READ cycle. Bidirectional I/O Parity lines. As inputs they reach the memo array via data register, that is triggered on the rising edge of clock. As an output, the line delivers the valid data stored in the array via an output register and output driver. The data delievered is from the previous clock period of the READ cycle. Interleaved or Linear Burst mode control Core Power Supply Core Power Supply Ground Isolated Input/Output Buffer Supply 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 31 91, 15, 41, 65 90, 17, 40, 67 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground 71, 76 14, 16, 38, 39, 65 No connections to internal silicon Micross Components reserves the right to change products or specifications without notice. 2 COTS PEM SSRAM AS5SP256K36 LOGIC BLOCK DIAGRAM A 0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 ADSP BW D DQ D ,DQP D BYTE WRITE REGISTER DQ D ,DQPD BYTE WRITE DRIVER BW C DQ C ,DQP C BYTE WRITE REGISTER DQ C ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE DRIVER BW B BW A BWE ZZ AS5SP256K36 Rev. 2.2 10/13 ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP B DQP C DQP D DQ A ,DQP A BYTE WRITE DRIVER DQ A ,DQP A BYTE WRITE REGISTER GW CE 1 CE 2 CE 3 OE MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL Micross Components reserves the right to change products or specifications without notice. 3 COTS PEM SSRAM AS5SP256K36 FUNCTIONAL DESCRIPTION cycle. Consecutive single cycle READS are supported. Once Micross Components AS5SP256K36 Synchronous SRAM is the READ operation has been completed and deselected by use manufactured to support today’s High Performance platforms of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs utilizing the Industries leading Processor elements including will tri-state immediately. those of Intel and Motorola. The AS5SP256K36 supports Synchronous SRAM READ and WRITE operations as well as A Single ADSP\ controlled WRITE operation is initiated when Synchronous Burst READ/WRITE operations. All inputs with both of the following conditions are satisfied at the time of the exception of OE\, MODE and ZZ are synchronous in nature Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip and sampled and registered on the rising edge of the devices Enable(s) are asserted ACTIVE. The address presented to input clock (CLK). The type, start and the duration of Burst the address bus is registered and loaded on CLK HIGH, then Mode operations is controlled by MODE, ADSC\, ADSP\ and presented to the core array. The WRITE controls Global Write, ADV\ as well as the Chip Enable pins CE1\, CE2, and CE3\. and Byte Write Enable (GW\, BWE\) as well as the individual All synchronous accesses including the Burst accesses are Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are enabled via the use of the multiple enable pins and wait state ignored on the first machine cycle. ADSP\ triggered WRITE insertion is supported and controlled via the use of the Advance accesses require two (2) machine cycles to complete. If Global Write is asserted LOW on the second Clock (CLK) rise, the control (ADV\). data presented to the array via the Data bus will be written into The AS5SP256K36 supports both Interleaved as well as Linear the array at the corresponding address location specified by the Burst modes therefore making it an architectural fit for either Address bus. If GW\ is HIGH (inactive) then BWE\ and one or the Intel or Motorola CISC processor elements available on the more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\) controls the write operation. All WRITES that are initiated in Market today. this device are internally self timed. The AS5SP256K36 supports Byte WRITE operations and enters this functional mode with the Byte Write Enable (BWE\) and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global Writes are supported via the Global Write Enable (GW\) and Global Write Enable will override the Byte Write inputs and will perform a Write to all Data I/Os. The AS5SP256K36 provides ease of producing very dense arrays via the multiple Chip Enable input pins and Tri-state outputs. Single Cycle Access Operations A Single READ operation is initiated when all of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are in their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. The address presented to the Address inputs is stored within the Address Registers and Address Counter/Advancement Logic and then passed or presented to the array core. The corresponding data of the addressed location is propagated to the Output Registers and passed to the data bus on the next rising clock via the Output Buffers. The time at which the data is presented to the Data bus is as specified by either the Clock to Data valid specification or the Output Enable to Data Valid spec for the device speed grade chosen. The only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following AS5SP256K36 Rev. 2.2 10/13 A Single ADSC\ controlled WRITE operation is initiated when the following conditions are satisfied: [1] ADSC\ is asserted LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are asserted (TRUE or Active), and [4] the appropriate combination of the WRITE inputs (GW\, BWE\, BWx\) are asserted (ACTIVE). Thus completing the WRITE to the desired Byte(s) or the complete data-path. ADSC\ triggered WRITE accesses require a single clock (CLK) machine cycle to complete. The address presented to the input Address bus pins at time of clock HIGH will be the location that the WRITE occurs. The ADV\ pin is ignored during this cycle, and the data WRITTEN to the array will either be a BYTE WRITE or a GLOBAL WRITE depending on the use of the WRITE control functions GW\ and BWE\ as well as the individual BYTE CONTOLS (BWx\). Deep Power-Down Mode (SLEEP) The AS5SP256K36 has a Deep Power-Down mode and is controlled by the ZZ pin. The ZZ pin is an Asynchronous input and asserting this pin places the SSRAM in a deep powerdown mode (SLEEP). While in this mode, Data integrity is guaranteed. For the device to be placed successfully into this operational mode the device must be deselected and the Chip Enables, ADSP\ and ADSC\ remain inactive for the duration of tZZREC after the ZZ input returns LOW. Use of this deep power-down mode conserves power and is very useful in multiple memory page designs where the mode recovery time can be hidden. Micross Components reserves the right to change products or specifications without notice. 4 COTS PEM SSRAM AS5SP256K36 SYNCHRONOUS TRUTH TABLES CE1\ H L L L L L L L X H X H X H X H CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L H H L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV\ X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE Notes: 1. X = Don’t Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE BURST SEQUENCE TABLES Burst Control Pin [MODE] First Address State HIGH Case 1 A1 0 0 1 1 Fourth Address Burst Control Pin [MODE] First Address A0 State LOW Case 1 A0 A1 0 0 1 1 Fourth Address CAPACITANCE Interleaved Burst Case 2 A1 A0 0 0 1 0 0 1 1 1 0 1 0 1 Linear Burst Case 2 A1 A0 0 1 1 0 Case 3 A1 1 0 1 0 Case 4 A0 1 1 0 0 A1 0 1 0 1 1 1 0 0 Case 3 A1 1 0 1 0 A Case 4 A0 1 1 0 0 A1 0 1 0 1 1 0 0 1 BW\ H L L L L L X BWa\ X H L H H L X BWb\ X H H L H L X BWc\ X H H H L L X BWd\ X H H H L L X Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE Byte [C], [D] WRITE ALL Bytes WRITE ALL Bytes ZZ H L L L L Power-Down (SLEEP) READ OE\ X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z Rt = 50 ohm Zo=50 ohm Vt= Termination Voltage Rt= Termination Resistor Units 4.6 Units pF pF pF Output Diagram [A] Max. Max. 6 8 6 AC TEST LOADS ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Parameter Symbol Min. -0.3 Voltage on VDD Pin VDD Voltage on VDDQ Pins VDDQ VDD Voltage on Input Pins VIN -0.3 Voltage on I/O Pins VIO -0.3 Power Dissipation PD Storage Temperature tSTG -65 Operating Temperatures /IT -40 [Screening Levels] /ET -40 /XT -55 Symbol CI CIO CCLK ASYNCHRONOUS TRUTH TABLE A Operation WRITE De-Selected WRITE TABLE GW\ H H H H H H L Parameter Input Capacitance Input/Output Capacitance Clock Input Capacitance 30 pF Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ V R= 317 [email protected] R= 1667 [email protected] V VDD+0.3 V VDDQ+0.3 V 1.6 W R C 150 85 R 105 R 125 R Output 3.3/2.5v 5 pF R= 351 [email protected] R= 1538 [email protected] C C Diagram [B] C *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 5 COTS PEM SSRAM AS5SP256K36 DC Electrical Characteristics (VDD=3.3v -5%/+10%), TA= Min. and Max temperatures of Screening level chosen) Symbol VDD VDDQ VoH Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Test Conditions 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA Output Low Voltage VoL VDD=Min., IOL=8mA VDD=Min., IOL=1mA VIH Input High Voltage VIL Input Low Voltage IIL IZZL IOL IDD Input Leakage (except ZZ)&Mode VDD=Max., VIN=VSS to VDD Input Leakage, ZZ pin & mode Output Disabled, VOUT=VSSQ to VDDQ Output Leakage VDD=Max., f=Max., 5.0ns Cycle, 200 Mhz Operating Current IOH=0mA 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz Max. VDD, Device De-Selected, Automatic CE. Power-down Current -TTL inputs VIN>/=VIH or VIN</=VIL 5.0ns Cycle, 200 Mhz f=fMAX=1/tCYC 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v Automatic CE. Power-down f=0 Current - CMOS Inputs ISB1 ISB2 Min 3.135 2.375 2.4 2 2 1.7 -0.3 -0.3 -5 -30 -5 Max 3.630 VDD 0.4 0.4 VDD+0.3 VDD+0.3 0.8 0.7 5 30 5 275 250 225 Units V V V V V V V V V V uA uA uA mA mA mA 150 140 130 110 mA mA mA mA Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 THERMAL RESISTANCE Parameter ȺJA ȺJC Description ThermalResistance (JunctiontoAmbient) ThermalResistance (JunctiontoCase) TestConditions Testconditionsfollowstandardtest methodsandproceduresfor measuringthermalimpedance,per EIA/JESD51 DQ DQC Package Package Unit 29.41 30.2 o 6.13 6.5 o C/W C/W Notes: [1] [2] [3] [4] [5] [6] AS5SP256K36 Rev. 2.2 10/13 All Voltages referenced to VSS (Logic Ground) Overshoot: VIH < +4.6V for t<tCYC/2 for I<20mA Undershoot: VIL >-0.7V for t<tCYC/2 for I<20mA Power-up: VIH <+3.6V and VDD<3.135V for t<200ms MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +100uA The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies. AC load current is higher than stated values, AC I/O curves can be made available upon request VDDQ should never exceed VDD, VDD and VDDQ can be connected together This parameter is sampled Micross Components reserves the right to change products or specifications without notice. 6 COTS PEM SSRAM AS5SP256K36 AC Switching Characteristics (VDD=VDDQ=3.3v -5%/+10%,) TA= Min. and Max temperatures of Screening level chosen) Parameter Clock (CLK) Cycle Time Clock (CLK) High Time Clock (CLK) Low Time Clock Access Time Clock (CLK) High to Output Low-Z Clock High to Output High-Z Output Enable to Data Valid Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Address Set-up to CLK High Address Hold from CLK High Address Status Set-up to CLK High Address Status Hold from CLK High Address Advance Set-up to CLK High Address Advance Hold from CLK High Chip Enable Set-up to CLK High (CEx\, CE2) Chip Enable Hold from CLK High (CEx\, CE2) Data Set-up to CLK High Data Hold from CLK High Write Set-up to CLK High (GW\, BWE\, BWx\) Write Hold from CLK High (GW\, BWE\, BWX\) ZZ High to Power Down ZZ Low to Power Up 1. 2. 3. 4. 5. 6. 7. 8. 9. AS5SP256K36 Rev. 2.2 10/13 Symbol tCYC tCH tCL tCD tCLZ tCHZ tOE tOH tOELZ tOEHZ tAS tAH tASS tASH tADVS tADVH tCES tCEH tDS tDH tWES tWEH tPD tPU -30 [200Mhz] Min. Max. 5.00 2.00 2.00 3.00 1.25 1.25 3.00 3.00 1.25 0.00 3.00 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 2 2 -35 [166Mhz] Min. Max. 6.00 2.20 2.20 3.50 1.25 1.25 3.50 3.50 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -40 [133Mhz] Min. Max. 7.50 2.50 2.50 4.00 1.25 1.25 3.50 4.00 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles Notes 1 1 2 2,3,4,5 2,3,4,5 6 2,3,4,5 2,3,4,5 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 Measured as HIGH when above VIH and Low when below VIL This parameter is measured with the output loading shown in AC Test Loads This parameter is sampled Transition is measured +500mV from steady state voltage Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention OE\ is a Don't Care when a Byte or Global Write is sampled LOW A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD (minimum) initially before a Read or Write operation can be initiated. Micross Components reserves the right to change products or specifications without notice. 7 COTS PEM SSRAM AS5SP256K36 AC Switching Waveforms Write Cycle Timing Single Write Burst Write tCYC Pipelined Write tCH CLK tASS tASH tCL ADSP\ ADSP\ Ignored with CE1\ inactive ADSC\ tASS tASH ADV\ tADVS Ax tADVH A1 ADV\ Must be Inactive for ADSP\ Write A3 A2 tAS tAH GW\ tWES tWEH tWEH tWES BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ CE2 CE3\ OE\ tDS DQx,DQPx tDH W1 W2a W2b W2c W2d W3 DON'T CARE UNDEFINED AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 8 COTS PEM SSRAM AS5SP256K36 AC Switching Waveforms Read Cycle Timing Single Read Burst Read tCYC tCH Pipelined Read tCL CLK tASS tASH ADSP\ Ignored with CE1\ Inactive ADSP\ ADSC\ Initiated Read ADSC\ Suspend Burst ADV\ tADVS Ax tADVH A2 A1 tAS A3 tAH GW\ tWES tWEH BWE\, BWx\ tCES CE1\ Masks ADSP\ tCEH CE1\ Unselected with CE2 CE2 CE3\ OE\ tOEHZ tOE tCD DQx,DQPx R1 tOH R2a R2b R2c R2d R3a DON'T CARE UNDEFINED AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 9 COTS PEM SSRAM AS5SP256K36 AC Switching Waveforms Read / Write Cycle Timing tCYC Pipelined Read Burst Read tCH tCL CLK tASS tASH ADSP\ ADSC\ ADV\ tADVS tADVH tAS Ax A1R A2W A3W A4R A5R tAH GW\ tWES tWEH BWE\, BWx\ tCES tCEH tCES tCEH CE1\ CE2 CE3\ OE\ tOE DQx,DQPx DON'T CARE A1O tOEHZ tOH A2I A4O [a] A3I A4O [b] A4O [c] A4O [d] tOELZ tCD UNDEFINED AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 10 COTS PEM SSRAM AS5SP256K36 Power Down (SNOOZE MODE) Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total memory array solution. The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE) mode is done so by de-asserting the ZZ pin . While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery time (tZZREC). ZZ MODE ELECTRICAL CHARACTERISTICS Parameter Power Down (SNOOZE) Mode ZZ Active (Signal HIGH) to Power Down ZZ Inactive (Signal Low) to Power Up Symbol Test Conditon IDDzz ZZ >/- VDD - 0.2V tZZS ZZ >/- VDD - 0.2V tZZR ZZ </- 0.2V Min. 2 tCYC Max. 75 2 tCYC Units mA ns ns ZZ MODE TIMING DIAGRAM CLK ADSP\ ADSC\ CEx\ CE2 ZZ tZZS IDD AS5SP256K36 Rev. 2.2 10/13 tZZREC IDDzz Micross Components reserves the right to change products or specifications without notice. 11 COTS PEM SSRAM AS5SP256K36 MECHANICAL DEFINITION 100-Pin TQFP (Package Designator DQ) AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 12 COTS PEM SSRAM AS5SP256K36 ORDERING INFORMATION TQFP Device Number AS5SP256K36DQ-30/IT AS5SP256K36DQ-35/IT AS5SP256K36DQ-40/IT AS5SP256K36DQ-30/ET AS5SP256K36DQ-35/ET AS5SP256K36DQ-40/ET AS5SP256K36DQ-35/XT AS5SP256K36DQ-40/XT Configuration 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO 256Kx36, 3.3vCore/3.3,2.5vIO *AVAILABLE PROCESSES IT = Industrial Temperature Range ET = Enhanced Temperature Range XT = Military Temperature Range AS5SP256K36 Rev. 2.2 10/13 tCD (ns) 3.0 3.5 4.0 3.0 3.5 4.0 3.5 4.0 Clock (Mhz) 200* 166 133 200 166 133 166 133 -40oC to +85oC -40oC to +105oC -55oC to +125oC Micross Components reserves the right to change products or specifications without notice. 13 COTS PEM SSRAM AS5SP256K36 DOCUMENT TITLE 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect REVISION HISTORY Rev # 1.6 History Updated Assignment Table to indicate ADV\ Low Release Date June 2009 Status Release 1.7 Changed all references to ADV\ June 2009 Release 1.8 Updated DC Chart July 2009 Release 1.9 Added Micross Information January 2010 Release 2.0 Added copper lead frame and RoHS May 2011 compliant options, Updated IDDzz from 60mA to 75mA, Updated logic block diagram on page 2. Deleted ISB3 & ISB4 specs. Changed: IDDMax (-30) (-35) (-40) ISB1Max (-30) (-35) (-40) ISB2Max CI &CCLK CIO ΘJA ΘJC From 220mA 180mA 140mA 120mA 110mA 100mA 40mA 5pf 5pf 35oc/w 9oc/w Release To 275mA 250mA 225mA 150mA 140mA 130mA 110mA 6pf 8pf 29.41oc/w 6.13oc/w 2.1 Added Thermal Resistance for DQC package, page 6. September 2011 Release 2.2 Removed Cu-lead frame option October 2013 Release AS5SP256K36 Rev. 2.2 10/13 Micross Components reserves the right to change products or specifications without notice. 14