AS5SS256K18

SSRAM
AS5SS256K18
256K x 18 SSRAM
PIN ASSIGNMENT
(Top View)
Synchronous Burst SRAM,
Flow-Through
100-pin TQFP (DQ)
SA
SA
CE\
CE2
NC
NC
bwB\
BWa\
CE2\
VDD
VSS
CLK
GW\
BWE\
OE\
ADSC\
ADSP\
ADV\
SA
SA
FEATURES
• Timing
7.5ns/8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
MARKING
-8
-9
-10
1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 47 48 49 50
MODE
SA
SA
SA
SA
OPTIONS
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
81
SA
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
SA
SA
SA
SA
SA
SA
• Fast access times: 8, 10, and 15ns
• Fast clock speed: 113, 100, and 66 MHz
• Fast clock and OE\ access times
• Single +3.3V ± 5% power supply (VDD)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRTIE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address
pipelining
• Clock-controlled and registered addresses, data I/Os and
control signals
• Interally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• Low capacitive bus loading
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
• RoHs compliant options available
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
• Packages
TQFP
DQ
• Operating Temperature Ranges:
- Military -55oC to +125oC
- Enhanced -45oC to +105oC
- Industrial -45oC to +85oC
/IT
/ET
/XT
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\).
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. The data-out
(Q), enabled by OE\, is also asynchronous. WRITE cycles can be from
one to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent
burst addresses can be internally generated as controlled by the burst
advance input (ADV\).
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this
x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb
pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits
are available on this device.
The 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are TTL-compatible. The
device is ideally suited for 486, Pentium®, and PowerPC systems and
those systems that benefit from a wide synchronous data bus.
No. 1001
GENERAL DESCRIPTION
The Micross Components Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated
using an advanced CMOS process.
The 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE\), two additional chip enables for easy depth expansion (CE2\,
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
1
SSRAM
AS5SS256K18
PIN DESCRIPTIONS
PIN NUMBERS
SYM
TYPE
DESCRIPTION
37, 36, 32-35, 44-50,
80-82, 99, 100
93, 94
SA0, SA1,
SA
BWa\
BWb\
Input
87
BWE\
Input
88
GW\
Input
89
CLK
Input
98
CE\
Input
92
CE2\
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written and must meet the setup and hold times around the rising edge of CLK. A byte
write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\ controls DQa
pins and DQPa; BWb\ controls DQb pins and DQPb.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet
the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the
BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of
CLK.
Clock: This signal registers the addresses, data, chip enables, byte write enables and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device and
Conditions the internal use of ADSP\. CE\ is sampled only when a new external address is
loaded.
Synchronous Chip Enable: This active LOW input is used to enable the device and is
sampled only when a new external address is loaded.
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable the device and is
sampled only when a new external address is loaded.
86
OE\
Input
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
83
ADV\
Input
84
ADSP\
Input
85
ADSC\
Input
31
MODE
Input
64
ZZ
Input
(a) 58, 59, 62, 63, 68,
69, 72, 73
(b) 8, 9, 12,13, 18, 19,
22, 23
74, 24
DQa
DQb
Input/
Output
Synchronous Address Advance: This active LOW input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. A HIGH on this
pin effectively causes wait states to be generated (no address advance). To ensure use of
correct address during WRITE cycle, ADV\ must be HIGH at the rising edge of the first
clock after an ADSP\ cycle is initiated.
Synchronous Address Status Processor: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ is performed using the
new address, independent of the byte write enables and ADSC\, but dependent upon CE\,
CE2, and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if CE2 if
LOW or CE2\ is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ or WRITE is performed
using the new address if CE\ is LOW. ADSC\ is also used to place the chip into powerdown state when CE\ is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A
NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while
device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a lowpower standby mode in which all data in the memory array is retained. When ZZ is active,
all other inputs are ignored.
SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup
and hold times around the rising edge of CLK.
NC/DQPa
NC/DQPb
NC/ I/O
No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins.
Input
15, 41,65, 91
VDD
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
4, 11, 20, 27, 54, 61,
70, 77
VDDQ
Supply
Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for
range.
5, 10, 14, 17, 21, 26,
40, 55, 60, 67 71, 76,
90
38, 39
VSS
Supply
Ground: GND
DNU
---
1-3, 6, 7, 16,25, 28-30,
51-53, 56,57, 66, 75,
78, 79, 95, 96
NC
-----
42, 43
NF
AS5SS256K18
Rev. 2.5 10/13
Do Not Use: These signals may either be unconnected or wired to GND to improve
package heat dissipation.
No Connect: These signals are not internally connected and may be connected to ground to
improve package heat dissipation.
No Function: These pins are internally connected to the die and will have the capacitance of
input pins. It is allowable to leave these pins unconnected or driven by signals.
Micross Components reserves the right to change products or specifications without notice.
2
SSRAM
AS5SS256K18
INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE=LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE Byte "b"
WRITE All Bytes
WRITE All Bytes
GW\
H
H
H
H
H
L
BWE\
H
L
L
L
L
X
BWa\
X
H
L
H
L
X
BWb\
X
H
H
L
L
X
NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be
written.
FUNCTIONAL BLOCK DIAGRAM
18
SA0, SA1, SA
MODE
ADV\
CLK
18
ADDRESS
REGISTER
16
2
Q1
BINARY
COUNTER AND
LOGIC
Q0
CLR
18
SA0-SA1
SA1'
SA0'
ADSC\
ADSP\
BWb\
9
BYTE "b"
WRITE REGISTER
9
BWa\
BWE\
GW\
CE\
CE2
CE2\
OE\
BYTE "a"
WRITE REGISTER
BYTE "b"
WRITE DRIVER
BYTE "a"
WRITE DRIVER
9
9
256K x 9 x 2
MEMORY
ARRAY
18
SENSE
AMPS
18
OUTPUT
BUFFERS
18
DQs
DQPa
DQPb
INPUT
REGISTERS
18
ENABLE
REGISTER
2
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing
diagrams for detailed information.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SS256K18
TRUTH TABLE
OPERATION
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
USED
NONE
NONE
NONE
NONE
NONE
NONE
EXTERNAL
EXTERNAL
EXTERNAL
EXTERNAL
EXTERNAL
NEXT
NEXT
NEXT
NEXT
NEXT
NEXT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTES: 1. X means “Don’t Care.” \ means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for all BWx\,
BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input
data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals
and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SS256K18
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V
Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V
Storage Temperature (plastic) .....................-55C to +125C
Max Junction Temperature**.......................................+150C
Short Circuit Output Current..........…...........................100mA
*Stresses greater than those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
**Maximum junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ± 5% unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
CONDITIONS
SYMBOL
VIH
MIN
2.0
MAX
VDD +0.3
UNITS
V
NOTES
1, 2
VIL
-0.3
0.8
V
1, 2
(0V<VIN<VDD)
ILI
-2
2
P$
3
Output(s) disabled;
0V<VIN<VDD
ILO
-2
2
P$
Output High Voltage
IOH = -4.0mA
VOH
2.4
--
V
1, 4
Output Low Voltage
IOL = 8.0 mA
VOL
--
0.5
V
1, 4
VDD
3.135
3.465
V
1
VDDQ
3.135
3.465
V
1, 5
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Supply Voltage
Isolated Output Buffer Supply
CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
CONDITIONS
SYM
MAX
UNITS
NOTES
TA = 25°C; f = 1MHz;
CI
6
pF
6
VDD = 3.3V
CO
8
pF
6
THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
DQ
DQC
Package Package
CONDITIONS
SYM
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
TJA
30.32
TJC
6.85
UNITS
NOTES
35.25
°C/W
6
7.96
°C/W
6
NOTES:
1. All voltages referenced to VSS (GND)
2. Overshoot: VIH < +4.6V for t < tKC/2 for I < 20mA
Undershoot: VIL > -0.7V for t < tKC/2 for I < 20mA
Power-up: VIH < +3.465V and VDD<3.135V for t < 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10μA.
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
6. This parameter is sampled.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
5
SSRAM
AS5SS256K18
IDD ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ±5% unless otherwise noted)
PARAMETER
Power Supply Current:
Operating
CONDITIONS
Device selected; all inputs < VIL or > VIH;
Cycle time > tKC (MIN); VDD = MAX; Outputs Open
SYM
-8
MAX
-9
-10
IDD
225
205
185
mA
2, 3, 4
ISB2
90
90
90
mA
3, 4
ISB3
120
120
120
mA
3, 4
UNITS NOTES
Device deselected; VDD = MAX;
CMOS Standby
TTL Standby
All inputs < Vss +0.2 or > VDDQ -0.2;
All inputs static; CLK frequency =0
Device deselected; VDD = MAX;
All inputs < VIL or > VIH;
All inputs static; CLK frequency = 0
NOTES:
1. VDDQ = +3.3V ± 5%
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle
times and greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C and 15ns cycle time.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
6
SSRAM
AS5SS256K18
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) -55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ± 5% unless otherwise noted)
DESCRIPTION
SYMBOL
-8
MIN
-9
MAX
MIN
-10
MAX
MIN
MAX
UNITS
NOTES
CLOCK
Clock cycle time
tKC
Clock frequency
tKF
Clock HIGH time
Clock LOW time
8.8
10
113
15
100
ns
66
MHz
tKH
2.5
3.0
4.0
ns
2
tKL
2.5
3.0
4.0
ns
2
OUTPUT TIMES
Clock to output valid
tKQ
7.5
8.5
10
ns
Clock to output invalid
tKQX
1.5
3.0
3.0
ns
3
Clock to output in Low-Z
tKQLZ
1.5
3.0
3.0
ns
3, 4, 5
Clock to output in High-Z
tKQHZ
4.2
5.0
5.0
ns
3, 4, 5
OE\ to output valid
tOEQ
4.2
5.0
5.0
ns
6
ns
3, 4, 5
ns
3, 4, 5
OE\ to output in Low-Z
tOELZ
OE\ to output in High-Z
SETUP TIMES
tOEHZ
Address
0
0
4.2
0
5.0
5.0
tAS
1.5
1.8
2.0
ns
7, 8
Address status (ADSC\, ADSP\)
tADSS
1.5
1.8
2.0
ns
7, 8
Address advance (ADV\)
tAAS
1.5
1.8
2.0
ns
7, 8
Byte write enables (BWa\-BWb\, GW\, BWE\)
tWS
1.5
1.8
2.0
ns
7, 8
Data-in
tDS
1.5
1.8
2.0
ns
7, 8
Chip enable (CE\)
HOLD TIMES
tCES
1.5
1.8
2.0
ns
7, 8
Address
tAH
0.5
0.5
0.5
ns
7, 8
Address status (ADSC\, ADSP\)
tADSH
0.5
0.5
0.5
ns
7, 8
Address advance (ADV\)
tAAH
0.5
0.5
0.5
ns
7, 8
Byte write enables (BWa\-BWb\, GW\, BWE\)
tWH
0.5
0.5
0.5
ns
7, 8
Data-in
tDH
0.5
0.5
0.5
ns
7, 8
Chip enable (CE\)
tCEH
0.5
0.5
0.5
ns
7, 8
NOTES:
1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ± 5%) unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
7. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is
defined by at least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\
or ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising
edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is
LOW to remain enabled.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
7
SSRAM
AS5SS256K18
OUTPUT LOADS
AC TEST CONDITIONS
VIH = (VDD/2.2) + 1.5V
Input pulse levels
DQ
VIL = (VDD/2.2) - 1.5V
1ns
VDD/2.2
Input rise and fall times
Input timing reference levels
Output reference levels
Z0=50
50
VDDQ/2.2
See Figures 1 and 2
Output load
Vt = 1.5V
Fig. 1 OUTPUT LOAD EQUIVALENT
LOAD DERATING CURVES
The 256K x 18 Synchronous Burst SRAM timing is dependent upon
the capacitive loading on the outputs.
3.3v
SNOOZE MODE
317
SNOOZE MODE is a low-current, “power-down” mode in which the
device is deselected and current is reduced to ISB2Z. The duration of
SNOOZE MODE is dictated by the length of time ZZ is in a HIGH
state. After the device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that causes the device
DQ
5 pF
351
to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z
is guaranteed after the setup time tZZ is met. Any READ or WRITE
operation pending when the device enters SNOOZE MODE is not
quaranteed to complete successfully. Therefore, SNOOZE MODE
must not be initiated until valid pending operations are completed.
Fig. 2 OUTPUT LOAD EQUIVALENT
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
MAX
UNITS
ISB2Z
45
mA
ZZ active to input ignored
tZZ
tKC
ns
1
ZZ inactive to input sampled
tRZZ
ns
1
ZZ active to snooze current
tZZI
ns
1
ZZ inactive to exit snooze current
tRZZI
ns
1
Current during SNOOZE MODE
CONDITIONS
SYM
ZZ > VIH
MIN
tKC
tKC
0
NOTES
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
tRZZ
tZZ
ZZ
ISUPPLY
tZZI
ISB2
tRZZI
ALL INPUTS*
* Except ZZ
AS5SS256K18
Rev. 2.5 10/13
Don’t Care
Micross Components reserves the right to change products or specifications without notice.
8
SSRAM
AS5SS256K18
READ TIMING
tKC
tKL
CLK
tKH
tADSS
ADSP\
tADSH
tADSS
ADSC\
tAS
A1
ADDRESS
Deselect Cycle
(Note 4)
tADSH
A2
tAH
BWE\, GW\,
BWa\-BWb\
tCES tCEH tWS tWH
CE\
(Note 2)
tAAS tAAH
ADV\
ADV\ suspends burst.
OE\
Q
High-Z
tOEQ
tKQLZ
tOEHZ
Q(A1)
tKQ
tOELZ tKQ
tKQX
Q(A2)
tKQHZ
Q(A2+1)
SINGLE READ
NOTE:
Q(A2+2)
Q(A2+3)
(NOTE 1)
Q(A2)
Q(A2+1)
Q(A2+2)
Burst wraps around to
its initial state.
BURST READ
1. Q(A2) referes to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled tKQHZ after deselect.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
9
SSRAM
AS5SS256K18
tKC
tKL
CLK
WRITE TIMING
tKH
tADSS
ADSP\
ADSC\ extends burst. t
ADSS
tADSH
ADSC\
tAS
ADDRESS
A1
tADSH
A2
tAH
A3
tWS tWH
BYTE WRITE signals are ignored
when ADSP\ is LOW.
BEW\,
BWa\ - BWb\
t t
(Note 5) WS WH
GW\
tCES tCEH
CE\
(NOTE 2)
tAAS tAAH
ADV\
ADV\ suspends burst.
(Note 4)
(Note 3)
tDS tDH
OE\
D
High-Z
D(A1)
tOEHZ
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(Note 1)
Q
BURST READ
SINGLE WRITE
BURST WRITE
Extended
BURST WRITE
Don’t Care
NOTE:
1. D(A2) refers to output from address A2. D(A2+1) refres to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period
prior to the byte write enable inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BWE\, BWa\ and BWb\ LOW.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
10
SSRAM
AS5SS256K18
READ/WRITE TIMING6
tKC
tKL
CLK
tADSS
tKH
ADSP\
tADSH
ADSC\
tAS
ADDRESS
A1
tAH
BWE\, GW\
BWa\ - BWb\
A4
A3
A2
A5
A6
tWS
tCES
tWH
CE\
(Note 2)
tCEH
ADV\
OE\
D
Q
tDS tDH
High-Z
Q(A1)
tOEHZ
tOELZ
D(A3)
Q(A2)
Back-to-Back READS
(NOTE 5)
D(A5)
tKQ
Q(A4)
SINGLE WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITE’s
BURST READ
Don’t Care
NOTE:
D(A6)
(NOTE 1)
Undefined
1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP\, ADSC\, or ADV\ cycle is performed.
4. GW\ is HIGH.
5. Back-to-back READs may be controlled by either ADSP\ or ADSC\.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
11
SSRAM
AS5SS256K18
MECHANICAL DEFINITIONS
100-Pin TQPF, Micross Case #1001 (Package Designator DQ)
16.00 +0.20/-0.05
14.00 + 0.10
Pin #1 ID
20.10 + 0.10
22.10 + 0.10/-0.15
DETAIL A
0.25
Gage Plane
0.10 +0.10/-0.05
1.00 TYP
0.62
See Detail A
1.40 + 0.05
0.10
0.15 +0.03/-0.02
1.50 + 0.10
NOTE:
0.32 +0.06/-0.10
0.65
0.60 + 0.15
1. All dimensions in Millimeters (MAX/MIN) or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protursion is 0.25mm per side.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
12
SSRAM
AS5SS256K18
ORDERING INFORMATION
100-Pin TQFP
EXAMPLE: AS5SS256K18DQ-8/IT
Package
Device Number
Speed ns Process
Type
AS5SS256K18
DQ
-8
/*
AS5SS256K18
DQ
-9
/*
AS5SS256K18
DQ
-10
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
ET = Enhanced Temperature Range
XT = Military Temperature Range
AS5SS256K18
Rev. 2.5 10/13
-40oC to +85oC
-40oC to +105oC
-55oC to +125oC
Micross Components reserves the right to change products or specifications without notice.
13
SSRAM
AS5SS256K18
DOCUMENT TITLE
256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through
REVISION HISTORY
Rev #
2.2
History
Updated Micross Information
2.3
Added copper lead frame and RoHS
May 2011
compliant options.
Changed:
From
To
4pF
6pF
CI
CO
5pF
8pF
ISB2Z
10mA
45mA
IDDMax (-8) 375mA
225mA
(-9) 325mA
205mA
(-10) 250mA
185mA
ISB2 Max
10mA
90mA
ISB3 Max
25mA
120mA
Deleted CA &CCK specifications. Corrected
pin-out, pin 14 is NC not VSS. Changed VDD
tolerance from +0.3V/-0.165V to ±5%. Deleted
IDDI and IDD4 specs.
Release
2.4
Added DQC package on the Thermal
Resistance table, page 5.
September 2011
Release
2.5
Removed Cu-lead frame option
October 2013
Release
AS5SS256K18
Rev. 2.5 10/13
Release Date
January 2010
Status
Release
Micross Components reserves the right to change products or specifications without notice.
14