CA3130 S E M I C O N D U C T O R BiMOS Operational Amplifier with MOSFET Input/CMOS Output April 1993 Features Description • MOSFET Input Stage Provides: - Very High ZI = 1.5 TΩ (1.5 x 1012Ω) Typ. - Very Low II = 5pA Typ. at 15V Operation = 2pA Typ. at 5V Operation CA3130A and CA3130 are integrated-circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. • Ideal for Single-Supply Applications • Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail • CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails Applications • Ground-Referenced Single Supply Amplifiers Gate-protected p-channel MOSFET (PMOS) transistors are used in the input circuit to provide very-high-input impedance, very-low-input current, and exceptional speed performance. The use of PMOS field-effect transistors in the input stage results in common-mode input-voltage capability down to 0.5 volt below the negative-supply terminal, an important attribute in single-supply applications. A complementary-symmetry MOS (CMOS) transistor-pair, capable of swinging the output voltage to within 10 millivolts of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA3130 Series circuits operate at supply voltages ranging from 5 to 16 volts, or ±2.5 to ±8 volts when using split supplies. They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions can also made to permit strobing of the output stage. • Fast Sample-Hold Amplifiers • Long-Duration Timers/Monostables • High-Input-Impedance Comparators (Ideal Interface with Digital CMOS) • High-Input-Impedance Wideband Amplifiers • Voltage Followers (e.g. Follower for Single-Supply D/A Converter) The CA3130A offers superior input characteristics over those of the CA3130. • Voltage Regulators (Permits Control of Output Voltage Down to Zero Volts) • Peak Detectors • Single-Supply Full-Wave Precision Rectifiers • Photo-Diode Sensor Amplifiers Pinouts Ordering Information CA3130, CA3130A (PDIP, SOIC) TOP VIEW CA3130, CA3130A (CAN) TOP VIEW PHASE COMPENSATION OFFSET NULL INV. INPUT NON-INV. INPUT 1 V- 4 2 3 8 – + STROBE 7 V+ 6 OUTPUT 5 OFFSET NULL TAB PART NUMBER STROBE INV. INPUT 1 NON-INV. INPUT 7 – + 2 4 V+ 6 5 3 PACKAGE CA3130AE -55oC to +125oC 8 Lead PDIP CA3130AM -55oC to +125oC 8 Lead SOIC CA3130AM96 -55oC to +125oC 8 Lead SOIC* 8 OFFSET NULL TEMP. RANGE OUTPUT OFFSET NULL V- AND CASE CA3130AT -55oC to +125oC 8 Pin CAN CA3130BT -55oC to +125oC 8 Pin CAN CA3130E -55oC to +125oC 8 Lead PDIP CA3130M -55oC to +125oC 8 Lead SOIC CA3130M96 -55oC to +125oC 8 Lead SOIC* CA3130T -55oC to +125oC 8 Pin CAN * Denotes Tape and Reel CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 2-108 File Number 817.2 Specifications CA3130, CA3130A Absolute Maximum Ratings Operating Conditions DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . . 16V Differential-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8 V) to (V- -0.5V) Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Device Dissipation: Without Heat SinkUp To 55oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 mW Above 55oC . . . . . . . . . . . . . . . . . . Derate Linearly 6.67 mW/oC With Heat SinkUp To 90οC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Above 90οC . . . . . . . . . . . . . . . . . Derate Linearly 16.7 mW/oC. Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10 Sec.). . . . . . . . . . . . . . . . . +300oC Operating Temperature Range (All Types) . . . . . . . -55oC to +125oC Storage Temperature Range(All Types) . . . . . . . . . -65oC to +150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TA = +25oC, V+ = 15V, V- = 0V (Unless Otherwise Specified) LIMITS CA3130A PARAMETERS SYMBOLS TEST CONDITIONS CA3130 MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO| V± = ±7.5V - 2 5 - 8 15 mV Input Offset Current |IIO| V± = ±7.5V - 0.5 20 - 0.5 30 pA II V± = ±7.5V - 5 30 - 5 50 pA 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB CMRR 80 90 - 70 90 - dB VICR 0 -0.5 to 12 10 0 -0.5 to 12 10 V Input Current Large-Signal Voltage Gain Common-Mode Rejection Ratio Common-Mode Input Voltage Range Power-Supply Rejection Ratio Maximum Output Voltage Maximum Output Current Supply Current Input Offset Voltage Temperature Drift AOL VO = 10 Vp-p RL = 2kΩ ∆VIO/∆V± V± = ±7.5V - 32 150 - 32 320 µV/V VOM+ At RL = 2kΩ 12 13.3 - 12 13.3 - V VOM- At RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V VOM+ At RL = 2kΩ 14.99 15 - 14.99 15 - V VOM- At RL = 2kΩ - 0 0.01 - 0 0.01 V IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA I+ VO = 7.5V, RL = ∞ - 10 15 - 10 15 mA I+ VO = 0V, RL = ∞ - 2 3 - 2 3 mA - 10 - - 10 - µV/oC ∆VIO/∆T NOTE: 1. Short circuit may be applied to ground or to either supply. 2-109 Specifications CA3130, CA3130A Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = +7.5V, V- = -7.5V, TA = +25oC (Unless Otherwise Specified) PARAMETERS SYMBOL Input Offset Voltage Adjustment Range TEST CONDITIONS 10kΩ Across Terms. 4 and 5 or 4 and 1 CA3130A, CA3130 UNITS ±22 mV 1.5 TΩ Input Resistance RI Input Capacitance CI f = 1MHz 4.3 pF Equivalent Input Noise Voltage eN BW = 0.2MHz, RS = 1MΩ* 23 µV CC = 0 15 MHz CC = 47pF 4 MHz Open Loop CC = 0 30 V/µs Closed Loop CC = 56pF 10 V/µs 0.09 µs Unity Gain Crossover Frequency fT Slew Rate: SR Transient Response: CC = 56pF, CL = 25pF, RL = 2kW (Voltage Follower) Rise Time tR Overshoot OS 10 % tS 1.2 µs Settling Time (To <0.1%, VIN = 4VP-P) * Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ. Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = +25oC (Unless Otherwise Specified) PARAMETERS SYMBOL TEST CONDITIONS CA3130A CA3130 UNITS Input Offset Voltage VIO 2 8 mV Input Offset Current IIO 0.1 0.1 pA Input Current II 2 2 pA CMRR 90 80 dB 100 100 kV/V 100 100 dB 0 to 2.8 0 to 2.8 V VO = 5V, RL = ∞ 300 300 µA VO = 2.5V, RL = ∞ 500 500 µA 200 200 µV/V Common-Mode Rejection Ratio Large-Signal Voltage Gain Common-Mode Input Voltage Range Supply Current Power Supply Rejection Ratio AOL VO = 4VP-P, RL = 5kW VICR I+ ∆VIO/∆V+ 2-110 CA3130, CA3130A “CURRENT SOURCE LOAD” FOR Q11 CURRENT SOURCE FOR Q6 AND Q7 BIAS CIRCUIT Q1 Q2 7 V+ Q3 D1 Z1 8.3V D2 R1 D4 Q4 Q5 D3 40kΩ R2 5kΩ SECOND STAGE INPUT STAGE NON-INV. INPUT D5 D6 D7 D8 OUTPUT STAGE 3 + INV.-INPUT 2 Q6 Q8 Q7 OUTPUT - 6 R3 1kΩ R4 1kΩ Q9 Q10 Q12 Q11 R5 1kΩ 5 R6 1kΩ OFFSET NULL 1 COMPENSATION 8 STROBING 4 V- NOTE: DIODES D5 THROUGH D8 PROVIDE GATE-OXIDE PROTECTION FOR MOSFET INPUT STAGE FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3130 SERIES Circuit Description Figure 2 is a block diagram of the CA3130 Series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5 V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 2, provide the total gain of the CA3130. A biasing circuit provides two potentials for common use in the first and second stages. Term. 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Term. 8 is tied to the negative supply rail (Term. 4) by mechanical or electrical means, the output potential at Term. 6 essentially rises to the positive supplyrail potential at Term. 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g.,when the amplifier output is used to drive CMOS digital circuits in Comparator applications). Input Stages The circuit of the CA3130 is shown in Figure 1. It consists of a differential-input stage using PMOS field-effect transistors (Q6, Q7) working into a mirror-pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror-pair transistors also function as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000Ω potentiometer across Terms. 1 and 5 and the potentiometer slider arm to Term. 4. Cascade-connected PMOS transistors Q2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described. The small diodes D5 through D8 provide gate-oxide protection against high-voltage transients, including static electricity during handling for Q6 and Q7. Second-Stage Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascade-connected load resistance provided by 2-111 CA3130, CA3130A PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terms. 1 and 8. A 47picofarad capacitor provides sufficient compensation for stable unity-gain operation in most applications. V+ CA3130 7 200µA 1.35mA 200µA 8mA* 0mA** BIAS CKT. + Bias-Source Circuit 3 Output Stage The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 5. Typical op-amp loads are readily driven by the output stage. Because large-signal excursions are non-linear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01 percent accuracy levels, including the negative supply rail. AV ≈ 6000X AV ≈ 5X OUTPUT AV ≈ 30X 6 2 - V4 5 CC 1 OFFSET NULL 8 STROBE COMPENSATION (WHEN REQUIRED) TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) = 15V *WITH INPUT TERMINALS BIASED SO THAT TERM. 6 POTENTIAL IS +7.5V ABOVE TERM. 4. **WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL. FIGURE 2. BLOCK DIAGRAM OF THE CA3130 SERIES 120 AOL * For general information on the characteristics of CMOS transistorpairs in linear-circuit applications, see File Number 619, data bulletin on CA3600E “CMOS Transistor Array”. SUPPLY VOLTAGE: V+ = 15V; V- = 0 TA = +25oC 100 80 φ OL 4 1 2 2 60 40 -100 3 -200 3 1 -300 4 20 CAPACITANCE: LOAD (CL) = 9pF COMPENSATION (CC) = 0 0 101 102 103 104 105 106 FREQUENCY (Hz) 107 OPEN-LOOP PHASE (DEGREES) At total supply voltages somewhat less than 8.3 volts, zener diode Z1 becomes nonconductive and the potential, developed across series-connected R1, D1-D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply-voltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3 volts. Operation at total supply voltages below about 4.5 volts results in seriously degraded performance. INPUT OPEN-LOOP VOLTAGE GAIN (dB) At total supply voltages, somewhat above 8.3 volts, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3 volts across the series-connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate-bias potential of about 4.5 volts for PMOS transistors Q4 and Q5 with respect to Term. 7. A potential of about 2.2 volts is developed across diode-connected PMOS transistor Q1 with respect to Term. 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is “mirror-connected”* to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200-microampere current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. 108 1 = LOAD RESISTANCE (RL) = ∞ 2 = CL = 30pF, CC = 15pF, RL = 2kΩ 3 = CL = 30pF, CC = 47pF, RL = 2kΩ 4 = CL = 30pF, CC = 150pF, RL = 2kΩ FIGURE 3. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY 2-112 CA3130, CA3130A 17.5 150 OPEN-LOOP VOLTAGE GAIN (dB) 140 130 120 110 100 90 12.5 -50 0 50 TEMPERATURE (oC) 10 17.5 5 2.5 0 QUIESCENT SUPPLY CURRENT (mA) 7.5 5 OUTPUT VOLTAGE HIGH = V+ OR LOW = V2.5 10 12 14 16 TOTAL SUPPLY VOLTAGE (V) VOLTAGE DROP ACROSS NMOS OUTPUT STAGE TRANSISTOR (V) VOLTAGE DROP ACROSS PMOS OUTPUT STAGE TRANSISTOR (V) 10V 15V POSITIVE SUPPLY VOLTAGE = 5V 6 4 2 0.01 8 6 4 2 20 22.5 TA = -55oC +25oC 8 +125oC 6 4 2 2 10 0 2 4 6 8 10 12 14 TOTAL SUPPLY VOLTAGE (V) 16 2 0.001 8 6 4 2 NEGATIVE SUPPLY VOLTAGE = 0V TA = +25oC 15V 10V POSITIVE SUPPLY VOLTAGE = 5V 18 6 4 2 0.1 0.01 8 6 4 8 6 4 2 8 6 4 2 0.001 2 0.001 17.5 FIGURE 7. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 18 0.1 15 50 NEGATIVE SUPPLY VOLTAGE = 0V TA = +25oC 8 6 4 2 12.5 10 18 FIGURE 6. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 10 10 OUTPUT VOLTAGE = V+/2 V- = 0 12 0 0 8 7.5 14 10 6 5 FIGURE 5. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE ∞ 4 2.5 GATE VOLTAGE [TERMS 4 AND 8] (V) LOAD RESISTANCE = TA = +25oC OUTPUT VOLTAGE BALANCED = V+/2 V- = 0 12.5 2 500Ω 7.5 100 FIGURE 4. OPEN-LOOP GAIN vs TEMPERATURE 50 2kΩ 1kΩ 0 80 -100 QUIESCENT SUPPLY CURRENT (mA) SUPPLY VOLTAGE: V+ = 15, V- = 0V TA = +25oC 15 LOAD RESISTANCE = 5kΩ OUTPUT VOLTAGE [TERMS 4 AND 6] (V) LOAD RESISTANCE = 2kΩ 4 68 2 4 68 2 4 68 2 4 68 0.01 0.1 1.0 10 MAGNITUDE OF LOAD CURRENT (mA) 2 4 68 2 100 FIGURE 8. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) vs LOAD CURRENT 2-113 0.001 4 68 2 4 68 2 4 68 2 4 68 0.01 0.1 1 10 MAGNITUDE OF LOAD CURRENT (mA) 2 4 68 100 FIGURE 9. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) vs LOAD CURRENT CA3130, CA3130A As shown in the Table of Electrical Characteristics, the input current for the CA3130 Series Op-Amps is typically 5pA at TA = +25oC when terminals 2 and 3 are at a common-mode potential of +7.5 volts with respect to negative supply Terminal 4. Figure 10 contains data showing the variation of input current as a function of common-mode input voltage at TA = +25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2 volts. As previously noted, the input current is essentially the result of the leakage current through the gate-protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the TO-5 package also contributes an increment of leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to Terminal 4 potential, and the TO-5 case of the CA3130 is also internally tied to Terminal 4, input terminal 3 is essentially “guarded” from spurious leakage currents. input circuit. As with any semiconductor-junction device, including op-amps with a junction-FET input stage, the leakage current approximately doubles for every +10oC increase in temperature. Figure 11 provides data on the typical variation of input bias current as a function of temperature in the CA3130. 4000 2 V+ = 7.5V V- = -7.5V 1000 INPUT CURRENT (pA) Input Current Variation with Common Mode Input Voltage 8 6 4 2 100 8 6 4 2 10 8 6 4 2 1 -80 -60 -40 -20 10 TA = +25oC 0 20 40 60 80 TEMPERATURE (oC) 100 120 140 INPUT VOLTAGE (V) FIGURE 11. INPUT CURRENT vs AMBIENT TEMPERATURE 7.5 In applications requiring the lowest practical input current and incremental increases in current because of “warm-up” effects, it is suggested that an appropriate heat sink be used with the CA3130. In addition, when “sinking” or “sourcing” significant output current the chip temperature increases, causing an increase in the input current. In such cases, heatsinking can also very markedly reduce and stabilize input current variations. 15 VOLTS V+ TO 5 VOLTS 7 5 2 CA3130 PA 6 3 8 2.5 VIN 4 0 VOLTS TO -10 VOLTS Input-Offset-Voltage (VIO) Variation with DC Bias vs Device Operating Life V- 0 -1 0 1 2 3 4 5 6 INPUT CURRENT (pA) 7 FIGURE 10. INPUT CURRENT vs COMMON-MODE VOLTAGE Offset Nulling Offset-voltage nulling is usually accomplished with a 100,000-ohm potentiometer connected across Terms. 1 and 5 and with the potentiometer slider arm connected to Term. 4. A fine offset-null adjustment usually can be effected with the slider arm positioned in the mid-point of the potentiometer's total range. Input-Current Variation with Temperature The input current of the CA3130 Series circuits is typically 5pA at +25oC. The major portion of this input current is due to leakage current through the gate-protective diodes in the It is well known that the characteristics of a MOSFET device can change slightly when a dc gate-source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA3130 should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential dc bias voltage applied across Terms. 2 and 3. Figure 12 shows typical data pertinent to shifts in offset voltage encountered with CA3130 devices (TO-5 package) during life testing. At lower temperatures (TO-5 and plastic), for example at +85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The twovolt dc differential voltage example represents conditions when the amplifier output stage is “toggled”, e.g., as in comparator applications. 2-114 CA3130, CA3130A Power-Supply Considerations 7 OFFSET-VOLTAGE SHIFT (mV) TA = +125oC FOR TO-5 PACKAGES 6 5 DIFFERENTIAL DC VOLTAGE (ACROSS TERMS 2 AND 3) = 2V OUTPUT STAGE TOGGLED 4 3 2 DIFFERENTIAL DC VOLTAGE (ACROSS TERMS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 Because the CA3130 is very useful in single-supply applications, it is pertinent to review some considerations relating to power-supply current consumption under both single-and dual-supply service. Figures 13A and 13B show the CA3130 connected for both dual-and single-supply operation. Dual-supply Operation: When the output voltage at Term. 6 is zero-volts, the currents supplied by the two power supplies are equal. When the gate terminals of Q8 and Q12 are driven increasingly positive with respect to ground, current flow through Q12 (from the negative supply) to the load is increased and current flow through Q8 (from the positive supply) decreases correspondingly. When the gate terminals of Q8 and Q12 are driven increasingly negative with respect to ground, current flow through Q8 is increased and current flow through Q12 is decreased accordingly. TIME (HOURS) FIGURE 12. TYPICAL INCREMENTAL OFFSET-VOLTAGE SHIFT vs OPERATING LIFE POSITIVE SUPPLY + 7 3 CA3130 + Q8 6 Q12 2 RL 4 - 8 NEGATIVE SUPPLY + (A) DUAL POWER-SUPPLY OPERATION POSITIVE SUPPLY + 7 3 CA3130 + Q8 6 Q12 2 - RL 4 8 Single-supply Operation: Initially, let it be assumed that the value of RL is very high (or disconnected), and that the inputterminal bias (Terms. 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops across Q8 and Q12 are of equal magnitude. Figure 6 shows typical quiescent supply-current vs supply-voltage for the CA3130 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply-current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage-transfer characteristics (see Figure 5). If either Q8 or Q12 are swung out of their linear regions toward cut-off (a non-linear region), there will be a corresponding reduction in supply-current. In the extreme case, e.g., with Term. 8 swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply-current to series-connected transistors Q8, Q12 goes essentially to zero. The two preceding stages in the CA3130, however, continue to draw modest supply-current (see the lower curve in Figure 6) even though the output stage is strobed off. Figure 13A shows a dual-supply arrangement for the output stage that can also be strobed off, assuming RL = ∞ by pulling the potential of Term. 8 down to that of Term. 4. Let it now be assumed that a load-resistance of nominal value (e.g., 2 kilohms) is connected between Term. 6 and ground in the circuit of Figure 13B. Let it further be assumed again that the input-terminal bias (Terms. 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8 must now supply quiescent current to both RL and transistor Q12, it should be apparent that under these conditions the supply-current must increase as an inverse function of the RL magnitude. Figure 8 shows the voltage-drop across PMOS transistor Q8 as a function of load current at several supply voltages. Figure 5 shows the voltage-transfer characteristics of the output stage for several values of load resistance. Wideband Noise (B) SINGLE POWER-SUPPLY OPERATION FIGURE 13. CA3130 OUTPUT STAGE IN DUAL AND SINGLE POWER-SUPPLY OPERATION From the standpoint of low-noise performance considerations, the use of the CA3130 is most advantageous in applications where in the source resistance of the input signal is on the order of 1 megohm or more. In this case, the total input-referred noise voltage is typically only 23µV when the 2-115 CA3130, CA3130A +7.5V test-circuit amplifier of Figure 14 is operated at a total supply voltage of 15 volts. This value of total input-referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for values of source resistance very much greater than 1 megohm, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors. 0.01µF 7 3 + 2 - 10kΩ 6 2kΩ 4 8 1 0.01µF -7.5V 25pF CC = 56pF +7.5V 2kΩ 0.01µF Rs BW (-3dB) = 4MHz SR = 10V/µs 7 3 + 2 - 1MΩ 0.1µF NOISE VOLTAGE OUTPUT 6 4 8 1 30.1kΩ 0.01 µF 47pF -7.5V BW (-3dB) = 200kHz TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 23µV TYP. 1kΩ FIGURE 14. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENTS Typical Applications Top Trace: Bottom Trace: Voltage Followers Output Input (A) SMALL-SIGNAL RESPONSE (50mV/DIV. AND 200ns/DIV.) Operational amplifiers with very high input resistances, like the CA3130, are particularly suited to service as voltage followers. Figure 15 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA3130 in a split-supply configuration. A voltage follower, operated from a single supply, is shown in Figure 16, together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 16A with input-signal ramping. The waveforms in Figure 16B show that the follower does not lose its input-to-output phasesense, even though the input is being swung 7.5 volts below ground potential. This unique characteristic is an important attribute in both operational amplifier and comparator applications. Figure 16B also shows the manner in which the CMOS output stage permits the output signal to swing down to the negative supply-rail potential (i.e., ground in the case shown). The digital-to-analog converter (DAC) circuit, described in the following section, illustrates the practical use of the CA3130 in a single-supply voltage-follower application. Top Trace: Center Trace: Bottom Trace: Output Signal (2V/DIV. and 5µs/DIV.) Difference Signal (5mV/DIV. and 5µs/DIV.) Input Signal (2V/DIV. and 5µs/DIV.) (B) INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER) FIGURE 15. SPLIT-SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS 2-116 CA3130, CA3130A +15V 9-Bit COS/MOS DAC A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)* is shown in Figure 17 This system combines the concepts of multiple-switch CMOS lC's, a low-cost ladder network of discrete metal-oxide-film resistors, a CA3130 op-amp connected as a follower, and an inexpensive monolithic regulator in a simple single power-supply arrangement. An additional feature of the DAC is that it is readily interfaced with CMOS input logic, e.g., 10-volt logic levels are used in the circuit of Figure 17. 0.01µF 7 3 + 2 - 10kΩ 6 4 1 8 56pF 5 100kΩ The circuit uses an R/2R voltage-ladder network, with the output potential obtained directly by terminating the ladder arms at either the positive or the negative power-supply terminal. Each CD4007A contains three “inverters”, each “inverter” functioning as a single-pole double-throw switch to terminate an arm of the R/2R network at either the positive or negative power-supply terminal. The resistor ladder is an assembly of one percent tolerance metal-oxide film resistors. The five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000-ohm resistors from the same manufacturing lot. OFFSET ADJUST 2kΩ 0.1µF A single 15-volt supply provides a positive bus for the CA3130 follower amplifier and feeds the CA3085 voltage regulator. A “scale-adjust” function is provided by the regulator output control, set to a nominal 10-volt level in this system. The line-voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in the supply. The flexibility afforded by the COS/MOS building blocks simplifies the design of DAC systems tailored to particular needs. Single-Supply, Absolute-Value, Ideal Full-Wave Rectifier (A) OUTPUT-WAVEFORM WITH INPUT-SIGNAL RAMPING (2V/ DIV. AND 500µs/DIV.) The absolute-value circuit using the CA3130 is shown in Figure 18. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative-going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative-going excursion of the input signal, the CA3130 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 18 is satisfied, the fullwave output is symmetrical. Peak Detectors Top Trace: Bottom Trace: Output (5V/DIV. and 200µs/DIV.) Input Signal (5V/DIV. and 200µs/DIV.) (B) OUTPUT WAVEFORM WITH GROUND-REFERENCE SINEWAVE INPUT FIGURE 16. SINGLE-SUPPLY VOLTAGE-FOLLOWER WITH ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9 IN AN6080) Peak-detector circuits are easily implemented with the CA3130, as illustrated in Figure 19 for both the peak-positive and the peak-negative circuit. It should be noted that with large-signal inputs, the bandwidth of the peak-negative circuit is much less than that of the peak-positive circuit. The second stage of the CA3130 limits the bandwidth in this case. Negative-going output-signal excursion requires a positive-going signal excursion at the collector of transistor Q11, which is loaded by the intrinsic capacitance of the associated circuitry in this mode. On the other hand, during a negative-going signal excursion at the collector of Q11, the transistor functions in an active “pull-down” mode so that the intrinsic capacitance can be discharged more expeditiously. 2-117 CA3130, CA3130A 10V LOGIC INPUTS +10.010 LSB 9 8 7 6 3 10 14 11 6 5 4 3 2 MSB 1 6 3 10 6 3 10 BIT 1 2 3 4 5 6-9 2 CD4007A “SWITCHES” CD4007A “SWITCHES” CD4007A “SWITCHES” ALL RESISTANCES IN OHMS 9 13 1 8 5 13 1 8 5 12 7 4 806K 1% 402K 1% 200K 1% 100K 1% 806K 1% 806K 1% 12 8 5 (2) 806K 1% 806K 1% 750K 1% (4) 806K 1% (8) 806K 1% PARALLELED RESISTORS + OUTPUT +10.010 CA3085 CA3130 6 8 3 LOAD 22 1K 1% 6 7 4 10K 0.001µF 5 3 VOLTAGE FOLLOWER 2 1 8 REGULATED VOLTAGE 1K ADJ 3 83K 1% 4 2µF 25V 1 7 1 - 1% 806K 1% 13 62 2 + 12 806K +15V VOLTAGE REGULATOR +15V REQUIRED RATIO-MATCH STANDARD ±0.1% ±0.2% ±0.4% ±0.8% ±1% ABS 100K OFFSET NULL 2K 56pF 0.1µF FIGURE 17. 18-9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130 R2 2kΩ +15V 0.01 µF R1 7 - 2 4kΩ CA3130 6 + 3 4 IN914 5.1kΩ 5 -0V 1 8 R3 100kΩ OFFSET ADJUST 20pF PEAK ADJUST 2kΩ -0V Gain R 3 = For X R 3 = = R = R R 1 2 = X = 1 ( 1 4k Ω ( R 1 3 + R2 + R3 +X ) −X 2 X 0.5: R 2kΩ 4kΩ 0.75 0.5 = ) = R R 2 1 6k Ω Top Trace: Output Signal (2V/div.) Bottom Trace: Input Signal (10V/div.) Time base on both traces: 0.2ms/div. 20Vp-p Input: BW(-3dB) = 230kHz, DC Output (Avg.) = 3.2V 1Vp-p Input: BW(-3dB) = 130kHz, DC Output (Avg.) = 160mV FIGURE 18. SINGLE-SUPPLY, ABSOLUTE-VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS 2-118 CA3130, CA3130A 6VP-P INPUT; BW(-3dB) = 1.3MHz 6VP-P INPUT; BW(-3dB) = 360kHz +7.5V 0.3 VP-P INPUT; BW(-3dB) = 240kHz 0.3 VP-P INPUT; BW(-3dB) = 320kHz 0.01µF 7 3 10kΩ 2 +7.5V 0.01µF 7 +DC OUTPUT + CA3130 - 3 10kΩ 6 2 IN914 4 + CA3130 - IN914 - 100 kΩ 5µF - 5µF + 0.01µF 0.01µF -7.5V 2kΩ 6 4 + 100 kΩ -DC OUTPUT 2kΩ (A) PEAK POSITIVE DETECTOR CIRCUIT -7.5V (B) PEAK NEGATIVE DETECTOR CIRCUIT FIGURE 19. PEAK-DETECTOR CIRCUITS CURRENT LIMIT ADJ 3Ω + R2 1kΩ IC3 Q5 13 CA3086 10 7 Q4 11 12 Q1 3 Q3 9 8 Q2 6 2 1 14 4 5 + 56pF 5µF 25V 2.2kΩ 0.01µF + - IC2 +20V INPUT OUTPUT 0 TO 13V AT 40mA 20kΩ 1kΩ 390Ω CA3086 10 11 1, 2 Q4 3, 5 Q3 8, 7 6 1 7 6 Q5 12 - 8 25µF Q1 Q2 4 ERROR AMPLIFIER + CA3130 + IC1 3 30kΩ 4 14 13 2 50kΩ R1 62kΩ 100kΩ VOLTAGE ADJUST 0.01 - REGULATION (NO LOAD TO FULL LOAD): < 0.01% INPUT REGULATION: 0.02%/V HUM AND NOISE OUTPUT: < 25µV UP TO 100kHz FIGURE 20. VOLTAGE REGULATOR CIRCUIT (0 TO 13V AT 40mA) 2-119 CA3130, CA3130A 2N3055 1Ω Q2 + + 10kΩ 2N2102 1k CURRENT LIMIT ADJUST Q1 4.3kΩ 1W Q3 3.3kΩ 1W 2N5294 + - +55V INPUT 43kΩ 1000pF 100µF 1 IC2 CA3086 + - 8 2N2102 + 6 Q1 9 8, 7 3 5 Q2 Q3 6 Q5 14 12 13 Q4 ERROR AMPLIFIER 7 10, 11 1, 2 Q4 100µF - 2.2kΩ 5µF + 3 10kΩ CA3130 - IC1 OUTPUT: 0.1 TO 50V AT 1A 2 4 8.2kΩ 4 1kΩ 62kΩ 50kΩ VOLTAGE ADJUST - REGULATION (NO LOAD TO FULL LOAD): < 0.005% INPUT REGULATION: 0.01%/V HUM AND NOISE OUTPUT: < 250µV RMS UP TO 100kHz FIGURE 21. VOLTAGE REGULATOR CIRCUIT (0.1 TO 50V AT 1A) 2-120 CA3130, CA3130A Error-Amplifier in Regulated-Power Supplies The CA3130 is an ideal choice for error-amplifier service in regulated power supplies since it can function as an erroramplifier when the regulated output voltage is required to approach zero. Figure 20 shows the schematic diagram of a 40mA power supply capable of providing regulated output voltage by continuous adjustment over the range from 0 to 13 volts. Q3 and Q4 in lC2 (a CA3086 transistor-array lC) function as zeners to provide supply-voltage for the CA3130 comparator (IC1). Q1, Q2, and Q5 in IC2 are configured as a low impedance, temperature-compensated source of adjustable reference voltage for the error amplifier. Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086 transistor-array lC) are connected in parallel as the series-pass element. Transistor Q5 in lC3 functions as a current-limiting device by diverting base drive from the series-pass transistors, in accordance with the adjustment of resistor R2. Figure 21 contains the schematic diagram of a regulated power-supply capable of providing regulated output voltage by continuous adjustment over the range from 0.1 to 50 volts and currents up to 1 ampere. The error amplifier (lC1) and circuitry associated with lC2 function as previously described, although the output of lC1 is boosted by a discrete transistor (Q4) to provide adequate base drive for the Darlington-connected series-pass transistors Q1, Q2. Transistor Q3 functions in the previously described current-limiting circuit. Another CA3130, IC3, is used as a controlled switch to set the excursion limits of the triangular output from the integrator circuit. Capacitor C2 is a “peaking adjustment” to optimize the high-frequency square-wave performance of the circuit. Potentiometer R3 is adjustable to perfect the “amplitude symmetry” of the square-wave output signals. Output from the threshold detector is fed back via resistor R4 to the input of lC1 so as to toggle the current source from plus to minus in generating the linear triangular wave. Operation with Output-Stage Power-Booster The current-sourcing and-sinking capability of the CA3130 output stage is easily supplemented to provide power-boost capability. In the circuit of Figure 24, three CMOS transistorpairs in a single CA3600E* lC array are shown parallel connected with the output stage in the CA3130. In the Class A mode of CA3600E shown, a typical device consumes 20 mA of supply current at 15V operation. This arrangement boosts the current-handling capability of the CA3130 output stage by about 2.5X. The amplifier circuit in Figure 24 employs feedback to establish a closed-loop gain of 48 dB. The typical large-signal bandwidth (-3dB) is 50 kHz. * See File Number 619 for technical information. Multivibrators +15V The exceptionally high input resistance presented by the CA3130 is an attractive feature for multivibrator circuit design because it permits the use of timing circuits with high R/C ratios. The circuit diagram of a pulse generator (astable multivibrator), with provisions for independent control of the “on” and “off” periods, is shown in Figure 22. Resistors R1 and R2 are used to bias the CA3130 to the mid-point of the supply-voltage and R3 is the feedback resistor. The pulse repetition rate is selected by positioning S1 to the desired position and the rate remains essentially constant when the resistors which determine “on-period” and “off-period” are adjusted. 0.01µF R1 100kΩ 2kΩ Figure 23 contains a schematic diagram of a function generator using the CA3130 in the integrator and threshold detector functions. This circuit generates a triangular or squarewave output that can be swept over a 1,000,000:1 range (0.1 Hz to 100 kHz) by means of a single control, R1. A voltagecontrol input is also available for remote sweep-control. The heart of the frequency-determining system is an operational-transconductance-amplifier (OTA)*, lC1, operated as a voltage-controlled current-source. The output, IO, is a current applied directly to the integrating capacitor, C1, in the feedback loop of the integrator lC2, using a CA3130, to provide the triangular-wave output. Potentiometer R2 is used to adjust the circuit for slope symmetry of positive-going and negative-going signal excursions. 2kΩ R3 100kΩ 7 3 + CA3130 1µF Function Generator OFF-PERIOD ADJUST 1MΩ ON-PERIOD ADJUST 1MΩ R2 100kΩ SI 2 OUTPUT 4 0.1µF 0.01µF 6 2kΩ 0.001µF FREQUENCY RANGE: POSITION OF SI 0.001µF 0.01µF 0.1µF 1µF PULSE PERIOD 4µs to 1ms 40µs to 10ms 0.4µs to 100ms 4µs to 1s FIGURE 22. PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS FOR INDEPENDENT CONTROL OF “ON” AND “OFF” PERIODS. 2-121 CA3130, CA3130A R4 INTEGRATOR C1 270kΩ VOLTAGE-CONTROLLED CURRENT SOURCE +7.5V 3 3kΩ 3kΩ 2 +7.5V 7 IC1 IC1 IO + * CA3080A 4 +7.5V R2 100kΩ -7.5V 5 10MΩ IC3 7 C2 CA3130 + 3 6 3 + 2 CA3130 - 39kΩ 4 -7.5V 150kΩ +7.5V 7 - 2 6 THRESHOLD DETECTOR HIGH - FREQ. ADJUST 3 - 30pF 100pF 8 4 1 +7.5V 5 -7.5V VOLTAGE CONTROLLED INPUT 1 22kΩ SLOPE SYMMETRY 10kΩ ADJUST R3 100kΩ 56pF FREQUENCY ADJUST (100kHz MAX) R1 10kΩ 6 AMPLITUDE SYMMETRY ADJUST -7.5V -7.5V * SEE FILE NUMBER 475 AND AN6668 FOR TECHNICAL INFORMATION FIGURE 23. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL). +15V 0.01µF 14 1MΩ CA3600E* p1 1µF 2 11 p3 p2 7 750kΩ 3 + 2 CA3130 - 2kΩ 1µF 8 6 13 1 3 10 500µF 6 12 4 RL = 100Ω (PO = 150mW AT THD = 10%) 8 AV(CL) = 48 dB n1 LARGE SIGNAL BW(-3 dB) = 50kHz NOTE: TRANSISTORS p1, p2, p3 AND n1, n2, n3 ARE PARALLEL CONNECTED WITH Q8 AND Q12, RESPECTIVELY, OF THE CA3130 5 n2 7 n3 4 9 510kΩ *SEE FILE NUMBER 619 FIGURE 24. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130. 2-122