CY2310BNZ 3.3V SDRAM Buffer for Mobile PCs with Four SO-DIMMs Features Description • One input to 10 output buffer/driver • Supports up to four SDRAM SO-DIMMs • Two additional outputs for feedback • SMBus interface for output control • Low skew outputs • Up to 100 MHz operation • Multiple VDD and VSS pins for noise reduction • Dedicated OE pin for testing • Space-saving 28-pin SSOP package • 3.3V operation The CY2310BNZ is a 3.3V buffer designed to distribute high-speed clocks in mobile PC applications. The part has ten outputs, eight of which can be used to drive up to four SDRAM SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II processors. The CY2310BNZ can be used in conjunction with the CY2281 or similar clock synthesizer for a full Pentium II motherboard solution. The CY2310BNZ also includes an SMBus interface that can enable or disable each output clock. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. Pin Configuration Block Diagram 28-pin SSOP Top View BUF_IN SDATA SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SMBus Decoding SCLOCK 1 2 28 27 3 4 26 25 5 6 7 8 9 10 CY2310BNZ VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM8 VSS VDDIIC SDATA SDRAM0 SDRAM1 SDRAM2 SDRAM3 24 23 22 21 20 19 11 18 12 17 13 14 16 15 VDD SDRAM7 SDRAM6 VSS VDD SDRAM5 SDRAM4 VSS OE VDD SDRAM9 VSS VSSIIC SCLOCK OE Cypress Semiconductor Corporation Document #: 38-07260 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 28, 2003 CY2310BNZ Pin Description Pins Name Description 1, 5, 10, 19, 24, 28 VDD 3.3V Digital voltage supply 4, 8, 12, 17, 21, 25 VSS Ground 13 VDDIIC SMBus Voltage supply 16 VSSIIC Ground for SMBus 9 BUF_IN Input clock 20 OE Output Enable, three-states outputs when LOW. Internal pull-up to VDD 14 SDATA SMBus data input, internal pull-up to VDD 15 SCLK SMBus clock input, internal pull-up to VDD 2, 3, 6, 7 SDRAM [0–3] SDRAM byte 0 clock outputs 22, 23, 26, 27 SDRAM [4–7] SDRAM byte 1 clock outputs 11, 18 SDRAM [8–9] SDRAM byte 2 clock outputs Device Functionality OE SDRAM [0–17] 0 High-Z 1 Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit 1 x BUF_IN Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Pin # Description Bit 7 27 SDRAM7 (Active/Inactive) Bit 6 26 SDRAM6 (Active/Inactive) Bit 5 23 SDRAM5 (Active/Inactive) Bit 4 22 SDRAM4 (Active/Inactive) Bit 3 – Initialize to 0 Bit 2 – Initialize to 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Bit 1 – Initialize to 0 . Bit 0 – Initialize to 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0.” • SMBus Address for the CY2310BNZ is: Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description A6 A5 A4 A3 A2 A1 A0 R/W Bit 7 18 SDRAM9 (Active/Inactive) 1 1 0 1 0 0 1 ---- Bit 6 11 SDRAM8 (Active/Inactive) Bit 5 – Reserved, drive to 0 Bit 4 – Reserved, drive to 0 Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description Bit 3 – Reserved, drive to 0 Bit 7 – Initialize to 0 Bit 2 – Reserved, drive to 0 Bit 6 – Initialize to 0 Bit 1 – Reserved, drive to 0 Bit 5 – Initialize to 0 Bit 0 – Reserved, drive to 0 Bit 4 – Initialize to 0 Bit 3 7 SDRAM3 (Active/Inactive) Bit 2 6 SDRAM2 (Active/Inactive) Bit 1 3 SDRAM1 (Active/Inactive) Bit 0 2 SDRAM0 (Active/Inactive) Document #: 38-07260 Rev. *A Page 2 of 6 CY2310BNZ Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 7.0 V VIN Input Voltage Relative to V SS –0.5 VDD+0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 85 °C TJ Temperature, Junction Functional ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL–94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level 150 °C 32.24 °C/W 98.31 °C/W 2000 Volts V–0 1 ppm DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V at 64MHz 100 180 mA at 100 MHz 150 220 mA – 10 mA V VDD Supply Voltage @3.3V± 5% IDD1 3.3V Supply Current IDD2 3.3V Supply Current IDD Tristate 3.3V Supply Current in Three-State Logic Inputs VIL Input Low Voltage VSS–0.3 0.8 VIH Input High Voltage 2.0 VDD+0.5 V IIL1 Input Leakage Current, BUF_IN –5 +5 µA IIL2 Input Leakage Current[1] –20 +5 µA Logic Outputs (SDRAM0:9)[2] VOL Output Low Voltage IOL = 1 mA – 50 mV VOH Output High Voltage IOH = –1 mA 3.1 – V IOL Output Low Current VOL = 1.5V 70 185 mA IOH Output High Current VOH = 1.5V 65 160 mA pF Pin Capacitance/Inductance CIN Input Pin Capacitance – 5 COUT Output Pin Capacitance – 6 pF LIN Input Pin Inductance – 7 nH CLOAD Input Load Capacitance 20 30 pF AC Electrical Specifications Parameter Description Test Condition Min. Max. Unit 0 133 MHz Measured from 0.4V to 2.4V 1.5 4.0 V/ns Measured from 2.4V to 0.4V 1.5 4.0 V/ns FIN Input Frequency at 64 MHz TR Output Rise Edge Rate TF Output Fall Edge Rate TSR Output Skew, Rising Edges 200 ps TSF Output Skew, Falling Edges 200 ps TEN Output Enable Time 1.0 8.0 ns TDIS Output Disable Time 1.0 8.0 ns Notes: 1. OE, SDATA, and SCLOCK logic pins have a 250-kΩ internal pull-up resistor (VDD – 0.8V). 2. All SDRAM outputs loaded by 6" transmission lines with 22-pF capacitors on ends. Document #: 38-07260 Rev. *A Page 3 of 6 CY2310BNZ AC Electrical Specifications (continued) Parameter Description Test Condition tPR Rising Edge Propagation Delay TPF Falling Edge Propagation Delay TDC Duty Cycle Zo AC Output Impedance Measured at 1.5V Min. Max. Unit 3.0 5.0 ns 3.0 5.0 ns 50 60 % Ω Test Circuit VDD 0.1 µF CLK out OUTPUTS CLOAD GND Figure 1. Test Circuit Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Rs BUF_IN CPUCLK PCICLK USBCLK Rs SDRAM REF SDATA APIC SCLK Ct VDD 3.3V VDD CY2281 SSOP 28 This frequency synthesizer is used to generate CPU, PCL,USB, REF and APIC Clocks VSS Cd 0.1uF CY2310BNZ SSOP 28 Cd = Decoupling Capacitor Ct = Optional EMI-Reducing Capacitor Rs = Series Terminating Resistors Summary • Surface mount, low-ESR ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series-terminating resistor satisfies the following equation where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the Document #: 38-07260 Rev. *A buffer (typically 25W), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead Page 4 of 6 CY2310BNZ offers greater than 50W impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Ordering Information Ordering Code Package Type Operating Range CY2310BNZPVC–1 28-pin SSOP Commercial, 0 °C to 70°C CY2310BNZPVC–1T 28-pin SSOP – Tape and Reel Commercial, 0 °C to 70°C CY2310BNZPVI–1 28-pin SSOP Industrial, –40 °C to 85°C CY2310BNZPVI–1T 28-pin SSOP – Tape and Reel Industrial, –40 °C to 85°C Package Drawing and Dimension 28-lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Pentium II is a registered trademarks of Intel Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07260 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2310BNZ Document History Page Document Title: CY2310BNZ 3.3V 3.3V SDRAM Buffer for Mobile PCs with Four SO-DIMMs Document Number: 38-07260 ECN NO. Issue Date ** 110525 02/07/02 SZV Change from Spec number: 38-01089 to 38-07260 *A 121577 01/29/03 RGL Corrected the ordering information to match the devmaster. Changed the max value of the VDD Core Supply in the Absolute Maximum Conditions table from 4.6V to 7.0V REV. Document #: 38-07260 Rev. *A Orig. of Change Description of Change Page 6 of 6