1CY2310NZCY2310 NZCY2310ANZ CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Features Functional Description • One input to 10 output buffer/driver • Supports up to four SDRAM SO-DIMMs • Two additional outputs for feedback • Serial interface for output control • Low skew outputs • Up to 100-MHz operation • Multiple VDD and VSS pins for noise reduction • Dedicated OE pin for testing • Space-saving 28-pin SSOP package • 3.3V operation The CY2310ANZ is a 3.3V buffer designed to distribute high-speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II® processors. The CY2310ANZ can be used in conjunction with the CY2281 or similar clock synthesizer for a full Pentium II motherboard solution. The CY2310ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. Pin Configuration Block Diagram 28-pin SSOP Top View BUF_IN VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM8 VSS VDDIIC SDATA SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDATA Serial Interface Decoding SCLOCK SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 1 2 28 27 3 26 4 25 5 6 24 23 7 22 8 9 21 20 10 19 11 18 12 17 13 16 14 15 VDD SDRAM7 SDRAM6 VSS VDD SDRAM5 SDRAM4 VSS OE VDD SDRAM9 VSS VSSIIC SCLOCK OE Cypress Semiconductor Corporation Document #: 38-07142 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY2310ANZ Pin Summary Name Pins Description VDD 1, 5, 10, 19, 24, 28 3.3V Digital voltage supply VSS 4, 8, 12, 17, 21, 25 Ground VDDIIC 13 Serial interface voltage supply VSSIIC 16 Ground for serial interface BUF_IN 9 Input clock OE 20 Output Enable, three-states outputs when LOW. Internal pull-up to VDD SDATA 14 Serial data input, internal pull-up to VDD SCLK 15 Serial clock input, internal pull-up to VDD SDRAM [0–3] 2, 3, 6, 7 SDRAM byte 0 clock outputs SDRAM [4–7] 22, 23, 26, 27 SDRAM byte 1 clock outputs SDRAM [8–9] 11, 18 SDRAM byte 2 clock outputs Device Functionality OE SDRAM [0–17] 0 High-Z 1 1 x BUF_IN Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description . Bit 7 27 SDRAM7 (Active/Inactive) Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Bit 6 26 SDRAM6 (Active/Inactive) Bit 5 23 SDRAM5 (Active/Inactive) Bit 4 22 SDRAM4 (Active/Inactive) Bit 3 -- Initialize to 0 • Reserved and unused bits should be programmed to “0”. • Serial interface address for the CY2310ANZ is: A6 A5 A4 A3 A2 A1 A0 R/W Bit 2 -- Initialize to 0 1 1 0 1 0 0 1 ---- Bit 1 -- Initialize to 0 Bit 0 -- Initialize to 0 Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enabled Bit Pin # Description Byte 2: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit 7 -- Initialize to 0 Bit 7 18 SDRAM9 (Active/Inactive) Bit 6 -- Initialize to 0 Bit 6 11 SDRAM8 (Active/Inactive) Bit 5 -- Initialize to 0 Bit 5 -- Reserved, drive to 0 Bit 4 -- Initialize to 0 Bit 4 -- Reserved, drive to 0 Bit 3 7 SDRAM3 (Active/Inactive) Bit 3 -- Reserved, drive to 0 Bit 2 6 SDRAM2 (Active/Inactive) Bit 2 -- Reserved, drive to 0 Bit 1 3 SDRAM1 (Active/Inactive) Bit 1 -- Reserved, drive to 0 Bit 0 2 SDRAM0 (Active/Inactive) Bit 0 -- Reserved, drive to 0 Document #: 38-07142 Rev. *B Page 2 of 8 CY2310ANZ Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V Storage Temperature ................................. –65°C to +150°C DC Input Voltage (Except BUF_IN)........–0.5V to VDD + 0.5V Junction Temperature ................................................. 150°C DC Input Voltage (BUF_IN)............................ –0.5V to +7.0V Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions Parameter Description Min. Max. Unit 3.135 3.465 V VDD Supply Voltage TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance 20 30 pF CIN Input Capacitance 7 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Min. Max. Unit Electrical Characteristics Parameter Description Voltage[1] Test Conditions VIL Input LOW VILiic Input LOW Voltage VIH Input HIGH Voltage[1] IIL Input LOW Current (BUF_IN input) VIN = 0V IIL Input LOW Current (Except BUF_IN Pin) VIN = 0V IIH Input HIGH Current VIN = VDD VOL VOH Except serial interface pins 0.8 V For serial interface pins only 0.7 V 2.0 Output LOW Voltage[2] IOL = 25 mA Output HIGH Voltage[2] IOH = –36 mA Current[2] IDD Supply IDD Supply Current Current[2] –10 –10 V 10 µA 100 µA 10 µA 0.4 V 2.4 V Unloaded outputs, 100-MHz 200 mA Loaded outputs, 100-MHz 360 mA Unloaded outputs, 66.67-MHz 150 mA IDD Supply IDD Supply Current Loaded outputs, 66.67-MHz 230 mA IDDS Supply Current BUF_IN=VDD or VSS All other inputs at VDD 500 µA Notes: 1. BUF_IN input has a threshold voltage of VDD/2. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07142 Rev. *B Page 3 of 8 CY2310ANZ Switching Characteristics[3] Parameter Name Test Conditions Min. Typ. Maximum Operating Frequency Duty Cycle[2, 4] = t2 ÷ t1 MHz Measured at 1.5V 45.0 50.0 55.0 % Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns [2] 0.9 t4 Falling Edge Rate Measured between 2.4V and 0.4V t5 Output to Output Skew[2] All outputs equally loaded 1.5 4.0 V/ns 150 250 ps [2] Input edge greater than 1 V/ns 1.0 3.5 5.0 ns [2] 3.5 5.0 ns SDRAM Buffer LH Prop. Delay t6 Unit 100 [2] Rising Edge Rate t3 Max. t7 SDRAM Buffer HL Prop. Delay Input edge greater than 1 V/ns 1.0 t8 [2] SDRAM Buffer Enable Delay Input edge greater than 1 V/ns 1.0 5 12 ns t9 SDRAM Buffer Disable Delay[2] Input edge greater than 1 V/ns 1.0 20 30 ns Switching Waveforms Duty Cycle Timing t1 t2 1.5V 1.5V 1.5V All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V 2.4V 0.4V 3.3V 0V t4 t3 Output-Output Skew OUTPUT 1.5V 1.5V OUTPUT t5 Notes: 3. All parameters specified with loaded outputs. 4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns Document #: 38-07142 Rev. *B Page 4 of 8 CY2310ANZ Switching Waveforms (continued) SDRAM Buffer LH and HL Propagation Delay INPUT OUTPUT t6 t7 SDRAM Buffer Enable and Disable Times OE Three-State Active OUTPUTS t8 t9 Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD GND Document #: 38-07142 Rev. *B Page 5 of 8 CY2310ANZ Application Information Clock traces must be terminated with either series or parallel termination, as is normally done. Summary • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF–22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07142 Rev. *B Page 6 of 8 CY2310ANZ Ordering Information Ordering Code Operating Range Package Type Standard CY2310ANZPVC–1 28-pin SSOP Commercial CY2310ANZPVC–1T 28-pin SSOP - Tape and Reel Commercial CY2310ANZPVXC–1 28-pin SSOP Commercial CY2310ANZPVXC–1T 28-pin SSOP - Tape and Reel Commercial Lead-free Package Diagram 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Pentium II is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07142 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2310ANZ Document History Page Document Title: CY2310ANZ 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs Document Number: 38-07142 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110251 11/18/01 DSG Change from Spec number: 38-00659 to 38-07142 *A 121829 12/14/02 RBI Power up requirements added to Operating Conditions Information *B 310555 See ECN RGL Added Lead-free Devices Document #: 38-07142 Rev. *B Page 8 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.