ETC CY54FCT244CTLMB

CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
D
D
D
D
D
D
D
D
OEA
DA0
OB0
DA1
OB1
DA2
OB2
DA3
OB3
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OEB
OA0
DB0
OA1
DB1
OA2
DB2
OA3
DB3
CY54FCT244T . . . L PACKAGE
(TOP VIEW)
OB0
DA0
OEA
VCC
OEB
D
CY54FCT244T . . . D PACKAGE
CY74FCT244T . . . P, Q, OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
CY54FCT244T
– 48-mA Output Sink Current
12-mA Output Source Current
CY74FCT244T
– 64-mA Output Sink Current
32-mA Output Source Current
3-State Outputs
DA1
OB1
DA2
OB2
DA3
4
3
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
OA0
DB0
OA1
DB1
OA2
OB 3
GND
DB 3
OA 3
DB 2
D
description
The ’FCT244T devices are octal buffers and line drivers designed to be employed as memory address drivers,
clock drivers, and bus-oriented transmitters/receivers. These devices provide speed and drive capabilities
equivalent to their fastest bipolar logic counterparts, while reducing power consumption. The input and output
voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
ORDERING INFORMATION
QSOP – Q
0°C to 70°C
TOP-SIDE
MARKING
3.6
CY74FCT244DTQCT
Tube
3.6
CY74FCT244DTSOC
Tape and reel
3.6
CY74FCT244DTSOCT
Tube
4.1
CY74FCT244CTSOC
Tape and reel
4.1
CY74FCT244CTSOCT
QSOP – Q
Tape and reel
4.1
CY74FCT244CTQCT
FCT244C
DIP – P
Tube
4.6
CY74FCT244ATPC
CY74FCT244ATPC
Tube
4.6
CY74FCT244ATSOC
Tape and reel
4.6
CY74FCT244ATSOCT
Tape and reel
4.6
CY74FCT244ATQCT
Tube
6.5
CY74FCT244TSOC
Tape and reel
6.5
CY74FCT244TSOCT
QSOP – Q
Tape and reel
6.5
CY74FCT244TQCT
CDIP – D
Tube
4.6
CY54FCT244CTDMB
LCC – L
Tube
4.6
CY54FCT244CTLMB
CDIP – D
Tube
5.1
CY54FCT244ATDMB
LCC – L
Tube
5.1
CY54FCT244ATLMB
CDIP – D
Tube
7
CY54FCT244TDMB
SOIC – SO
SOIC – SO
QSOP – Q
SOIC – SO
–55°C
55°C to 125°C
ORDERABLE
PART NUMBER
Tape and reel
SOIC – SO
40°C to 85°C
–40°C
SPEED
(ns)
PACKAGE†
TA
FCT244D
FCT244D
FCT244C
FCT244A
FCT244A
FCT244
FCT244
LCC – L
Tube
7
CY54FCT244TLMB
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OEA
OEB
D
OUTPUT
O
L
L
L
L
L
L
H
H
H
H
X
Z
H = High logic level, L = Low logic level,
X = Don’t care, Z = High-impedance state
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
logic diagram (positive logic)
OEA
1
2
18
DA1
4
16
DA2
6
14
8
12
DA0
DA3
OEB
DB0
DB1
DB2
DB3
OA0
OA1
OA2
OA3
19
17
3
15
5
13
7
11
9
OB0
OB1
OB2
OB3
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
recommended operating conditions (see Note 2)
CY54FCT244T
CY74FCT244DT
CY74FCT244T
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
4.75
5
5.25
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
0.8
0.8
V
High-level output current
–12
–32
–32
mA
IOL
TA
Low-level output current
48
64
64
mA
85
°C
High-level input voltage
Operating free-air temperature
2
–55
2
125
0
2
70
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
4
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–40
V
V
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
CY54FCT244T
TYP† MAX
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.75 V,
IIN = –18 mA
IIN = –18 mA
VCC = 4.5 V,
IOH = –12 mA
IOH = –32 mA
VCC = 4
4.75
75 V
MIN
–0.7
–1.2
–0.7
2.4
2.4
Vhys
All inputs
II
VCC = 5.5 V,
VCC = 5.25 V,
VIN = VCC
VIN = VCC
5
IIH
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 2.7 V
VIN = 2.7 V
±1
IIL
VCC = 5.5 V,
VCC = 5.25 V,
VIN = 0.5 V
VIN = 0.5 V
±1
IOZH
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 2.7 V
VOUT = 2.7 V
10
IOZL
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0.5 V
VOUT = 0.5 V
–10
IOS‡
VCC = 5.5 V,
VCC = 5.25 V,
VOUT = 0 V
VOUT = 0 V
VCC = 0 V,
VCC = 5.5 V,
VOUT = 4.5 V
VIN ≤ 0.2 V,
∆ICC
0.3
3.3
0.55
IOL = 64 mA
0.3
0.2
0.55
0.2
±1
±1
10
–10
–120
–225
–60
–120
±1
VIN ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V
VCC = 5.25 V,
VIN ≤ 0.2 V,
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
0.1
0.5
VCC = 5.5 V, One input switching at 50% duty cycle,
Outputs open, OEA = OEB = GND,
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
0.06
V
V
5
–60
V
V
2
IOH = –15 mA
IOL = 48 mA
VCC = 4.5 V,
VCC = 4.75 V,
ICC
–1.2
UNIT
3.3
VOL
Ioff
CY74FCT244T
TYP† MAX
MIN
–225
±1
0.2
0.1
0.2
0.5
2
2
µA
µA
µA
µA
µA
mA
µA
mA
mA
0.12
mA/
MHz
VCC = 5.25 V, One input switching at 50% duty cycle,
Outputs open, OEA = OEB = GND,
0.06
0.12
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
ICCD¶
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
CY54FCT244T
TYP† MAX
TEST CONDITIONS
MIN
One bit switching VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
at f1 = 10 MHz
at 50% duty cycle V = 3.4 V or GND
IN
IC#
VCC = 5.5 V,
Outputs open,
Eight bits
VIN = 0.2 V or
OEA = OEB = GND switching
VIN ≥ VCC – 0.2 V
at f1 = 2.5
2 5 MHz
at 50% duty cycle VIN = 3.4 V or GND
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
UNIT
mA
One bit switching VIN ≤ 0.2 V or
VIN ≥ VCC – 0.2 V
at f1 = 10 MHz
at 50% duty cycle V = 3.4 V or GND
IN
VCC = 5.25 V,
Outputs open,
Eight bits
VIN = 0.2 V or
OEA = OEB = GND switching
VIN ≥ VCC – 0.2 V
at f1 = 2.5
2 5 MHz
at 50% duty cycle VIN = 3.4 V or GND
0.7
1.4
1
2.4
1.3
2.6||
3.3
10.6||
Ci
5
10
5
10
pF
Co
9
12
9
12
pF
† Typical values are at VCC = 5 V, TA = 25°C.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
= Total supply current
IC
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
6
CY74FCT244T
TYP† MAX
MIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
CY54FCT244T
CY54FCT244AT
CY54FCT244CT
MIN
MAX
MIN
MAX
MIN
MAX
1.5
7
1.5
5.1
1.5
4.6
1.5
7
1.5
5.1
1.5
4.6
1.5
8.5
1.5
6.5
1.5
6.5
1.5
8.5
1.5
6.5
1.5
6.5
1.5
7.5
1.5
5.9
1.5
5.7
1.5
7.5
1.5
5.9
1.5
5.7
UNIT
ns
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
O
tPZH
tPZL
OE
O
tPHZ
tPLZ
OE
O
CY74FCT244T
CY74FCT244AT
CY74FCT244CT
CY74FCT244DT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
6.5
1.5
4.6
1.5
4.1
1.5
3.6
1.5
6.5
1.5
4.6
1.5
4.1
1.5
3.6
1.5
8
1.5
6.2
1.5
5.8
1.5
4.8
1.5
8
1.5
6.2
1.5
5.8
1.5
4.8
1.5
7
1.5
5.6
1.5
5.2
1.5
4
1.5
7
1.5
5.6
1.5
5.2
1.5
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
7
CY54FCT244T, CY74FCT244T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS071 – OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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• DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright  2001, Texas Instruments Incorporated